1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 20ebc4cdaSBenjamin Herrenschmidt/* 30ebc4cdaSBenjamin Herrenschmidt * This file contains the 64-bit "server" PowerPC variant 40ebc4cdaSBenjamin Herrenschmidt * of the low level exception handling including exception 50ebc4cdaSBenjamin Herrenschmidt * vectors, exception return, part of the slb and stab 60ebc4cdaSBenjamin Herrenschmidt * handling and other fixed offset specific things. 70ebc4cdaSBenjamin Herrenschmidt * 80ebc4cdaSBenjamin Herrenschmidt * This file is meant to be #included from head_64.S due to 925985edcSLucas De Marchi * position dependent assembly. 100ebc4cdaSBenjamin Herrenschmidt * 110ebc4cdaSBenjamin Herrenschmidt * Most of this originates from head_64.S and thus has the same 120ebc4cdaSBenjamin Herrenschmidt * copyright history. 130ebc4cdaSBenjamin Herrenschmidt * 140ebc4cdaSBenjamin Herrenschmidt */ 150ebc4cdaSBenjamin Herrenschmidt 167230c564SBenjamin Herrenschmidt#include <asm/hw_irq.h> 178aa34ab8SBenjamin Herrenschmidt#include <asm/exception-64s.h> 1846f52210SStephen Rothwell#include <asm/ptrace.h> 197cba160aSShreyas B. Prabhu#include <asm/cpuidle.h> 20da2bc464SMichael Ellerman#include <asm/head-64.h> 212c86cd18SChristophe Leroy#include <asm/feature-fixups.h> 22890274c2SMichael Ellerman#include <asm/kup.h> 238aa34ab8SBenjamin Herrenschmidt 2415820091SNicholas Piggin/* PACA save area offsets (exgen, exmc, etc) */ 2515820091SNicholas Piggin#define EX_R9 0 2615820091SNicholas Piggin#define EX_R10 8 2715820091SNicholas Piggin#define EX_R11 16 2815820091SNicholas Piggin#define EX_R12 24 2915820091SNicholas Piggin#define EX_R13 32 3015820091SNicholas Piggin#define EX_DAR 40 3115820091SNicholas Piggin#define EX_DSISR 48 3215820091SNicholas Piggin#define EX_CCR 52 3315820091SNicholas Piggin#define EX_CFAR 56 3415820091SNicholas Piggin#define EX_PPR 64 3515820091SNicholas Piggin#if defined(CONFIG_RELOCATABLE) 3615820091SNicholas Piggin#define EX_CTR 72 3715820091SNicholas Piggin.if EX_SIZE != 10 3815820091SNicholas Piggin .error "EX_SIZE is wrong" 3915820091SNicholas Piggin.endif 4015820091SNicholas Piggin#else 4115820091SNicholas Piggin.if EX_SIZE != 9 4215820091SNicholas Piggin .error "EX_SIZE is wrong" 4315820091SNicholas Piggin.endif 4415820091SNicholas Piggin#endif 4515820091SNicholas Piggin 460ebc4cdaSBenjamin Herrenschmidt/* 4712a04809SNicholas Piggin * We're short on space and time in the exception prolog, so we can't 4812a04809SNicholas Piggin * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 4912a04809SNicholas Piggin * Instead we get the base of the kernel from paca->kernelbase and or in the low 5012a04809SNicholas Piggin * part of label. This requires that the label be within 64KB of kernelbase, and 5112a04809SNicholas Piggin * that kernelbase be 64K aligned. 5212a04809SNicholas Piggin */ 5312a04809SNicholas Piggin#define LOAD_HANDLER(reg, label) \ 5412a04809SNicholas Piggin ld reg,PACAKBASE(r13); /* get high part of &label */ \ 5512a04809SNicholas Piggin ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label) 5612a04809SNicholas Piggin 5712a04809SNicholas Piggin#define __LOAD_HANDLER(reg, label) \ 5812a04809SNicholas Piggin ld reg,PACAKBASE(r13); \ 5912a04809SNicholas Piggin ori reg,reg,(ABS_ADDR(label))@l 6012a04809SNicholas Piggin 6112a04809SNicholas Piggin/* 6212a04809SNicholas Piggin * Branches from unrelocated code (e.g., interrupts) to labels outside 6312a04809SNicholas Piggin * head-y require >64K offsets. 6412a04809SNicholas Piggin */ 6512a04809SNicholas Piggin#define __LOAD_FAR_HANDLER(reg, label) \ 6612a04809SNicholas Piggin ld reg,PACAKBASE(r13); \ 6712a04809SNicholas Piggin ori reg,reg,(ABS_ADDR(label))@l; \ 6812a04809SNicholas Piggin addis reg,reg,(ABS_ADDR(label))@h 6912a04809SNicholas Piggin 7012a04809SNicholas Piggin/* Exception register prefixes */ 7112a04809SNicholas Piggin#define EXC_HV 1 7212a04809SNicholas Piggin#define EXC_STD 0 7312a04809SNicholas Piggin 7412a04809SNicholas Piggin#if defined(CONFIG_RELOCATABLE) 7512a04809SNicholas Piggin/* 7612a04809SNicholas Piggin * If we support interrupts with relocation on AND we're a relocatable kernel, 7712a04809SNicholas Piggin * we need to use CTR to get to the 2nd level handler. So, save/restore it 7812a04809SNicholas Piggin * when required. 7912a04809SNicholas Piggin */ 8012a04809SNicholas Piggin#define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 8112a04809SNicholas Piggin#define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 8212a04809SNicholas Piggin#define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 8312a04809SNicholas Piggin#else 8412a04809SNicholas Piggin/* ...else CTR is unused and in register. */ 8512a04809SNicholas Piggin#define SAVE_CTR(reg, area) 8612a04809SNicholas Piggin#define GET_CTR(reg, area) mfctr reg 8712a04809SNicholas Piggin#define RESTORE_CTR(reg, area) 8812a04809SNicholas Piggin#endif 8912a04809SNicholas Piggin 9012a04809SNicholas Piggin/* 9112a04809SNicholas Piggin * PPR save/restore macros used in exceptions-64s.S 9212a04809SNicholas Piggin * Used for P7 or later processors 9312a04809SNicholas Piggin */ 9412a04809SNicholas Piggin#define SAVE_PPR(area, ra) \ 9512a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(940) \ 9612a04809SNicholas Piggin ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \ 9712a04809SNicholas Piggin std ra,_PPR(r1); \ 9812a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 9912a04809SNicholas Piggin 10012a04809SNicholas Piggin#define RESTORE_PPR_PACA(area, ra) \ 10112a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(941) \ 10212a04809SNicholas Piggin ld ra,area+EX_PPR(r13); \ 10312a04809SNicholas Piggin mtspr SPRN_PPR,ra; \ 10412a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 10512a04809SNicholas Piggin 10612a04809SNicholas Piggin/* 10712a04809SNicholas Piggin * Get an SPR into a register if the CPU has the given feature 10812a04809SNicholas Piggin */ 10912a04809SNicholas Piggin#define OPT_GET_SPR(ra, spr, ftr) \ 11012a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 11112a04809SNicholas Piggin mfspr ra,spr; \ 11212a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 11312a04809SNicholas Piggin 11412a04809SNicholas Piggin/* 11512a04809SNicholas Piggin * Set an SPR from a register if the CPU has the given feature 11612a04809SNicholas Piggin */ 11712a04809SNicholas Piggin#define OPT_SET_SPR(ra, spr, ftr) \ 11812a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 11912a04809SNicholas Piggin mtspr spr,ra; \ 12012a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 12112a04809SNicholas Piggin 12212a04809SNicholas Piggin/* 12312a04809SNicholas Piggin * Save a register to the PACA if the CPU has the given feature 12412a04809SNicholas Piggin */ 12512a04809SNicholas Piggin#define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 12612a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(943) \ 12712a04809SNicholas Piggin std ra,offset(r13); \ 12812a04809SNicholas PigginEND_FTR_SECTION_NESTED(ftr,ftr,943) 12912a04809SNicholas Piggin 13012a04809SNicholas Piggin.macro EXCEPTION_PROLOG_0 area 13112a04809SNicholas Piggin GET_PACA(r13) 13212a04809SNicholas Piggin std r9,\area\()+EX_R9(r13) /* save r9 */ 13312a04809SNicholas Piggin OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR) 13412a04809SNicholas Piggin HMT_MEDIUM 13512a04809SNicholas Piggin std r10,\area\()+EX_R10(r13) /* save r10 - r12 */ 13612a04809SNicholas Piggin OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 13712a04809SNicholas Piggin.endm 13812a04809SNicholas Piggin 13912a04809SNicholas Piggin.macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask 14012a04809SNicholas Piggin OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR) 14112a04809SNicholas Piggin OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR) 14212a04809SNicholas Piggin INTERRUPT_TO_KERNEL 14312a04809SNicholas Piggin SAVE_CTR(r10, \area\()) 14412a04809SNicholas Piggin mfcr r9 14512a04809SNicholas Piggin .if \kvm 14612a04809SNicholas Piggin KVMTEST \hsrr \vec 14712a04809SNicholas Piggin .endif 14812a04809SNicholas Piggin .if \bitmask 14912a04809SNicholas Piggin lbz r10,PACAIRQSOFTMASK(r13) 15012a04809SNicholas Piggin andi. r10,r10,\bitmask 15112a04809SNicholas Piggin /* Associate vector numbers with bits in paca->irq_happened */ 15212a04809SNicholas Piggin .if \vec == 0x500 || \vec == 0xea0 15312a04809SNicholas Piggin li r10,PACA_IRQ_EE 15412a04809SNicholas Piggin .elseif \vec == 0x900 15512a04809SNicholas Piggin li r10,PACA_IRQ_DEC 15612a04809SNicholas Piggin .elseif \vec == 0xa00 || \vec == 0xe80 15712a04809SNicholas Piggin li r10,PACA_IRQ_DBELL 15812a04809SNicholas Piggin .elseif \vec == 0xe60 15912a04809SNicholas Piggin li r10,PACA_IRQ_HMI 16012a04809SNicholas Piggin .elseif \vec == 0xf00 16112a04809SNicholas Piggin li r10,PACA_IRQ_PMI 16212a04809SNicholas Piggin .else 16312a04809SNicholas Piggin .abort "Bad maskable vector" 16412a04809SNicholas Piggin .endif 16512a04809SNicholas Piggin 16612a04809SNicholas Piggin .if \hsrr 16712a04809SNicholas Piggin bne masked_Hinterrupt 16812a04809SNicholas Piggin .else 16912a04809SNicholas Piggin bne masked_interrupt 17012a04809SNicholas Piggin .endif 17112a04809SNicholas Piggin .endif 17212a04809SNicholas Piggin 17312a04809SNicholas Piggin std r11,\area\()+EX_R11(r13) 17412a04809SNicholas Piggin std r12,\area\()+EX_R12(r13) 17512a04809SNicholas Piggin GET_SCRATCH0(r10) 17612a04809SNicholas Piggin std r10,\area\()+EX_R13(r13) 17712a04809SNicholas Piggin.endm 17812a04809SNicholas Piggin 17912a04809SNicholas Piggin.macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri 18012a04809SNicholas Piggin ld r10,PACAKMSR(r13) /* get MSR value for kernel */ 18112a04809SNicholas Piggin .if ! \set_ri 18212a04809SNicholas Piggin xori r10,r10,MSR_RI /* Clear MSR_RI */ 18312a04809SNicholas Piggin .endif 18412a04809SNicholas Piggin .if \hsrr 18512a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 18612a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 18712a04809SNicholas Piggin mtspr SPRN_HSRR1,r10 18812a04809SNicholas Piggin .else 18963d60d0cSNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 19012a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and SRR1 */ 19112a04809SNicholas Piggin mtspr SPRN_SRR1,r10 19263d60d0cSNicholas Piggin .endif 19363d60d0cSNicholas Piggin LOAD_HANDLER(r10, \label\()) 19463d60d0cSNicholas Piggin .if \hsrr 19563d60d0cSNicholas Piggin mtspr SPRN_HSRR0,r10 19663d60d0cSNicholas Piggin HRFI_TO_KERNEL 19763d60d0cSNicholas Piggin .else 19863d60d0cSNicholas Piggin mtspr SPRN_SRR0,r10 19912a04809SNicholas Piggin RFI_TO_KERNEL 20012a04809SNicholas Piggin .endif 20112a04809SNicholas Piggin b . /* prevent speculative execution */ 20212a04809SNicholas Piggin.endm 20312a04809SNicholas Piggin 20412a04809SNicholas Piggin.macro EXCEPTION_PROLOG_2_VIRT label, hsrr 20512a04809SNicholas Piggin#ifdef CONFIG_RELOCATABLE 20612a04809SNicholas Piggin .if \hsrr 20712a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 20812a04809SNicholas Piggin .else 20912a04809SNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 21012a04809SNicholas Piggin .endif 21112a04809SNicholas Piggin LOAD_HANDLER(r12, \label\()) 21212a04809SNicholas Piggin mtctr r12 21312a04809SNicholas Piggin .if \hsrr 21412a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 21512a04809SNicholas Piggin .else 21612a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and HSRR1 */ 21712a04809SNicholas Piggin .endif 21812a04809SNicholas Piggin li r10,MSR_RI 21912a04809SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 22012a04809SNicholas Piggin bctr 22112a04809SNicholas Piggin#else 22212a04809SNicholas Piggin .if \hsrr 22312a04809SNicholas Piggin mfspr r11,SPRN_HSRR0 /* save HSRR0 */ 22412a04809SNicholas Piggin mfspr r12,SPRN_HSRR1 /* and HSRR1 */ 22512a04809SNicholas Piggin .else 22612a04809SNicholas Piggin mfspr r11,SPRN_SRR0 /* save SRR0 */ 22712a04809SNicholas Piggin mfspr r12,SPRN_SRR1 /* and SRR1 */ 22812a04809SNicholas Piggin .endif 22912a04809SNicholas Piggin li r10,MSR_RI 23012a04809SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 23112a04809SNicholas Piggin b \label 23212a04809SNicholas Piggin#endif 23312a04809SNicholas Piggin.endm 23412a04809SNicholas Piggin 23512a04809SNicholas Piggin/* 23612a04809SNicholas Piggin * Branch to label using its 0xC000 address. This results in instruction 23712a04809SNicholas Piggin * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned 23812a04809SNicholas Piggin * on using mtmsr rather than rfid. 23912a04809SNicholas Piggin * 24012a04809SNicholas Piggin * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than 24112a04809SNicholas Piggin * load KBASE for a slight optimisation. 24212a04809SNicholas Piggin */ 24312a04809SNicholas Piggin#define BRANCH_TO_C000(reg, label) \ 24412a04809SNicholas Piggin __LOAD_HANDLER(reg, label); \ 24512a04809SNicholas Piggin mtctr reg; \ 24612a04809SNicholas Piggin bctr 24712a04809SNicholas Piggin 24812a04809SNicholas Piggin#ifdef CONFIG_RELOCATABLE 24912a04809SNicholas Piggin#define BRANCH_LINK_TO_FAR(label) \ 25012a04809SNicholas Piggin __LOAD_FAR_HANDLER(r12, label); \ 25112a04809SNicholas Piggin mtctr r12; \ 25212a04809SNicholas Piggin bctrl 25312a04809SNicholas Piggin 25412a04809SNicholas Piggin#else 25512a04809SNicholas Piggin#define BRANCH_LINK_TO_FAR(label) \ 25612a04809SNicholas Piggin bl label 25712a04809SNicholas Piggin#endif 25812a04809SNicholas Piggin 25912a04809SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 26012a04809SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 26112a04809SNicholas Piggin/* 26212a04809SNicholas Piggin * If hv is possible, interrupts come into to the hv version 26312a04809SNicholas Piggin * of the kvmppc_interrupt code, which then jumps to the PR handler, 26412a04809SNicholas Piggin * kvmppc_interrupt_pr, if the guest is a PR guest. 26512a04809SNicholas Piggin */ 26612a04809SNicholas Piggin#define kvmppc_interrupt kvmppc_interrupt_hv 26712a04809SNicholas Piggin#else 26812a04809SNicholas Piggin#define kvmppc_interrupt kvmppc_interrupt_pr 26912a04809SNicholas Piggin#endif 27012a04809SNicholas Piggin 27112a04809SNicholas Piggin.macro KVMTEST hsrr, n 27212a04809SNicholas Piggin lbz r10,HSTATE_IN_GUEST(r13) 27312a04809SNicholas Piggin cmpwi r10,0 27412a04809SNicholas Piggin .if \hsrr 27512a04809SNicholas Piggin bne do_kvm_H\n 27612a04809SNicholas Piggin .else 27712a04809SNicholas Piggin bne do_kvm_\n 27812a04809SNicholas Piggin .endif 27912a04809SNicholas Piggin.endm 28012a04809SNicholas Piggin 28112a04809SNicholas Piggin.macro KVM_HANDLER area, hsrr, n, skip 28212a04809SNicholas Piggin .if \skip 28312a04809SNicholas Piggin cmpwi r10,KVM_GUEST_MODE_SKIP 28412a04809SNicholas Piggin beq 89f 28512a04809SNicholas Piggin .else 28612a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(947) 28712a04809SNicholas Piggin ld r10,\area+EX_CFAR(r13) 28812a04809SNicholas Piggin std r10,HSTATE_CFAR(r13) 28912a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947) 29012a04809SNicholas Piggin .endif 29112a04809SNicholas Piggin 29212a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(948) 29312a04809SNicholas Piggin ld r10,\area+EX_PPR(r13) 29412a04809SNicholas Piggin std r10,HSTATE_PPR(r13) 29512a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948) 29612a04809SNicholas Piggin ld r10,\area+EX_R10(r13) 29712a04809SNicholas Piggin std r12,HSTATE_SCRATCH0(r13) 29812a04809SNicholas Piggin sldi r12,r9,32 29912a04809SNicholas Piggin /* HSRR variants have the 0x2 bit added to their trap number */ 30012a04809SNicholas Piggin .if \hsrr 30112a04809SNicholas Piggin ori r12,r12,(\n + 0x2) 30212a04809SNicholas Piggin .else 30312a04809SNicholas Piggin ori r12,r12,(\n) 30412a04809SNicholas Piggin .endif 30564e41351SNicholas Piggin 30664e41351SNicholas Piggin#ifdef CONFIG_RELOCATABLE 30764e41351SNicholas Piggin /* 30864e41351SNicholas Piggin * KVM requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives 30964e41351SNicholas Piggin * outside the head section. CONFIG_RELOCATABLE KVM expects CTR 31064e41351SNicholas Piggin * to be saved in HSTATE_SCRATCH1. 31164e41351SNicholas Piggin */ 31264e41351SNicholas Piggin mfctr r9 31364e41351SNicholas Piggin std r9,HSTATE_SCRATCH1(r13) 31464e41351SNicholas Piggin __LOAD_FAR_HANDLER(r9, kvmppc_interrupt) 31564e41351SNicholas Piggin mtctr r9 31664e41351SNicholas Piggin ld r9,\area+EX_R9(r13) 31764e41351SNicholas Piggin bctr 31864e41351SNicholas Piggin#else 31964e41351SNicholas Piggin ld r9,\area+EX_R9(r13) 32064e41351SNicholas Piggin b kvmppc_interrupt 32164e41351SNicholas Piggin#endif 32264e41351SNicholas Piggin 32312a04809SNicholas Piggin 32412a04809SNicholas Piggin .if \skip 32512a04809SNicholas Piggin89: mtocrf 0x80,r9 32612a04809SNicholas Piggin ld r9,\area+EX_R9(r13) 32712a04809SNicholas Piggin ld r10,\area+EX_R10(r13) 32812a04809SNicholas Piggin .if \hsrr 32912a04809SNicholas Piggin b kvmppc_skip_Hinterrupt 33012a04809SNicholas Piggin .else 33112a04809SNicholas Piggin b kvmppc_skip_interrupt 33212a04809SNicholas Piggin .endif 33312a04809SNicholas Piggin .endif 33412a04809SNicholas Piggin.endm 33512a04809SNicholas Piggin 33612a04809SNicholas Piggin#else 33712a04809SNicholas Piggin.macro KVMTEST hsrr, n 33812a04809SNicholas Piggin.endm 33912a04809SNicholas Piggin.macro KVM_HANDLER area, hsrr, n, skip 34012a04809SNicholas Piggin.endm 34112a04809SNicholas Piggin#endif 34212a04809SNicholas Piggin 34312a04809SNicholas Piggin#define EXCEPTION_PROLOG_COMMON_1() \ 34412a04809SNicholas Piggin std r9,_CCR(r1); /* save CR in stackframe */ \ 34512a04809SNicholas Piggin std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 34612a04809SNicholas Piggin std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 34712a04809SNicholas Piggin std r10,0(r1); /* make stack chain pointer */ \ 34812a04809SNicholas Piggin std r0,GPR0(r1); /* save r0 in stackframe */ \ 34912a04809SNicholas Piggin std r10,GPR1(r1); /* save r1 in stackframe */ \ 35012a04809SNicholas Piggin 35112a04809SNicholas Piggin/* Save original regs values from save area to stack frame. */ 35212a04809SNicholas Piggin#define EXCEPTION_PROLOG_COMMON_2(area) \ 35312a04809SNicholas Piggin ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 35412a04809SNicholas Piggin ld r10,area+EX_R10(r13); \ 35512a04809SNicholas Piggin std r9,GPR9(r1); \ 35612a04809SNicholas Piggin std r10,GPR10(r1); \ 35712a04809SNicholas Piggin ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 35812a04809SNicholas Piggin ld r10,area+EX_R12(r13); \ 35912a04809SNicholas Piggin ld r11,area+EX_R13(r13); \ 36012a04809SNicholas Piggin std r9,GPR11(r1); \ 36112a04809SNicholas Piggin std r10,GPR12(r1); \ 36212a04809SNicholas Piggin std r11,GPR13(r1); \ 36312a04809SNicholas PigginBEGIN_FTR_SECTION_NESTED(66); \ 36412a04809SNicholas Piggin ld r10,area+EX_CFAR(r13); \ 36512a04809SNicholas Piggin std r10,ORIG_GPR3(r1); \ 36612a04809SNicholas PigginEND_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 36712a04809SNicholas Piggin GET_CTR(r10, area); \ 36812a04809SNicholas Piggin std r10,_CTR(r1); 36912a04809SNicholas Piggin 370d064151fSNicholas Piggin#define EXCEPTION_PROLOG_COMMON_3(trap) \ 37112a04809SNicholas Piggin std r2,GPR2(r1); /* save r2 in stackframe */ \ 37212a04809SNicholas Piggin SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 37312a04809SNicholas Piggin SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 37412a04809SNicholas Piggin mflr r9; /* Get LR, later save to stack */ \ 37512a04809SNicholas Piggin ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 37612a04809SNicholas Piggin std r9,_LINK(r1); \ 37712a04809SNicholas Piggin lbz r10,PACAIRQSOFTMASK(r13); \ 37812a04809SNicholas Piggin mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 37912a04809SNicholas Piggin std r10,SOFTE(r1); \ 38012a04809SNicholas Piggin std r11,_XER(r1); \ 381d064151fSNicholas Piggin li r9,(trap)+1; \ 38212a04809SNicholas Piggin std r9,_TRAP(r1); /* set trap number */ \ 38312a04809SNicholas Piggin li r10,0; \ 38412a04809SNicholas Piggin ld r11,exception_marker@toc(r2); \ 38512a04809SNicholas Piggin std r10,RESULT(r1); /* clear regs->result */ \ 38612a04809SNicholas Piggin std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 38712a04809SNicholas Piggin 388d064151fSNicholas Piggin/* 389d064151fSNicholas Piggin * On entry r13 points to the paca, r9-r13 are saved in the paca, 390d064151fSNicholas Piggin * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 391d064151fSNicholas Piggin * SRR1, and relocation is on. 392d064151fSNicholas Piggin */ 393d064151fSNicholas Piggin#define EXCEPTION_COMMON(area, trap) \ 394d064151fSNicholas Piggin andi. r10,r12,MSR_PR; /* See if coming from user */ \ 395d064151fSNicholas Piggin mr r10,r1; /* Save r1 */ \ 396d064151fSNicholas Piggin subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 397d064151fSNicholas Piggin beq- 1f; \ 398d064151fSNicholas Piggin ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 399d064151fSNicholas Piggin1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 400d064151fSNicholas Piggin blt+ cr1,3f; /* abort if it is */ \ 401d064151fSNicholas Piggin li r1,(trap); /* will be reloaded later */ \ 402d064151fSNicholas Piggin sth r1,PACA_TRAP_SAVE(r13); \ 403d064151fSNicholas Piggin std r3,area+EX_R3(r13); \ 404d064151fSNicholas Piggin addi r3,r13,area; /* r3 -> where regs are saved*/ \ 405d064151fSNicholas Piggin RESTORE_CTR(r1, area); \ 406d064151fSNicholas Piggin b bad_stack; \ 407d064151fSNicholas Piggin3: EXCEPTION_PROLOG_COMMON_1(); \ 408d064151fSNicholas Piggin kuap_save_amr_and_lock r9, r10, cr1, cr0; \ 409d064151fSNicholas Piggin beq 4f; /* if from kernel mode */ \ 410d064151fSNicholas Piggin ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 411d064151fSNicholas Piggin SAVE_PPR(area, r9); \ 412d064151fSNicholas Piggin4: EXCEPTION_PROLOG_COMMON_2(area); \ 413d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(trap); \ 414d064151fSNicholas Piggin ACCOUNT_STOLEN_TIME 415d064151fSNicholas Piggin 416d064151fSNicholas Piggin 417d064151fSNicholas Piggin/* 418d064151fSNicholas Piggin * Exception where stack is already set in r1, r1 is saved in r10. 419d064151fSNicholas Piggin * PPR save and CPU accounting is not done (for some reason). 420d064151fSNicholas Piggin */ 421d064151fSNicholas Piggin#define EXCEPTION_COMMON_STACK(area, trap) \ 422d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_1(); \ 423d064151fSNicholas Piggin kuap_save_amr_and_lock r9, r10, cr1; \ 424d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_2(area); \ 425d064151fSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(trap) 426d064151fSNicholas Piggin 427*391e941bSNicholas Piggin/* 428*391e941bSNicholas Piggin * Restore all registers including H/SRR0/1 saved in a stack frame of a 429*391e941bSNicholas Piggin * standard exception. 430*391e941bSNicholas Piggin */ 431*391e941bSNicholas Piggin.macro EXCEPTION_RESTORE_REGS hsrr 432*391e941bSNicholas Piggin /* Move original SRR0 and SRR1 into the respective regs */ 433*391e941bSNicholas Piggin ld r9,_MSR(r1) 434*391e941bSNicholas Piggin .if \hsrr 435*391e941bSNicholas Piggin mtspr SPRN_HSRR1,r9 436*391e941bSNicholas Piggin .else 437*391e941bSNicholas Piggin mtspr SPRN_SRR1,r9 438*391e941bSNicholas Piggin .endif 439*391e941bSNicholas Piggin ld r9,_NIP(r1) 440*391e941bSNicholas Piggin .if \hsrr 441*391e941bSNicholas Piggin mtspr SPRN_HSRR0,r9 442*391e941bSNicholas Piggin .else 443*391e941bSNicholas Piggin mtspr SPRN_SRR0,r9 444*391e941bSNicholas Piggin .endif 445*391e941bSNicholas Piggin ld r9,_CTR(r1) 446*391e941bSNicholas Piggin mtctr r9 447*391e941bSNicholas Piggin ld r9,_XER(r1) 448*391e941bSNicholas Piggin mtxer r9 449*391e941bSNicholas Piggin ld r9,_LINK(r1) 450*391e941bSNicholas Piggin mtlr r9 451*391e941bSNicholas Piggin ld r9,_CCR(r1) 452*391e941bSNicholas Piggin mtcr r9 453*391e941bSNicholas Piggin REST_8GPRS(2, r1) 454*391e941bSNicholas Piggin REST_4GPRS(10, r1) 455*391e941bSNicholas Piggin REST_GPR(0, r1) 456*391e941bSNicholas Piggin /* restore original r1. */ 457*391e941bSNicholas Piggin ld r1,GPR1(r1) 458*391e941bSNicholas Piggin.endm 459d064151fSNicholas Piggin 46012a04809SNicholas Piggin#define RUNLATCH_ON \ 46112a04809SNicholas PigginBEGIN_FTR_SECTION \ 46212a04809SNicholas Piggin ld r3, PACA_THREAD_INFO(r13); \ 46312a04809SNicholas Piggin ld r4,TI_LOCAL_FLAGS(r3); \ 46412a04809SNicholas Piggin andi. r0,r4,_TLF_RUNLATCH; \ 46512a04809SNicholas Piggin beql ppc64_runlatch_on_trampoline; \ 46612a04809SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_CTRL) 46712a04809SNicholas Piggin 46812a04809SNicholas Piggin/* 46912a04809SNicholas Piggin * When the idle code in power4_idle puts the CPU into NAP mode, 47012a04809SNicholas Piggin * it has to do so in a loop, and relies on the external interrupt 47112a04809SNicholas Piggin * and decrementer interrupt entry code to get it out of the loop. 47212a04809SNicholas Piggin * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 47312a04809SNicholas Piggin * to signal that it is in the loop and needs help to get out. 47412a04809SNicholas Piggin */ 47512a04809SNicholas Piggin#ifdef CONFIG_PPC_970_NAP 47612a04809SNicholas Piggin#define FINISH_NAP \ 47712a04809SNicholas PigginBEGIN_FTR_SECTION \ 47812a04809SNicholas Piggin ld r11, PACA_THREAD_INFO(r13); \ 47912a04809SNicholas Piggin ld r9,TI_LOCAL_FLAGS(r11); \ 48012a04809SNicholas Piggin andi. r10,r9,_TLF_NAPPING; \ 48112a04809SNicholas Piggin bnel power4_fixup_nap; \ 48212a04809SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 48312a04809SNicholas Piggin#else 48412a04809SNicholas Piggin#define FINISH_NAP 48512a04809SNicholas Piggin#endif 48612a04809SNicholas Piggin 487a0502434SNicholas Piggin/* 488a0502434SNicholas Piggin * Following are the BOOK3S exception handler helper macros. 489a0502434SNicholas Piggin * Handlers come in a number of types, and each type has a number of varieties. 490a0502434SNicholas Piggin * 491a0502434SNicholas Piggin * EXC_REAL_* - real, unrelocated exception vectors 492a0502434SNicholas Piggin * EXC_VIRT_* - virt (AIL), unrelocated exception vectors 493a0502434SNicholas Piggin * TRAMP_REAL_* - real, unrelocated helpers (virt can call these) 494a0502434SNicholas Piggin * TRAMP_VIRT_* - virt, unreloc helpers (in practice, real can use) 495a0502434SNicholas Piggin * TRAMP_KVM - KVM handlers that get put into real, unrelocated 496a0502434SNicholas Piggin * EXC_COMMON - virt, relocated common handlers 497a0502434SNicholas Piggin * 498a0502434SNicholas Piggin * The EXC handlers are given a name, and branch to name_common, or the 499a0502434SNicholas Piggin * appropriate KVM or masking function. Vector handler verieties are as 500a0502434SNicholas Piggin * follows: 501a0502434SNicholas Piggin * 502a0502434SNicholas Piggin * EXC_{REAL|VIRT}_BEGIN/END - used to open-code the exception 503a0502434SNicholas Piggin * 504a0502434SNicholas Piggin * EXC_{REAL|VIRT} - standard exception 505a0502434SNicholas Piggin * 506a0502434SNicholas Piggin * EXC_{REAL|VIRT}_suffix 507a0502434SNicholas Piggin * where _suffix is: 508a0502434SNicholas Piggin * - _MASKABLE - maskable exception 509a0502434SNicholas Piggin * - _OOL - out of line with trampoline to common handler 510a0502434SNicholas Piggin * - _HV - HV exception 511a0502434SNicholas Piggin * 512a0502434SNicholas Piggin * There can be combinations, e.g., EXC_VIRT_OOL_MASKABLE_HV 513a0502434SNicholas Piggin * 514a0502434SNicholas Piggin * The one unusual case is __EXC_REAL_OOL_HV_DIRECT, which is 515a0502434SNicholas Piggin * an OOL vector that branches to a specified handler rather than the usual 516a0502434SNicholas Piggin * trampoline that goes to common. It, and other underscore macros, should 517a0502434SNicholas Piggin * be used with care. 518a0502434SNicholas Piggin * 519a0502434SNicholas Piggin * KVM handlers come in the following verieties: 520a0502434SNicholas Piggin * TRAMP_KVM 521a0502434SNicholas Piggin * TRAMP_KVM_SKIP 522a0502434SNicholas Piggin * TRAMP_KVM_HV 523a0502434SNicholas Piggin * TRAMP_KVM_HV_SKIP 524a0502434SNicholas Piggin * 525a0502434SNicholas Piggin * COMMON handlers come in the following verieties: 526a0502434SNicholas Piggin * EXC_COMMON_BEGIN/END - used to open-code the handler 527a0502434SNicholas Piggin * EXC_COMMON 528a0502434SNicholas Piggin * EXC_COMMON_ASYNC 529a0502434SNicholas Piggin * 530a0502434SNicholas Piggin * TRAMP_REAL and TRAMP_VIRT can be used with BEGIN/END. KVM 531a0502434SNicholas Piggin * and OOL handlers are implemented as types of TRAMP and TRAMP_VIRT handlers. 532a0502434SNicholas Piggin */ 533a0502434SNicholas Piggin 534a0502434SNicholas Piggin#define __EXC_REAL(name, start, size, area) \ 535a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 536a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 537a0502434SNicholas Piggin EXCEPTION_PROLOG_0 area ; \ 538a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0 ; \ 539a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ 540a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 541a0502434SNicholas Piggin 542a0502434SNicholas Piggin#define EXC_REAL(name, start, size) \ 543a0502434SNicholas Piggin __EXC_REAL(name, start, size, PACA_EXGEN) 544a0502434SNicholas Piggin 545a0502434SNicholas Piggin#define __EXC_VIRT(name, start, size, realvec, area) \ 546a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 547a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 548a0502434SNicholas Piggin EXCEPTION_PROLOG_0 area ; \ 549a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0; \ 550a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ 551a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 552a0502434SNicholas Piggin 553a0502434SNicholas Piggin#define EXC_VIRT(name, start, size, realvec) \ 554a0502434SNicholas Piggin __EXC_VIRT(name, start, size, realvec, PACA_EXGEN) 555a0502434SNicholas Piggin 556a0502434SNicholas Piggin#define EXC_REAL_MASKABLE(name, start, size, bitmask) \ 557a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 558a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 559a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 560a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, bitmask ; \ 561a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \ 562a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 563a0502434SNicholas Piggin 564a0502434SNicholas Piggin#define EXC_VIRT_MASKABLE(name, start, size, realvec, bitmask) \ 565a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 566a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 567a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 568a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \ 569a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \ 570a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 571a0502434SNicholas Piggin 572a0502434SNicholas Piggin#define EXC_REAL_HV(name, start, size) \ 573a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 574a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 575a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN; \ 576a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0 ; \ 577a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \ 578a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 579a0502434SNicholas Piggin 580a0502434SNicholas Piggin#define EXC_VIRT_HV(name, start, size, realvec) \ 581a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 582a0502434SNicholas Piggin SET_SCRATCH0(r13); /* save r13 */ \ 583a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN; \ 584a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \ 585a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \ 586a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 587a0502434SNicholas Piggin 588a0502434SNicholas Piggin#define __EXC_REAL_OOL(name, start, size) \ 589a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 590a0502434SNicholas Piggin SET_SCRATCH0(r13); \ 591a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 592a0502434SNicholas Piggin b tramp_real_##name ; \ 593a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 594a0502434SNicholas Piggin 595a0502434SNicholas Piggin#define __TRAMP_REAL_OOL(name, vec) \ 596a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 597a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ; \ 598a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 599a0502434SNicholas Piggin 600a0502434SNicholas Piggin#define EXC_REAL_OOL(name, start, size) \ 601a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size); \ 602a0502434SNicholas Piggin __TRAMP_REAL_OOL(name, start) 603a0502434SNicholas Piggin 604a0502434SNicholas Piggin#define __EXC_REAL_OOL_MASKABLE(name, start, size) \ 605a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 606a0502434SNicholas Piggin 607a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_MASKABLE(name, vec, bitmask) \ 608a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 609a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \ 610a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 611a0502434SNicholas Piggin 612a0502434SNicholas Piggin#define EXC_REAL_OOL_MASKABLE(name, start, size, bitmask) \ 613a0502434SNicholas Piggin __EXC_REAL_OOL_MASKABLE(name, start, size); \ 614a0502434SNicholas Piggin __TRAMP_REAL_OOL_MASKABLE(name, start, bitmask) 615a0502434SNicholas Piggin 616a0502434SNicholas Piggin#define __EXC_REAL_OOL_HV_DIRECT(name, start, size, handler) \ 617a0502434SNicholas Piggin EXC_REAL_BEGIN(name, start, size); \ 618a0502434SNicholas Piggin SET_SCRATCH0(r13); \ 619a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 620a0502434SNicholas Piggin b handler; \ 621a0502434SNicholas Piggin EXC_REAL_END(name, start, size) 622a0502434SNicholas Piggin 623a0502434SNicholas Piggin#define __EXC_REAL_OOL_HV(name, start, size) \ 624a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 625a0502434SNicholas Piggin 626a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_HV(name, vec) \ 627a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 628a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \ 629a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 630a0502434SNicholas Piggin 631a0502434SNicholas Piggin#define EXC_REAL_OOL_HV(name, start, size) \ 632a0502434SNicholas Piggin __EXC_REAL_OOL_HV(name, start, size); \ 633a0502434SNicholas Piggin __TRAMP_REAL_OOL_HV(name, start) 634a0502434SNicholas Piggin 635a0502434SNicholas Piggin#define __EXC_REAL_OOL_MASKABLE_HV(name, start, size) \ 636a0502434SNicholas Piggin __EXC_REAL_OOL(name, start, size) 637a0502434SNicholas Piggin 638a0502434SNicholas Piggin#define __TRAMP_REAL_OOL_MASKABLE_HV(name, vec, bitmask) \ 639a0502434SNicholas Piggin TRAMP_REAL_BEGIN(tramp_real_##name); \ 640a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \ 641a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 642a0502434SNicholas Piggin 643a0502434SNicholas Piggin#define EXC_REAL_OOL_MASKABLE_HV(name, start, size, bitmask) \ 644a0502434SNicholas Piggin __EXC_REAL_OOL_MASKABLE_HV(name, start, size); \ 645a0502434SNicholas Piggin __TRAMP_REAL_OOL_MASKABLE_HV(name, start, bitmask) 646a0502434SNicholas Piggin 647a0502434SNicholas Piggin#define __EXC_VIRT_OOL(name, start, size) \ 648a0502434SNicholas Piggin EXC_VIRT_BEGIN(name, start, size); \ 649a0502434SNicholas Piggin SET_SCRATCH0(r13); \ 650a0502434SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN ; \ 651a0502434SNicholas Piggin b tramp_virt_##name; \ 652a0502434SNicholas Piggin EXC_VIRT_END(name, start, size) 653a0502434SNicholas Piggin 654a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL(name, realvec) \ 655a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 656a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ; \ 657a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD 658a0502434SNicholas Piggin 659a0502434SNicholas Piggin#define EXC_VIRT_OOL(name, start, size, realvec) \ 660a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size); \ 661a0502434SNicholas Piggin __TRAMP_VIRT_OOL(name, realvec) 662a0502434SNicholas Piggin 663a0502434SNicholas Piggin#define __EXC_VIRT_OOL_MASKABLE(name, start, size) \ 664a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 665a0502434SNicholas Piggin 666a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) \ 667a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 668a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \ 669a0502434SNicholas Piggin EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 670a0502434SNicholas Piggin 671a0502434SNicholas Piggin#define EXC_VIRT_OOL_MASKABLE(name, start, size, realvec, bitmask) \ 672a0502434SNicholas Piggin __EXC_VIRT_OOL_MASKABLE(name, start, size); \ 673a0502434SNicholas Piggin __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) 674a0502434SNicholas Piggin 675a0502434SNicholas Piggin#define __EXC_VIRT_OOL_HV(name, start, size) \ 676a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 677a0502434SNicholas Piggin 678a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_HV(name, realvec) \ 679a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 680a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \ 681a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV 682a0502434SNicholas Piggin 683a0502434SNicholas Piggin#define EXC_VIRT_OOL_HV(name, start, size, realvec) \ 684a0502434SNicholas Piggin __EXC_VIRT_OOL_HV(name, start, size); \ 685a0502434SNicholas Piggin __TRAMP_VIRT_OOL_HV(name, realvec) 686a0502434SNicholas Piggin 687a0502434SNicholas Piggin#define __EXC_VIRT_OOL_MASKABLE_HV(name, start, size) \ 688a0502434SNicholas Piggin __EXC_VIRT_OOL(name, start, size) 689a0502434SNicholas Piggin 690a0502434SNicholas Piggin#define __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) \ 691a0502434SNicholas Piggin TRAMP_VIRT_BEGIN(tramp_virt_##name); \ 692a0502434SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, bitmask ; \ 693a0502434SNicholas Piggin EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV 694a0502434SNicholas Piggin 695a0502434SNicholas Piggin#define EXC_VIRT_OOL_MASKABLE_HV(name, start, size, realvec, bitmask) \ 696a0502434SNicholas Piggin __EXC_VIRT_OOL_MASKABLE_HV(name, start, size); \ 697a0502434SNicholas Piggin __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) 698a0502434SNicholas Piggin 699a0502434SNicholas Piggin#define TRAMP_KVM(area, n) \ 700a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_##n); \ 701a0502434SNicholas Piggin KVM_HANDLER area, EXC_STD, n, 0 702a0502434SNicholas Piggin 703a0502434SNicholas Piggin#define TRAMP_KVM_SKIP(area, n) \ 704a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_##n); \ 705a0502434SNicholas Piggin KVM_HANDLER area, EXC_STD, n, 1 706a0502434SNicholas Piggin 707a0502434SNicholas Piggin#define TRAMP_KVM_HV(area, n) \ 708a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_H##n); \ 709a0502434SNicholas Piggin KVM_HANDLER area, EXC_HV, n, 0 710a0502434SNicholas Piggin 711a0502434SNicholas Piggin#define TRAMP_KVM_HV_SKIP(area, n) \ 712a0502434SNicholas Piggin TRAMP_KVM_BEGIN(do_kvm_H##n); \ 713a0502434SNicholas Piggin KVM_HANDLER area, EXC_HV, n, 1 714a0502434SNicholas Piggin 715a0502434SNicholas Piggin#define EXC_COMMON(name, realvec, hdlr) \ 716a0502434SNicholas Piggin EXC_COMMON_BEGIN(name); \ 717a0502434SNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, realvec); \ 718a0502434SNicholas Piggin bl save_nvgprs; \ 719a0502434SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11); \ 720a0502434SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD; \ 721a0502434SNicholas Piggin bl hdlr; \ 722a0502434SNicholas Piggin b ret_from_except 723a0502434SNicholas Piggin 724a0502434SNicholas Piggin/* 725a0502434SNicholas Piggin * Like EXC_COMMON, but for exceptions that can occur in the idle task and 726a0502434SNicholas Piggin * therefore need the special idle handling (finish nap and runlatch) 727a0502434SNicholas Piggin */ 728a0502434SNicholas Piggin#define EXC_COMMON_ASYNC(name, realvec, hdlr) \ 729a0502434SNicholas Piggin EXC_COMMON_BEGIN(name); \ 730a0502434SNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, realvec); \ 731a0502434SNicholas Piggin FINISH_NAP; \ 732a0502434SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11); \ 733a0502434SNicholas Piggin RUNLATCH_ON; \ 734a0502434SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD; \ 735a0502434SNicholas Piggin bl hdlr; \ 736a0502434SNicholas Piggin b ret_from_except_lite 737a0502434SNicholas Piggin 73812a04809SNicholas Piggin 73912a04809SNicholas Piggin/* 74057f26649SNicholas Piggin * There are a few constraints to be concerned with. 74157f26649SNicholas Piggin * - Real mode exceptions code/data must be located at their physical location. 74257f26649SNicholas Piggin * - Virtual mode exceptions must be mapped at their 0xc000... location. 74357f26649SNicholas Piggin * - Fixed location code must not call directly beyond the __end_interrupts 74457f26649SNicholas Piggin * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence 74557f26649SNicholas Piggin * must be used. 74657f26649SNicholas Piggin * - LOAD_HANDLER targets must be within first 64K of physical 0 / 74757f26649SNicholas Piggin * virtual 0xc00... 74857f26649SNicholas Piggin * - Conditional branch targets must be within +/-32K of caller. 74957f26649SNicholas Piggin * 75057f26649SNicholas Piggin * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and 75157f26649SNicholas Piggin * therefore don't have to run in physically located code or rfid to 75257f26649SNicholas Piggin * virtual mode kernel code. However on relocatable kernels they do have 75357f26649SNicholas Piggin * to branch to KERNELBASE offset because the rest of the kernel (outside 75457f26649SNicholas Piggin * the exception vectors) may be located elsewhere. 75557f26649SNicholas Piggin * 75657f26649SNicholas Piggin * Virtual exceptions correspond with physical, except their entry points 75757f26649SNicholas Piggin * are offset by 0xc000000000000000 and also tend to get an added 0x4000 75857f26649SNicholas Piggin * offset applied. Virtual exceptions are enabled with the Alternate 75957f26649SNicholas Piggin * Interrupt Location (AIL) bit set in the LPCR. However this does not 76057f26649SNicholas Piggin * guarantee they will be delivered virtually. Some conditions (see the ISA) 76157f26649SNicholas Piggin * cause exceptions to be delivered in real mode. 76257f26649SNicholas Piggin * 76357f26649SNicholas Piggin * It's impossible to receive interrupts below 0x300 via AIL. 76457f26649SNicholas Piggin * 76557f26649SNicholas Piggin * KVM: None of the virtual exceptions are from the guest. Anything that 76657f26649SNicholas Piggin * escalated to HV=1 from HV=0 is delivered via real mode handlers. 76757f26649SNicholas Piggin * 76857f26649SNicholas Piggin * 7690ebc4cdaSBenjamin Herrenschmidt * We layout physical memory as follows: 7700ebc4cdaSBenjamin Herrenschmidt * 0x0000 - 0x00ff : Secondary processor spin code 77157f26649SNicholas Piggin * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors 77257f26649SNicholas Piggin * 0x1900 - 0x3fff : Real mode trampolines 77357f26649SNicholas Piggin * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors 77457f26649SNicholas Piggin * 0x5900 - 0x6fff : Relon mode trampolines 7750ebc4cdaSBenjamin Herrenschmidt * 0x7000 - 0x7fff : FWNMI data area 77657f26649SNicholas Piggin * 0x8000 - .... : Common interrupt handlers, remaining early 77757f26649SNicholas Piggin * setup code, rest of kernel. 778e0319829SNicholas Piggin * 779e0319829SNicholas Piggin * We could reclaim 0x4000-0x42ff for real mode trampolines if the space 780e0319829SNicholas Piggin * is necessary. Until then it's more consistent to explicitly put VIRT_NONE 781e0319829SNicholas Piggin * vectors there. 7820ebc4cdaSBenjamin Herrenschmidt */ 78357f26649SNicholas PigginOPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) 78457f26649SNicholas PigginOPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) 78557f26649SNicholas PigginOPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) 78657f26649SNicholas PigginOPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) 787ccd47702SNicholas Piggin 788ccd47702SNicholas Piggin#ifdef CONFIG_PPC_POWERNV 789bd3524feSNicholas Piggin .globl start_real_trampolines 790bd3524feSNicholas Piggin .globl end_real_trampolines 791bd3524feSNicholas Piggin .globl start_virt_trampolines 792bd3524feSNicholas Piggin .globl end_virt_trampolines 793ccd47702SNicholas Piggin#endif 794ccd47702SNicholas Piggin 79557f26649SNicholas Piggin#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) 79657f26649SNicholas Piggin/* 79757f26649SNicholas Piggin * Data area reserved for FWNMI option. 79857f26649SNicholas Piggin * This address (0x7000) is fixed by the RPA. 79957f26649SNicholas Piggin * pseries and powernv need to keep the whole page from 80057f26649SNicholas Piggin * 0x7000 to 0x8000 free for use by the firmware 80157f26649SNicholas Piggin */ 80257f26649SNicholas PigginZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) 80357f26649SNicholas PigginOPEN_TEXT_SECTION(0x8000) 80457f26649SNicholas Piggin#else 80557f26649SNicholas PigginOPEN_TEXT_SECTION(0x7000) 80657f26649SNicholas Piggin#endif 80757f26649SNicholas Piggin 80857f26649SNicholas PigginUSE_FIXED_SECTION(real_vectors) 80957f26649SNicholas Piggin 8100ebc4cdaSBenjamin Herrenschmidt/* 8110ebc4cdaSBenjamin Herrenschmidt * This is the start of the interrupt handlers for pSeries 8120ebc4cdaSBenjamin Herrenschmidt * This code runs with relocation off. 8130ebc4cdaSBenjamin Herrenschmidt * Code from here to __end_interrupts gets copied down to real 8140ebc4cdaSBenjamin Herrenschmidt * address 0x100 when we are running a relocatable kernel. 8150ebc4cdaSBenjamin Herrenschmidt * Therefore any relative branches in this section must only 8160ebc4cdaSBenjamin Herrenschmidt * branch to labels in this section. 8170ebc4cdaSBenjamin Herrenschmidt */ 8180ebc4cdaSBenjamin Herrenschmidt .globl __start_interrupts 8190ebc4cdaSBenjamin Herrenschmidt__start_interrupts: 8200ebc4cdaSBenjamin Herrenschmidt 821e0319829SNicholas Piggin/* No virt vectors corresponding with 0x0..0x100 */ 8221a6822d1SNicholas PigginEXC_VIRT_NONE(0x4000, 0x100) 823e0319829SNicholas Piggin 824fb479e44SNicholas Piggin 825a7c1ca19SNicholas PigginEXC_REAL_BEGIN(system_reset, 0x100, 0x100) 826a7c1ca19SNicholas Piggin SET_SCRATCH0(r13) 8275dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXNMI 828a7c1ca19SNicholas Piggin 829a7c1ca19SNicholas Piggin /* This is EXCEPTION_PROLOG_1 with the idle feature section added */ 830a7c1ca19SNicholas Piggin OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR) 831a7c1ca19SNicholas Piggin OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_CFAR, r10, CPU_FTR_CFAR) 832a7c1ca19SNicholas Piggin INTERRUPT_TO_KERNEL 833a7c1ca19SNicholas Piggin SAVE_CTR(r10, PACA_EXNMI) 834a7c1ca19SNicholas Piggin mfcr r9 835a7c1ca19SNicholas Piggin 836fb479e44SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 837fb479e44SNicholas Piggin /* 838fb479e44SNicholas Piggin * If running native on arch 2.06 or later, check if we are waking up 839ba6d334aSBenjamin Herrenschmidt * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 840ba6d334aSBenjamin Herrenschmidt * bits 46:47. A non-0 value indicates that we are coming from a power 841ba6d334aSBenjamin Herrenschmidt * saving state. The idle wakeup handler initially runs in real mode, 842ba6d334aSBenjamin Herrenschmidt * but we branch to the 0xc000... address so we can turn on relocation 843ba6d334aSBenjamin Herrenschmidt * with mtmsr. 844fb479e44SNicholas Piggin */ 845a7c1ca19SNicholas PigginBEGIN_FTR_SECTION 846a7c1ca19SNicholas Piggin mfspr r10,SPRN_SRR1 847a7c1ca19SNicholas Piggin rlwinm. r10,r10,47-31,30,31 848a7c1ca19SNicholas Piggin beq- 1f 849a7c1ca19SNicholas Piggin cmpwi cr1,r10,2 850a7c1ca19SNicholas Piggin mfspr r3,SPRN_SRR1 851a7c1ca19SNicholas Piggin bltlr cr1 /* no state loss, return to idle caller */ 852a7c1ca19SNicholas Piggin BRANCH_TO_C000(r10, system_reset_idle_common) 853a7c1ca19SNicholas Piggin1: 854a7c1ca19SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 855fb479e44SNicholas Piggin#endif 856fb479e44SNicholas Piggin 857a7c1ca19SNicholas Piggin KVMTEST EXC_STD 0x100 858a7c1ca19SNicholas Piggin std r11,PACA_EXNMI+EX_R11(r13) 859a7c1ca19SNicholas Piggin std r12,PACA_EXNMI+EX_R12(r13) 860a7c1ca19SNicholas Piggin GET_SCRATCH0(r10) 861a7c1ca19SNicholas Piggin std r10,PACA_EXNMI+EX_R13(r13) 862a7c1ca19SNicholas Piggin 863a7c1ca19SNicholas Piggin EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 864c4f3b52cSNicholas Piggin /* 865c4f3b52cSNicholas Piggin * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is 866c4f3b52cSNicholas Piggin * being used, so a nested NMI exception would corrupt it. 867c4f3b52cSNicholas Piggin */ 868371fefd6SPaul Mackerras 8691a6822d1SNicholas PigginEXC_REAL_END(system_reset, 0x100, 0x100) 8701a6822d1SNicholas PigginEXC_VIRT_NONE(0x4100, 0x100) 8716de6638bSNicholas PigginTRAMP_KVM(PACA_EXNMI, 0x100) 872fb479e44SNicholas Piggin 873fb479e44SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 874fb479e44SNicholas PigginEXC_COMMON_BEGIN(system_reset_idle_common) 87510d91611SNicholas Piggin /* 87610d91611SNicholas Piggin * This must be a direct branch (without linker branch stub) because 87710d91611SNicholas Piggin * we can not use TOC at this point as r2 may not be restored yet. 87810d91611SNicholas Piggin */ 87910d91611SNicholas Piggin b idle_return_gpr_loss 880371fefd6SPaul Mackerras#endif 881371fefd6SPaul Mackerras 882a3d96f70SNicholas PigginEXC_COMMON_BEGIN(system_reset_common) 883c4f3b52cSNicholas Piggin /* 884c4f3b52cSNicholas Piggin * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able 885c4f3b52cSNicholas Piggin * to recover, but nested NMI will notice in_nmi and not recover 886c4f3b52cSNicholas Piggin * because of the use of the NMI stack. in_nmi reentrancy is tested in 887c4f3b52cSNicholas Piggin * system_reset_exception. 888c4f3b52cSNicholas Piggin */ 889c4f3b52cSNicholas Piggin lhz r10,PACA_IN_NMI(r13) 890c4f3b52cSNicholas Piggin addi r10,r10,1 891c4f3b52cSNicholas Piggin sth r10,PACA_IN_NMI(r13) 892c4f3b52cSNicholas Piggin li r10,MSR_RI 893c4f3b52cSNicholas Piggin mtmsrd r10,1 894aca79d2bSVaidyanathan Srinivasan 895b1ee8a3dSNicholas Piggin mr r10,r1 896b1ee8a3dSNicholas Piggin ld r1,PACA_NMI_EMERG_SP(r13) 897b1ee8a3dSNicholas Piggin subi r1,r1,INT_FRAME_SIZE 89847169fbaSNicholas Piggin EXCEPTION_COMMON_STACK(PACA_EXNMI, 0x100) 89947169fbaSNicholas Piggin bl save_nvgprs 90047169fbaSNicholas Piggin /* 90147169fbaSNicholas Piggin * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does 90247169fbaSNicholas Piggin * the right thing. We do not want to reconcile because that goes 90347169fbaSNicholas Piggin * through irq tracing which we don't want in NMI. 90447169fbaSNicholas Piggin * 90547169fbaSNicholas Piggin * Save PACAIRQHAPPENED because some code will do a hard disable 90647169fbaSNicholas Piggin * (e.g., xmon). So we want to restore this back to where it was 90747169fbaSNicholas Piggin * when we return. DAR is unused in the stack, so save it there. 90847169fbaSNicholas Piggin */ 90947169fbaSNicholas Piggin li r10,IRQS_ALL_DISABLED 91047169fbaSNicholas Piggin stb r10,PACAIRQSOFTMASK(r13) 91147169fbaSNicholas Piggin lbz r10,PACAIRQHAPPENED(r13) 91247169fbaSNicholas Piggin std r10,_DAR(r1) 91347169fbaSNicholas Piggin 914c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 915c06075f3SNicholas Piggin bl system_reset_exception 91615b4dd79SNicholas Piggin 91715b4dd79SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */ 918fbc50063SNicholas Piggin li r9,0 91915b4dd79SNicholas Piggin mtmsrd r9,1 920c4f3b52cSNicholas Piggin 921c4f3b52cSNicholas Piggin /* 92215b4dd79SNicholas Piggin * MSR_RI is clear, now we can decrement paca->in_nmi. 923c4f3b52cSNicholas Piggin */ 924c4f3b52cSNicholas Piggin lhz r10,PACA_IN_NMI(r13) 925c4f3b52cSNicholas Piggin subi r10,r10,1 926c4f3b52cSNicholas Piggin sth r10,PACA_IN_NMI(r13) 927c4f3b52cSNicholas Piggin 92815b4dd79SNicholas Piggin /* 92915b4dd79SNicholas Piggin * Restore soft mask settings. 93015b4dd79SNicholas Piggin */ 93115b4dd79SNicholas Piggin ld r10,_DAR(r1) 93215b4dd79SNicholas Piggin stb r10,PACAIRQHAPPENED(r13) 93315b4dd79SNicholas Piggin ld r10,SOFTE(r1) 93415b4dd79SNicholas Piggin stb r10,PACAIRQSOFTMASK(r13) 93515b4dd79SNicholas Piggin 936*391e941bSNicholas Piggin EXCEPTION_RESTORE_REGS EXC_STD 93715b4dd79SNicholas Piggin RFI_TO_USER_OR_KERNEL 938582baf44SNicholas Piggin 939582baf44SNicholas Piggin#ifdef CONFIG_PPC_PSERIES 940582baf44SNicholas Piggin/* 941582baf44SNicholas Piggin * Vectors for the FWNMI option. Share common code. 942582baf44SNicholas Piggin */ 943582baf44SNicholas PigginTRAMP_REAL_BEGIN(system_reset_fwnmi) 944582baf44SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 945fc557537SNicholas Piggin /* See comment at system_reset exception, don't turn on RI */ 946fc557537SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXNMI 947fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0 948fc557537SNicholas Piggin EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0 949fc557537SNicholas Piggin 950582baf44SNicholas Piggin#endif /* CONFIG_PPC_PSERIES */ 951582baf44SNicholas Piggin 9520ebc4cdaSBenjamin Herrenschmidt 9531a6822d1SNicholas PigginEXC_REAL_BEGIN(machine_check, 0x200, 0x100) 954b01c8b54SPaul Mackerras /* This is moved out of line as it can be patched by FW, but 955b01c8b54SPaul Mackerras * some code path might still want to branch into the original 956b01c8b54SPaul Mackerras * vector 957b01c8b54SPaul Mackerras */ 9581707dd16SPaul Mackerras SET_SCRATCH0(r13) /* save r13 */ 9595dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 9601e9b4507SMahesh SalgaonkarBEGIN_FTR_SECTION 961db7d31acSMahesh Salgaonkar b machine_check_common_early 9621e9b4507SMahesh SalgaonkarFTR_SECTION_ELSE 9631707dd16SPaul Mackerras b machine_check_pSeries_0 9641e9b4507SMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 9651a6822d1SNicholas PigginEXC_REAL_END(machine_check, 0x200, 0x100) 9661a6822d1SNicholas PigginEXC_VIRT_NONE(0x4200, 0x100) 967db7d31acSMahesh SalgaonkarTRAMP_REAL_BEGIN(machine_check_common_early) 968fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0 969afcf0095SNicholas Piggin /* 970afcf0095SNicholas Piggin * Register contents: 971afcf0095SNicholas Piggin * R13 = PACA 972afcf0095SNicholas Piggin * R9 = CR 973afcf0095SNicholas Piggin * Original R9 to R13 is saved on PACA_EXMC 974afcf0095SNicholas Piggin * 975afcf0095SNicholas Piggin * Switch to mc_emergency stack and handle re-entrancy (we limit 976afcf0095SNicholas Piggin * the nested MCE upto level 4 to avoid stack overflow). 977afcf0095SNicholas Piggin * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 978afcf0095SNicholas Piggin * 979afcf0095SNicholas Piggin * We use paca->in_mce to check whether this is the first entry or 980afcf0095SNicholas Piggin * nested machine check. We increment paca->in_mce to track nested 981afcf0095SNicholas Piggin * machine checks. 982afcf0095SNicholas Piggin * 983afcf0095SNicholas Piggin * If this is the first entry then set stack pointer to 984afcf0095SNicholas Piggin * paca->mc_emergency_sp, otherwise r1 is already pointing to 985afcf0095SNicholas Piggin * stack frame on mc_emergency stack. 986afcf0095SNicholas Piggin * 987afcf0095SNicholas Piggin * NOTE: We are here with MSR_ME=0 (off), which means we risk a 988afcf0095SNicholas Piggin * checkstop if we get another machine check exception before we do 989afcf0095SNicholas Piggin * rfid with MSR_ME=1. 9901945bc45SNicholas Piggin * 9911945bc45SNicholas Piggin * This interrupt can wake directly from idle. If that is the case, 9921945bc45SNicholas Piggin * the machine check is handled then the idle wakeup code is called 9932bf1071aSNicholas Piggin * to restore state. 994afcf0095SNicholas Piggin */ 995afcf0095SNicholas Piggin mr r11,r1 /* Save r1 */ 996afcf0095SNicholas Piggin lhz r10,PACA_IN_MCE(r13) 997afcf0095SNicholas Piggin cmpwi r10,0 /* Are we in nested machine check */ 998afcf0095SNicholas Piggin bne 0f /* Yes, we are. */ 999afcf0095SNicholas Piggin /* First machine check entry */ 1000afcf0095SNicholas Piggin ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ 1001afcf0095SNicholas Piggin0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1002afcf0095SNicholas Piggin addi r10,r10,1 /* increment paca->in_mce */ 1003afcf0095SNicholas Piggin sth r10,PACA_IN_MCE(r13) 1004afcf0095SNicholas Piggin /* Limit nested MCE to level 4 to avoid stack overflow */ 1005ba41e1e1SBalbir Singh cmpwi r10,MAX_MCE_DEPTH 1006afcf0095SNicholas Piggin bgt 2f /* Check if we hit limit of 4 */ 1007afcf0095SNicholas Piggin std r11,GPR1(r1) /* Save r1 on the stack. */ 1008afcf0095SNicholas Piggin std r11,0(r1) /* make stack chain pointer */ 1009afcf0095SNicholas Piggin mfspr r11,SPRN_SRR0 /* Save SRR0 */ 1010afcf0095SNicholas Piggin std r11,_NIP(r1) 1011afcf0095SNicholas Piggin mfspr r11,SPRN_SRR1 /* Save SRR1 */ 1012afcf0095SNicholas Piggin std r11,_MSR(r1) 1013afcf0095SNicholas Piggin mfspr r11,SPRN_DAR /* Save DAR */ 1014afcf0095SNicholas Piggin std r11,_DAR(r1) 1015afcf0095SNicholas Piggin mfspr r11,SPRN_DSISR /* Save DSISR */ 1016afcf0095SNicholas Piggin std r11,_DSISR(r1) 1017afcf0095SNicholas Piggin std r9,_CCR(r1) /* Save CR in stackframe */ 1018e13e7cd4SNicholas Piggin /* We don't touch AMR here, we never go to virtual mode */ 1019afcf0095SNicholas Piggin /* Save r9 through r13 from EXMC save area to stack frame. */ 1020afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) 1021afcf0095SNicholas Piggin mfmsr r11 /* get MSR value */ 1022db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1023afcf0095SNicholas Piggin ori r11,r11,MSR_ME /* turn on ME bit */ 1024db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1025afcf0095SNicholas Piggin ori r11,r11,MSR_RI /* turn on RI bit */ 1026afcf0095SNicholas Piggin LOAD_HANDLER(r12, machine_check_handle_early) 1027afcf0095SNicholas Piggin1: mtspr SPRN_SRR0,r12 1028afcf0095SNicholas Piggin mtspr SPRN_SRR1,r11 1029222f20f1SNicholas Piggin RFI_TO_KERNEL 1030afcf0095SNicholas Piggin b . /* prevent speculative execution */ 1031afcf0095SNicholas Piggin2: 1032afcf0095SNicholas Piggin /* Stack overflow. Stay on emergency stack and panic. 1033afcf0095SNicholas Piggin * Keep the ME bit off while panic-ing, so that if we hit 1034afcf0095SNicholas Piggin * another machine check we checkstop. 1035afcf0095SNicholas Piggin */ 1036afcf0095SNicholas Piggin addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ 1037afcf0095SNicholas Piggin ld r11,PACAKMSR(r13) 1038afcf0095SNicholas Piggin LOAD_HANDLER(r12, unrecover_mce) 1039afcf0095SNicholas Piggin li r10,MSR_ME 1040afcf0095SNicholas Piggin andc r11,r11,r10 /* Turn off MSR_ME */ 1041afcf0095SNicholas Piggin b 1b 1042afcf0095SNicholas Piggin b . /* prevent speculative execution */ 1043afcf0095SNicholas Piggin 1044afcf0095SNicholas PigginTRAMP_REAL_BEGIN(machine_check_pSeries) 1045afcf0095SNicholas Piggin .globl machine_check_fwnmi 1046afcf0095SNicholas Pigginmachine_check_fwnmi: 1047afcf0095SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 10485dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 1049a43c1590SMahesh SalgaonkarBEGIN_FTR_SECTION 1050db7d31acSMahesh Salgaonkar b machine_check_common_early 1051a43c1590SMahesh SalgaonkarEND_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 1052afcf0095SNicholas Pigginmachine_check_pSeries_0: 1053fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0 1054afcf0095SNicholas Piggin /* 105583a980f7SNicholas Piggin * MSR_RI is not enabled, because PACA_EXMC is being used, so a 105683a980f7SNicholas Piggin * nested machine check corrupts it. machine_check_common enables 105783a980f7SNicholas Piggin * MSR_RI. 1058afcf0095SNicholas Piggin */ 10592d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0 1060afcf0095SNicholas Piggin 1061afcf0095SNicholas PigginTRAMP_KVM_SKIP(PACA_EXMC, 0x200) 1062afcf0095SNicholas Piggin 1063afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_common) 1064afcf0095SNicholas Piggin /* 1065afcf0095SNicholas Piggin * Machine check is different because we use a different 1066afcf0095SNicholas Piggin * save area: PACA_EXMC instead of PACA_EXGEN. 1067afcf0095SNicholas Piggin */ 1068afcf0095SNicholas Piggin mfspr r10,SPRN_DAR 1069afcf0095SNicholas Piggin std r10,PACA_EXMC+EX_DAR(r13) 1070afcf0095SNicholas Piggin mfspr r10,SPRN_DSISR 1071afcf0095SNicholas Piggin stw r10,PACA_EXMC+EX_DSISR(r13) 1072d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXMC, 0x200) 1073afcf0095SNicholas Piggin FINISH_NAP 1074afcf0095SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1075afcf0095SNicholas Piggin ld r3,PACA_EXMC+EX_DAR(r13) 1076afcf0095SNicholas Piggin lwz r4,PACA_EXMC+EX_DSISR(r13) 1077afcf0095SNicholas Piggin /* Enable MSR_RI when finished with PACA_EXMC */ 1078afcf0095SNicholas Piggin li r10,MSR_RI 1079afcf0095SNicholas Piggin mtmsrd r10,1 1080afcf0095SNicholas Piggin std r3,_DAR(r1) 1081afcf0095SNicholas Piggin std r4,_DSISR(r1) 1082afcf0095SNicholas Piggin bl save_nvgprs 1083afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1084afcf0095SNicholas Piggin bl machine_check_exception 1085afcf0095SNicholas Piggin b ret_from_except 1086afcf0095SNicholas Piggin 1087afcf0095SNicholas Piggin#define MACHINE_CHECK_HANDLER_WINDUP \ 1088afcf0095SNicholas Piggin /* Clear MSR_RI before setting SRR0 and SRR1. */\ 1089fbc50063SNicholas Piggin li r9,0; \ 1090afcf0095SNicholas Piggin mtmsrd r9,1; /* Clear MSR_RI */ \ 1091ad73d8d4SNicholas Piggin /* Decrement paca->in_mce now RI is clear. */ \ 1092ad73d8d4SNicholas Piggin lhz r12,PACA_IN_MCE(r13); \ 1093ad73d8d4SNicholas Piggin subi r12,r12,1; \ 1094ad73d8d4SNicholas Piggin sth r12,PACA_IN_MCE(r13); \ 1095*391e941bSNicholas Piggin EXCEPTION_RESTORE_REGS EXC_STD 1096afcf0095SNicholas Piggin 10971945bc45SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 10981945bc45SNicholas Piggin/* 10991945bc45SNicholas Piggin * This is an idle wakeup. Low level machine check has already been 11001945bc45SNicholas Piggin * done. Queue the event then call the idle code to do the wake up. 11011945bc45SNicholas Piggin */ 11021945bc45SNicholas PigginEXC_COMMON_BEGIN(machine_check_idle_common) 11031945bc45SNicholas Piggin bl machine_check_queue_event 11041945bc45SNicholas Piggin 11051945bc45SNicholas Piggin /* 11061945bc45SNicholas Piggin * We have not used any non-volatile GPRs here, and as a rule 11071945bc45SNicholas Piggin * most exception code including machine check does not. 11081945bc45SNicholas Piggin * Therefore PACA_NAPSTATELOST does not need to be set. Idle 11091945bc45SNicholas Piggin * wakeup will restore volatile registers. 11101945bc45SNicholas Piggin * 11111945bc45SNicholas Piggin * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. 11121945bc45SNicholas Piggin * 11131945bc45SNicholas Piggin * Then decrement MCE nesting after finishing with the stack. 11141945bc45SNicholas Piggin */ 11151945bc45SNicholas Piggin ld r3,_MSR(r1) 111610d91611SNicholas Piggin ld r4,_LINK(r1) 11171945bc45SNicholas Piggin 11181945bc45SNicholas Piggin lhz r11,PACA_IN_MCE(r13) 11191945bc45SNicholas Piggin subi r11,r11,1 11201945bc45SNicholas Piggin sth r11,PACA_IN_MCE(r13) 11211945bc45SNicholas Piggin 112210d91611SNicholas Piggin mtlr r4 112310d91611SNicholas Piggin rlwinm r10,r3,47-31,30,31 112410d91611SNicholas Piggin cmpwi cr1,r10,2 112510d91611SNicholas Piggin bltlr cr1 /* no state loss, return to idle caller */ 112610d91611SNicholas Piggin b idle_return_gpr_loss 11271945bc45SNicholas Piggin#endif 1128afcf0095SNicholas Piggin /* 1129afcf0095SNicholas Piggin * Handle machine check early in real mode. We come here with 1130afcf0095SNicholas Piggin * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. 1131afcf0095SNicholas Piggin */ 1132afcf0095SNicholas PigginEXC_COMMON_BEGIN(machine_check_handle_early) 1133afcf0095SNicholas Piggin std r0,GPR0(r1) /* Save r0 */ 1134afcf0095SNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0x200) 1135afcf0095SNicholas Piggin bl save_nvgprs 1136afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1137afcf0095SNicholas Piggin bl machine_check_early 1138afcf0095SNicholas Piggin std r3,RESULT(r1) /* Save result */ 1139afcf0095SNicholas Piggin ld r12,_MSR(r1) 1140db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1141db7d31acSMahesh Salgaonkar b 4f 1142db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFCLR(CPU_FTR_HVMODE) 11431945bc45SNicholas Piggin 1144afcf0095SNicholas Piggin#ifdef CONFIG_PPC_P7_NAP 1145afcf0095SNicholas Piggin /* 1146afcf0095SNicholas Piggin * Check if thread was in power saving mode. We come here when any 1147afcf0095SNicholas Piggin * of the following is true: 1148afcf0095SNicholas Piggin * a. thread wasn't in power saving mode 1149afcf0095SNicholas Piggin * b. thread was in power saving mode with no state loss, 1150afcf0095SNicholas Piggin * supervisor state loss or hypervisor state loss. 1151afcf0095SNicholas Piggin * 1152afcf0095SNicholas Piggin * Go back to nap/sleep/winkle mode again if (b) is true. 1153afcf0095SNicholas Piggin */ 11541945bc45SNicholas PigginBEGIN_FTR_SECTION 11551945bc45SNicholas Piggin rlwinm. r11,r12,47-31,30,31 11566102c005SNicholas Piggin bne machine_check_idle_common 11571945bc45SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 1158afcf0095SNicholas Piggin#endif 11591945bc45SNicholas Piggin 1160afcf0095SNicholas Piggin /* 1161afcf0095SNicholas Piggin * Check if we are coming from hypervisor userspace. If yes then we 1162afcf0095SNicholas Piggin * continue in host kernel in V mode to deliver the MC event. 1163afcf0095SNicholas Piggin */ 1164afcf0095SNicholas Piggin rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ 1165afcf0095SNicholas Piggin beq 5f 1166db7d31acSMahesh Salgaonkar4: andi. r11,r12,MSR_PR /* See if coming from user. */ 1167afcf0095SNicholas Piggin bne 9f /* continue in V mode if we are. */ 1168afcf0095SNicholas Piggin 1169afcf0095SNicholas Piggin5: 1170afcf0095SNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1171db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1172afcf0095SNicholas Piggin /* 1173afcf0095SNicholas Piggin * We are coming from kernel context. Check if we are coming from 1174afcf0095SNicholas Piggin * guest. if yes, then we can continue. We will fall through 1175afcf0095SNicholas Piggin * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. 1176afcf0095SNicholas Piggin */ 1177afcf0095SNicholas Piggin lbz r11,HSTATE_IN_GUEST(r13) 1178afcf0095SNicholas Piggin cmpwi r11,0 /* Check if coming from guest */ 1179afcf0095SNicholas Piggin bne 9f /* continue if we are. */ 1180db7d31acSMahesh SalgaonkarEND_FTR_SECTION_IFSET(CPU_FTR_HVMODE) 1181afcf0095SNicholas Piggin#endif 1182afcf0095SNicholas Piggin /* 1183afcf0095SNicholas Piggin * At this point we are not sure about what context we come from. 1184afcf0095SNicholas Piggin * Queue up the MCE event and return from the interrupt. 1185afcf0095SNicholas Piggin * But before that, check if this is an un-recoverable exception. 1186afcf0095SNicholas Piggin * If yes, then stay on emergency stack and panic. 1187afcf0095SNicholas Piggin */ 1188afcf0095SNicholas Piggin andi. r11,r12,MSR_RI 1189afcf0095SNicholas Piggin bne 2f 1190afcf0095SNicholas Piggin1: mfspr r11,SPRN_SRR0 1191afcf0095SNicholas Piggin LOAD_HANDLER(r10,unrecover_mce) 1192afcf0095SNicholas Piggin mtspr SPRN_SRR0,r10 1193afcf0095SNicholas Piggin ld r10,PACAKMSR(r13) 1194afcf0095SNicholas Piggin /* 1195afcf0095SNicholas Piggin * We are going down. But there are chances that we might get hit by 1196afcf0095SNicholas Piggin * another MCE during panic path and we may run into unstable state 1197afcf0095SNicholas Piggin * with no way out. Hence, turn ME bit off while going down, so that 1198afcf0095SNicholas Piggin * when another MCE is hit during panic path, system will checkstop 1199afcf0095SNicholas Piggin * and hypervisor will get restarted cleanly by SP. 1200afcf0095SNicholas Piggin */ 1201afcf0095SNicholas Piggin li r3,MSR_ME 1202afcf0095SNicholas Piggin andc r10,r10,r3 /* Turn off MSR_ME */ 1203afcf0095SNicholas Piggin mtspr SPRN_SRR1,r10 1204222f20f1SNicholas Piggin RFI_TO_KERNEL 1205afcf0095SNicholas Piggin b . 1206afcf0095SNicholas Piggin2: 1207afcf0095SNicholas Piggin /* 1208afcf0095SNicholas Piggin * Check if we have successfully handled/recovered from error, if not 1209afcf0095SNicholas Piggin * then stay on emergency stack and panic. 1210afcf0095SNicholas Piggin */ 1211afcf0095SNicholas Piggin ld r3,RESULT(r1) /* Load result */ 1212afcf0095SNicholas Piggin cmpdi r3,0 /* see if we handled MCE successfully */ 1213afcf0095SNicholas Piggin 1214afcf0095SNicholas Piggin beq 1b /* if !handled then panic */ 1215db7d31acSMahesh SalgaonkarBEGIN_FTR_SECTION 1216afcf0095SNicholas Piggin /* 1217afcf0095SNicholas Piggin * Return from MC interrupt. 1218afcf0095SNicholas Piggin * Queue up the MCE event so that we can log it later, while 1219afcf0095SNicholas Piggin * returning from kernel or opal call. 1220afcf0095SNicholas Piggin */ 1221afcf0095SNicholas Piggin bl machine_check_queue_event 1222afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 1223222f20f1SNicholas Piggin RFI_TO_USER_OR_KERNEL 1224db7d31acSMahesh SalgaonkarFTR_SECTION_ELSE 1225db7d31acSMahesh Salgaonkar /* 1226db7d31acSMahesh Salgaonkar * pSeries: Return from MC interrupt. Before that stay on emergency 1227db7d31acSMahesh Salgaonkar * stack and call machine_check_exception to log the MCE event. 1228db7d31acSMahesh Salgaonkar */ 1229db7d31acSMahesh Salgaonkar LOAD_HANDLER(r10,mce_return) 1230db7d31acSMahesh Salgaonkar mtspr SPRN_SRR0,r10 1231db7d31acSMahesh Salgaonkar ld r10,PACAKMSR(r13) 1232db7d31acSMahesh Salgaonkar mtspr SPRN_SRR1,r10 1233db7d31acSMahesh Salgaonkar RFI_TO_KERNEL 1234db7d31acSMahesh Salgaonkar b . 1235db7d31acSMahesh SalgaonkarALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 1236afcf0095SNicholas Piggin9: 1237afcf0095SNicholas Piggin /* Deliver the machine check to host kernel in V mode. */ 1238afcf0095SNicholas Piggin MACHINE_CHECK_HANDLER_WINDUP 1239db7d31acSMahesh Salgaonkar SET_SCRATCH0(r13) /* save r13 */ 12405dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXMC 1241db7d31acSMahesh Salgaonkar b machine_check_pSeries_0 1242afcf0095SNicholas Piggin 1243afcf0095SNicholas PigginEXC_COMMON_BEGIN(unrecover_mce) 1244afcf0095SNicholas Piggin /* Invoke machine_check_exception to print MCE event and panic. */ 1245afcf0095SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1246afcf0095SNicholas Piggin bl machine_check_exception 1247afcf0095SNicholas Piggin /* 1248afcf0095SNicholas Piggin * We will not reach here. Even if we did, there is no way out. Call 1249afcf0095SNicholas Piggin * unrecoverable_exception and die. 1250afcf0095SNicholas Piggin */ 1251afcf0095SNicholas Piggin1: addi r3,r1,STACK_FRAME_OVERHEAD 1252afcf0095SNicholas Piggin bl unrecoverable_exception 1253afcf0095SNicholas Piggin b 1b 1254afcf0095SNicholas Piggin 1255a43c1590SMahesh SalgaonkarEXC_COMMON_BEGIN(mce_return) 1256a43c1590SMahesh Salgaonkar /* Invoke machine_check_exception to print MCE event and return. */ 1257a43c1590SMahesh Salgaonkar addi r3,r1,STACK_FRAME_OVERHEAD 1258a43c1590SMahesh Salgaonkar bl machine_check_exception 1259db7d31acSMahesh Salgaonkar MACHINE_CHECK_HANDLER_WINDUP 1260a43c1590SMahesh Salgaonkar RFI_TO_KERNEL 1261a43c1590SMahesh Salgaonkar b . 12620ebc4cdaSBenjamin Herrenschmidt 1263e779fc93SNicholas PigginEXC_REAL_BEGIN(data_access, 0x300, 0x80) 1264e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 12655dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1266e779fc93SNicholas Piggin b tramp_real_data_access 1267e779fc93SNicholas PigginEXC_REAL_END(data_access, 0x300, 0x80) 1268e779fc93SNicholas Piggin 1269e779fc93SNicholas PigginTRAMP_REAL_BEGIN(tramp_real_data_access) 1270fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0 127138555434SNicholas Piggin /* 127238555434SNicholas Piggin * DAR/DSISR must be read before setting MSR[RI], because 127338555434SNicholas Piggin * a d-side MCE will clobber those registers so is not 127438555434SNicholas Piggin * recoverable if they are live. 127538555434SNicholas Piggin */ 127638555434SNicholas Piggin mfspr r10,SPRN_DAR 127738555434SNicholas Piggin mfspr r11,SPRN_DSISR 127838555434SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 127938555434SNicholas Piggin stw r11,PACA_EXGEN+EX_DSISR(r13) 12802d046308SNicholas PigginEXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1 1281e779fc93SNicholas Piggin 1282e779fc93SNicholas PigginEXC_VIRT_BEGIN(data_access, 0x4300, 0x80) 1283e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 12845dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1285fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0 128638555434SNicholas Piggin mfspr r10,SPRN_DAR 128738555434SNicholas Piggin mfspr r11,SPRN_DSISR 128838555434SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 128938555434SNicholas Piggin stw r11,PACA_EXGEN+EX_DSISR(r13) 12902d046308SNicholas PigginEXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD 1291e779fc93SNicholas PigginEXC_VIRT_END(data_access, 0x4300, 0x80) 1292e779fc93SNicholas Piggin 129380795e6cSNicholas PigginTRAMP_KVM_SKIP(PACA_EXGEN, 0x300) 129480795e6cSNicholas Piggin 129580795e6cSNicholas PigginEXC_COMMON_BEGIN(data_access_common) 129680795e6cSNicholas Piggin /* 129780795e6cSNicholas Piggin * Here r13 points to the paca, r9 contains the saved CR, 129880795e6cSNicholas Piggin * SRR0 and SRR1 are saved in r11 and r12, 129980795e6cSNicholas Piggin * r9 - r13 are saved in paca->exgen. 130038555434SNicholas Piggin * EX_DAR and EX_DSISR have saved DAR/DSISR 130180795e6cSNicholas Piggin */ 1302d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x300) 130380795e6cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 130480795e6cSNicholas Piggin ld r12,_MSR(r1) 130580795e6cSNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 130680795e6cSNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 130780795e6cSNicholas Piggin li r5,0x300 130880795e6cSNicholas Piggin std r3,_DAR(r1) 130980795e6cSNicholas Piggin std r4,_DSISR(r1) 131080795e6cSNicholas PigginBEGIN_MMU_FTR_SECTION 131180795e6cSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 131280795e6cSNicholas PigginMMU_FTR_SECTION_ELSE 131380795e6cSNicholas Piggin b handle_page_fault 131480795e6cSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 131580795e6cSNicholas Piggin 13160ebc4cdaSBenjamin Herrenschmidt 13171a6822d1SNicholas PigginEXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) 1318e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 13195dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXSLB 1320e779fc93SNicholas Piggin b tramp_real_data_access_slb 13211a6822d1SNicholas PigginEXC_REAL_END(data_access_slb, 0x380, 0x80) 13220ebc4cdaSBenjamin Herrenschmidt 1323e779fc93SNicholas PigginTRAMP_REAL_BEGIN(tramp_real_data_access_slb) 1324fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0 132538555434SNicholas Piggin mfspr r10,SPRN_DAR 132638555434SNicholas Piggin std r10,PACA_EXSLB+EX_DAR(r13) 13272d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1 1328e779fc93SNicholas Piggin 13291a6822d1SNicholas PigginEXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) 1330e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 13315dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXSLB 1332fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0 133338555434SNicholas Piggin mfspr r10,SPRN_DAR 133438555434SNicholas Piggin std r10,PACA_EXSLB+EX_DAR(r13) 13352d046308SNicholas Piggin EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD 13361a6822d1SNicholas PigginEXC_VIRT_END(data_access_slb, 0x4380, 0x80) 133748e7b769SNicholas Piggin 13382b9af6e4SNicholas PigginTRAMP_KVM_SKIP(PACA_EXSLB, 0x380) 13392b9af6e4SNicholas Piggin 134048e7b769SNicholas PigginEXC_COMMON_BEGIN(data_access_slb_common) 1341d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXSLB, 0x380) 134248e7b769SNicholas Piggin ld r4,PACA_EXSLB+EX_DAR(r13) 134348e7b769SNicholas Piggin std r4,_DAR(r1) 134448e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 13457100e870SNicholas PigginBEGIN_MMU_FTR_SECTION 13467100e870SNicholas Piggin /* HPT case, do SLB fault */ 134748e7b769SNicholas Piggin bl do_slb_fault 134848e7b769SNicholas Piggin cmpdi r3,0 134948e7b769SNicholas Piggin bne- 1f 135048e7b769SNicholas Piggin b fast_exception_return 135148e7b769SNicholas Piggin1: /* Error case */ 13527100e870SNicholas PigginMMU_FTR_SECTION_ELSE 13537100e870SNicholas Piggin /* Radix case, access is outside page table range */ 13547100e870SNicholas Piggin li r3,-EFAULT 13557100e870SNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 135648e7b769SNicholas Piggin std r3,RESULT(r1) 135748e7b769SNicholas Piggin bl save_nvgprs 135848e7b769SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 135948e7b769SNicholas Piggin ld r4,_DAR(r1) 136048e7b769SNicholas Piggin ld r5,RESULT(r1) 136148e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 136248e7b769SNicholas Piggin bl do_bad_slb_fault 136348e7b769SNicholas Piggin b ret_from_except 136448e7b769SNicholas Piggin 13652b9af6e4SNicholas Piggin 13661a6822d1SNicholas PigginEXC_REAL(instruction_access, 0x400, 0x80) 13671a6822d1SNicholas PigginEXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) 136827ce77dfSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x400) 136927ce77dfSNicholas Piggin 137027ce77dfSNicholas PigginEXC_COMMON_BEGIN(instruction_access_common) 1371d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x400) 137227ce77dfSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 137327ce77dfSNicholas Piggin ld r12,_MSR(r1) 137427ce77dfSNicholas Piggin ld r3,_NIP(r1) 1375475b581fSMichael Ellerman andis. r4,r12,DSISR_SRR1_MATCH_64S@h 137627ce77dfSNicholas Piggin li r5,0x400 137727ce77dfSNicholas Piggin std r3,_DAR(r1) 137827ce77dfSNicholas Piggin std r4,_DSISR(r1) 137927ce77dfSNicholas PigginBEGIN_MMU_FTR_SECTION 138027ce77dfSNicholas Piggin b do_hash_page /* Try to handle as hpte fault */ 138127ce77dfSNicholas PigginMMU_FTR_SECTION_ELSE 138227ce77dfSNicholas Piggin b handle_page_fault 138327ce77dfSNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 138427ce77dfSNicholas Piggin 13850ebc4cdaSBenjamin Herrenschmidt 1386fc557537SNicholas Piggin__EXC_REAL(instruction_access_slb, 0x480, 0x80, PACA_EXSLB) 1387fc557537SNicholas Piggin__EXC_VIRT(instruction_access_slb, 0x4480, 0x80, 0x480, PACA_EXSLB) 13888d04631aSNicholas PigginTRAMP_KVM(PACA_EXSLB, 0x480) 13898d04631aSNicholas Piggin 139048e7b769SNicholas PigginEXC_COMMON_BEGIN(instruction_access_slb_common) 1391d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXSLB, 0x480) 139248e7b769SNicholas Piggin ld r4,_NIP(r1) 139354be0b9cSMichael Ellerman addi r3,r1,STACK_FRAME_OVERHEAD 13947100e870SNicholas PigginBEGIN_MMU_FTR_SECTION 13957100e870SNicholas Piggin /* HPT case, do SLB fault */ 139648e7b769SNicholas Piggin bl do_slb_fault 139748e7b769SNicholas Piggin cmpdi r3,0 139848e7b769SNicholas Piggin bne- 1f 139948e7b769SNicholas Piggin b fast_exception_return 140048e7b769SNicholas Piggin1: /* Error case */ 14017100e870SNicholas PigginMMU_FTR_SECTION_ELSE 14027100e870SNicholas Piggin /* Radix case, access is outside page table range */ 14037100e870SNicholas Piggin li r3,-EFAULT 14047100e870SNicholas PigginALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) 140548e7b769SNicholas Piggin std r3,RESULT(r1) 140648e7b769SNicholas Piggin bl save_nvgprs 140748e7b769SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 140848e7b769SNicholas Piggin ld r4,_NIP(r1) 140948e7b769SNicholas Piggin ld r5,RESULT(r1) 141048e7b769SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 141148e7b769SNicholas Piggin bl do_bad_slb_fault 141254be0b9cSMichael Ellerman b ret_from_except 14135e46e29eSNicholas Piggin 141448e7b769SNicholas Piggin 14151a6822d1SNicholas PigginEXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) 1416fc557537SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 1417fc557537SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 141880bd9177SNicholas PigginBEGIN_FTR_SECTION 1419fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED 1420fc557537SNicholas Piggin EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1 1421de56a948SPaul MackerrasFTR_SECTION_ELSE 1422fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED 1423fc557537SNicholas Piggin EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1 1424969391c5SPaul MackerrasALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) 14251a6822d1SNicholas PigginEXC_REAL_END(hardware_interrupt, 0x500, 0x100) 1426a5d4f3adSBenjamin Herrenschmidt 14271a6822d1SNicholas PigginEXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) 1428fc557537SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 1429fc557537SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 143080bd9177SNicholas PigginBEGIN_FTR_SECTION 1431fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED 1432fc557537SNicholas Piggin EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV 1433c138e588SNicholas PigginFTR_SECTION_ELSE 1434fc557537SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED 1435fc557537SNicholas Piggin EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD 1436c138e588SNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 14371a6822d1SNicholas PigginEXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) 1438c138e588SNicholas Piggin 14397ede5317SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x500) 14407ede5317SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x500) 1441c138e588SNicholas PigginEXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) 1442c138e588SNicholas Piggin 1443c138e588SNicholas Piggin 1444e779fc93SNicholas PigginEXC_REAL_BEGIN(alignment, 0x600, 0x100) 1445e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 14465dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1447fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0 144838555434SNicholas Piggin mfspr r10,SPRN_DAR 144938555434SNicholas Piggin mfspr r11,SPRN_DSISR 145038555434SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 145138555434SNicholas Piggin stw r11,PACA_EXGEN+EX_DSISR(r13) 14522d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1 1453e779fc93SNicholas PigginEXC_REAL_END(alignment, 0x600, 0x100) 1454e779fc93SNicholas Piggin 1455e779fc93SNicholas PigginEXC_VIRT_BEGIN(alignment, 0x4600, 0x100) 1456e779fc93SNicholas Piggin SET_SCRATCH0(r13) /* save r13 */ 14575dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1458fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0 145938555434SNicholas Piggin mfspr r10,SPRN_DAR 146038555434SNicholas Piggin mfspr r11,SPRN_DSISR 146138555434SNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 146238555434SNicholas Piggin stw r11,PACA_EXGEN+EX_DSISR(r13) 14632d046308SNicholas Piggin EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD 1464e779fc93SNicholas PigginEXC_VIRT_END(alignment, 0x4600, 0x100) 1465e779fc93SNicholas Piggin 1466da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x600) 1467f9aa6714SNicholas PigginEXC_COMMON_BEGIN(alignment_common) 1468d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x600) 1469f9aa6714SNicholas Piggin ld r3,PACA_EXGEN+EX_DAR(r13) 1470f9aa6714SNicholas Piggin lwz r4,PACA_EXGEN+EX_DSISR(r13) 1471f9aa6714SNicholas Piggin std r3,_DAR(r1) 1472f9aa6714SNicholas Piggin std r4,_DSISR(r1) 1473f9aa6714SNicholas Piggin bl save_nvgprs 1474f9aa6714SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1475f9aa6714SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1476f9aa6714SNicholas Piggin bl alignment_exception 1477f9aa6714SNicholas Piggin b ret_from_except 1478f9aa6714SNicholas Piggin 1479b01c8b54SPaul Mackerras 14801a6822d1SNicholas PigginEXC_REAL(program_check, 0x700, 0x100) 14811a6822d1SNicholas PigginEXC_VIRT(program_check, 0x4700, 0x100, 0x700) 1482da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x700) 148311e87346SNicholas PigginEXC_COMMON_BEGIN(program_check_common) 1484265e60a1SCyril Bur /* 1485265e60a1SCyril Bur * It's possible to receive a TM Bad Thing type program check with 1486265e60a1SCyril Bur * userspace register values (in particular r1), but with SRR1 reporting 1487265e60a1SCyril Bur * that we came from the kernel. Normally that would confuse the bad 1488265e60a1SCyril Bur * stack logic, and we would report a bad kernel stack pointer. Instead 1489265e60a1SCyril Bur * we switch to the emergency stack if we're taking a TM Bad Thing from 1490265e60a1SCyril Bur * the kernel. 1491265e60a1SCyril Bur */ 1492265e60a1SCyril Bur li r10,MSR_PR /* Build a mask of MSR_PR .. */ 1493265e60a1SCyril Bur oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ 1494265e60a1SCyril Bur and r10,r10,r12 /* Mask SRR1 with that. */ 1495265e60a1SCyril Bur srdi r10,r10,8 /* Shift it so we can compare */ 1496265e60a1SCyril Bur cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ 1497265e60a1SCyril Bur bne 1f /* If != go to normal path. */ 1498265e60a1SCyril Bur 1499265e60a1SCyril Bur /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ 1500265e60a1SCyril Bur andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ 1501265e60a1SCyril Bur /* 3 in EXCEPTION_PROLOG_COMMON */ 1502265e60a1SCyril Bur mr r10,r1 /* Save r1 */ 1503265e60a1SCyril Bur ld r1,PACAEMERGSP(r13) /* Use emergency stack */ 1504265e60a1SCyril Bur subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 1505265e60a1SCyril Bur b 3f /* Jump into the macro !! */ 1506d064151fSNicholas Piggin1: EXCEPTION_COMMON(PACA_EXGEN, 0x700) 150711e87346SNicholas Piggin bl save_nvgprs 150811e87346SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 150911e87346SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 151011e87346SNicholas Piggin bl program_check_exception 151111e87346SNicholas Piggin b ret_from_except 151211e87346SNicholas Piggin 1513a485c709SPaul Mackerras 15141a6822d1SNicholas PigginEXC_REAL(fp_unavailable, 0x800, 0x100) 15151a6822d1SNicholas PigginEXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) 1516da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0x800) 1517c78d9b97SNicholas PigginEXC_COMMON_BEGIN(fp_unavailable_common) 1518d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0x800) 1519c78d9b97SNicholas Piggin bne 1f /* if from user, just load it up */ 1520c78d9b97SNicholas Piggin bl save_nvgprs 1521c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1522c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1523c78d9b97SNicholas Piggin bl kernel_fp_unavailable_exception 1524c78d9b97SNicholas Piggin BUG_OPCODE 1525c78d9b97SNicholas Piggin1: 1526c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1527c78d9b97SNicholas PigginBEGIN_FTR_SECTION 1528c78d9b97SNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1529c78d9b97SNicholas Piggin * transaction), go do TM stuff 1530c78d9b97SNicholas Piggin */ 1531c78d9b97SNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1532c78d9b97SNicholas Piggin bne- 2f 1533c78d9b97SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_TM) 1534c78d9b97SNicholas Piggin#endif 1535c78d9b97SNicholas Piggin bl load_up_fpu 1536c78d9b97SNicholas Piggin b fast_exception_return 1537c78d9b97SNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1538c78d9b97SNicholas Piggin2: /* User process was in a transaction */ 1539c78d9b97SNicholas Piggin bl save_nvgprs 1540c78d9b97SNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1541c78d9b97SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1542c78d9b97SNicholas Piggin bl fp_unavailable_tm 1543c78d9b97SNicholas Piggin b ret_from_except 1544c78d9b97SNicholas Piggin#endif 1545c78d9b97SNicholas Piggin 1546b01c8b54SPaul Mackerras 1547a048a07dSNicholas PigginEXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED) 1548f14e953bSMadhavan SrinivasanEXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED) 154939c0da57SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x900) 155039c0da57SNicholas PigginEXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) 155139c0da57SNicholas Piggin 15520ebc4cdaSBenjamin Herrenschmidt 15531a6822d1SNicholas PigginEXC_REAL_HV(hdecrementer, 0x980, 0x80) 15541a6822d1SNicholas PigginEXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) 1555facc6d74SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0x980) 1556facc6d74SNicholas PigginEXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) 1557facc6d74SNicholas Piggin 1558da2bc464SMichael Ellerman 1559f14e953bSMadhavan SrinivasanEXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED) 1560f14e953bSMadhavan SrinivasanEXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED) 1561da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xa00) 1562ca243163SNicholas Piggin#ifdef CONFIG_PPC_DOORBELL 1563ca243163SNicholas PigginEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) 1564ca243163SNicholas Piggin#else 1565ca243163SNicholas PigginEXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) 1566ca243163SNicholas Piggin#endif 1567ca243163SNicholas Piggin 1568da2bc464SMichael Ellerman 15691a6822d1SNicholas PigginEXC_REAL(trap_0b, 0xb00, 0x100) 15701a6822d1SNicholas PigginEXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) 1571da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xb00) 1572341215dcSNicholas PigginEXC_COMMON(trap_0b_common, 0xb00, unknown_exception) 1573341215dcSNicholas Piggin 1574acd7d8ceSNicholas Piggin/* 1575acd7d8ceSNicholas Piggin * system call / hypercall (0xc00, 0x4c00) 1576acd7d8ceSNicholas Piggin * 1577acd7d8ceSNicholas Piggin * The system call exception is invoked with "sc 0" and does not alter HV bit. 1578acd7d8ceSNicholas Piggin * There is support for kernel code to invoke system calls but there are no 1579acd7d8ceSNicholas Piggin * in-tree users. 1580acd7d8ceSNicholas Piggin * 1581acd7d8ceSNicholas Piggin * The hypercall is invoked with "sc 1" and sets HV=1. 1582acd7d8ceSNicholas Piggin * 1583acd7d8ceSNicholas Piggin * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to 1584acd7d8ceSNicholas Piggin * 0x4c00 virtual mode. 1585acd7d8ceSNicholas Piggin * 1586acd7d8ceSNicholas Piggin * Call convention: 1587acd7d8ceSNicholas Piggin * 1588acd7d8ceSNicholas Piggin * syscall register convention is in Documentation/powerpc/syscall64-abi.txt 1589acd7d8ceSNicholas Piggin * 1590acd7d8ceSNicholas Piggin * For hypercalls, the register convention is as follows: 1591acd7d8ceSNicholas Piggin * r0 volatile 1592acd7d8ceSNicholas Piggin * r1-2 nonvolatile 1593acd7d8ceSNicholas Piggin * r3 volatile parameter and return value for status 1594acd7d8ceSNicholas Piggin * r4-r10 volatile input and output value 1595acd7d8ceSNicholas Piggin * r11 volatile hypercall number and output value 159676fc0cfcSNicholas Piggin * r12 volatile input and output value 1597acd7d8ceSNicholas Piggin * r13-r31 nonvolatile 1598acd7d8ceSNicholas Piggin * LR nonvolatile 1599acd7d8ceSNicholas Piggin * CTR volatile 1600acd7d8ceSNicholas Piggin * XER volatile 1601acd7d8ceSNicholas Piggin * CR0-1 CR5-7 volatile 1602acd7d8ceSNicholas Piggin * CR2-4 nonvolatile 1603acd7d8ceSNicholas Piggin * Other registers nonvolatile 1604acd7d8ceSNicholas Piggin * 1605acd7d8ceSNicholas Piggin * The intersection of volatile registers that don't contain possible 160676fc0cfcSNicholas Piggin * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry 160776fc0cfcSNicholas Piggin * without saving, though xer is not a good idea to use, as hardware may 160876fc0cfcSNicholas Piggin * interpret some bits so it may be costly to change them. 1609acd7d8ceSNicholas Piggin */ 16101b4d4a79SNicholas Piggin.macro SYSTEM_CALL virt 1611bc355125SPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1612bc355125SPaul Mackerras /* 1613acd7d8ceSNicholas Piggin * There is a little bit of juggling to get syscall and hcall 161476fc0cfcSNicholas Piggin * working well. Save r13 in ctr to avoid using SPRG scratch 161576fc0cfcSNicholas Piggin * register. 1616acd7d8ceSNicholas Piggin * 1617acd7d8ceSNicholas Piggin * Userspace syscalls have already saved the PPR, hcalls must save 1618acd7d8ceSNicholas Piggin * it before setting HMT_MEDIUM. 1619bc355125SPaul Mackerras */ 16201b4d4a79SNicholas Piggin mtctr r13 16211b4d4a79SNicholas Piggin GET_PACA(r13) 16221b4d4a79SNicholas Piggin std r10,PACA_EXGEN+EX_R10(r13) 16231b4d4a79SNicholas Piggin INTERRUPT_TO_KERNEL 16241b4d4a79SNicholas Piggin KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */ 16251b4d4a79SNicholas Piggin mfctr r9 1626bc355125SPaul Mackerras#else 16271b4d4a79SNicholas Piggin mr r9,r13 16281b4d4a79SNicholas Piggin GET_PACA(r13) 16291b4d4a79SNicholas Piggin INTERRUPT_TO_KERNEL 1630bc355125SPaul Mackerras#endif 1631bc355125SPaul Mackerras 1632727f1361SMichael Ellerman#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 16331b4d4a79SNicholas PigginBEGIN_FTR_SECTION 16341b4d4a79SNicholas Piggin cmpdi r0,0x1ebe 16351b4d4a79SNicholas Piggin beq- 1f 16361b4d4a79SNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) 16371b4d4a79SNicholas Piggin#endif 16385c2511bfSMichael Ellerman 1639b0b2a93dSNicholas Piggin /* We reach here with PACA in r13, r13 in r9. */ 16401b4d4a79SNicholas Piggin mfspr r11,SPRN_SRR0 16411b4d4a79SNicholas Piggin mfspr r12,SPRN_SRR1 1642b0b2a93dSNicholas Piggin 1643b0b2a93dSNicholas Piggin HMT_MEDIUM 1644b0b2a93dSNicholas Piggin 1645b0b2a93dSNicholas Piggin .if ! \virt 16461b4d4a79SNicholas Piggin __LOAD_HANDLER(r10, system_call_common) 16471b4d4a79SNicholas Piggin mtspr SPRN_SRR0,r10 16481b4d4a79SNicholas Piggin ld r10,PACAKMSR(r13) 16491b4d4a79SNicholas Piggin mtspr SPRN_SRR1,r10 16501b4d4a79SNicholas Piggin RFI_TO_KERNEL 16511b4d4a79SNicholas Piggin b . /* prevent speculative execution */ 16521b4d4a79SNicholas Piggin .else 16531b4d4a79SNicholas Piggin li r10,MSR_RI 16541b4d4a79SNicholas Piggin mtmsrd r10,1 /* Set RI (EE=0) */ 1655b0b2a93dSNicholas Piggin#ifdef CONFIG_RELOCATABLE 1656b0b2a93dSNicholas Piggin __LOAD_HANDLER(r10, system_call_common) 1657b0b2a93dSNicholas Piggin mtctr r10 1658b0b2a93dSNicholas Piggin bctr 1659b0b2a93dSNicholas Piggin#else 16601b4d4a79SNicholas Piggin b system_call_common 1661d807ad37SNicholas Piggin#endif 16621b4d4a79SNicholas Piggin .endif 16631b4d4a79SNicholas Piggin 16641b4d4a79SNicholas Piggin#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH 16651b4d4a79SNicholas Piggin /* Fast LE/BE switch system call */ 16661b4d4a79SNicholas Piggin1: mfspr r12,SPRN_SRR1 16671b4d4a79SNicholas Piggin xori r12,r12,MSR_LE 16681b4d4a79SNicholas Piggin mtspr SPRN_SRR1,r12 16691b4d4a79SNicholas Piggin mr r13,r9 16701b4d4a79SNicholas Piggin RFI_TO_USER /* return to userspace */ 16711b4d4a79SNicholas Piggin b . /* prevent speculative execution */ 16721b4d4a79SNicholas Piggin#endif 16731b4d4a79SNicholas Piggin.endm 1674d807ad37SNicholas Piggin 16751a6822d1SNicholas PigginEXC_REAL_BEGIN(system_call, 0xc00, 0x100) 16761b4d4a79SNicholas Piggin SYSTEM_CALL 0 16771a6822d1SNicholas PigginEXC_REAL_END(system_call, 0xc00, 0x100) 1678b01c8b54SPaul Mackerras 16791a6822d1SNicholas PigginEXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) 16801b4d4a79SNicholas Piggin SYSTEM_CALL 1 16811a6822d1SNicholas PigginEXC_VIRT_END(system_call, 0x4c00, 0x100) 1682d807ad37SNicholas Piggin 1683acd7d8ceSNicholas Piggin#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 1684acd7d8ceSNicholas Piggin /* 1685acd7d8ceSNicholas Piggin * This is a hcall, so register convention is as above, with these 1686acd7d8ceSNicholas Piggin * differences: 1687acd7d8ceSNicholas Piggin * r13 = PACA 168876fc0cfcSNicholas Piggin * ctr = orig r13 168976fc0cfcSNicholas Piggin * orig r10 saved in PACA 1690acd7d8ceSNicholas Piggin */ 1691acd7d8ceSNicholas PigginTRAMP_KVM_BEGIN(do_kvm_0xc00) 1692acd7d8ceSNicholas Piggin /* 1693acd7d8ceSNicholas Piggin * Save the PPR (on systems that support it) before changing to 1694acd7d8ceSNicholas Piggin * HMT_MEDIUM. That allows the KVM code to save that value into the 1695acd7d8ceSNicholas Piggin * guest state (it is the guest's PPR value). 1696acd7d8ceSNicholas Piggin */ 169776fc0cfcSNicholas Piggin OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) 1698acd7d8ceSNicholas Piggin HMT_MEDIUM 169976fc0cfcSNicholas Piggin OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) 1700acd7d8ceSNicholas Piggin mfctr r10 170176fc0cfcSNicholas Piggin SET_SCRATCH0(r10) 1702acd7d8ceSNicholas Piggin std r9,PACA_EXGEN+EX_R9(r13) 1703acd7d8ceSNicholas Piggin mfcr r9 170417bdc064SNicholas Piggin KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0 1705acd7d8ceSNicholas Piggin#endif 1706da2bc464SMichael Ellerman 1707d807ad37SNicholas Piggin 17081a6822d1SNicholas PigginEXC_REAL(single_step, 0xd00, 0x100) 17091a6822d1SNicholas PigginEXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) 1710da2bc464SMichael EllermanTRAMP_KVM(PACA_EXGEN, 0xd00) 1711bc6675c6SNicholas PigginEXC_COMMON(single_step_common, 0xd00, single_step_exception) 1712da2bc464SMichael Ellerman 17131a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) 1714da0e7e62SMichael EllermanEXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) 1715f5c32c1dSNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) 1716f5c32c1dSNicholas PigginEXC_COMMON_BEGIN(h_data_storage_common) 1717f5c32c1dSNicholas Piggin mfspr r10,SPRN_HDAR 1718f5c32c1dSNicholas Piggin std r10,PACA_EXGEN+EX_DAR(r13) 1719f5c32c1dSNicholas Piggin mfspr r10,SPRN_HDSISR 1720f5c32c1dSNicholas Piggin stw r10,PACA_EXGEN+EX_DSISR(r13) 1721d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xe00) 1722f5c32c1dSNicholas Piggin bl save_nvgprs 1723f5c32c1dSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1724f5c32c1dSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1725d7b45615SSuraj Jitindar SinghBEGIN_MMU_FTR_SECTION 1726d7b45615SSuraj Jitindar Singh ld r4,PACA_EXGEN+EX_DAR(r13) 1727d7b45615SSuraj Jitindar Singh lwz r5,PACA_EXGEN+EX_DSISR(r13) 1728d7b45615SSuraj Jitindar Singh std r4,_DAR(r1) 1729d7b45615SSuraj Jitindar Singh std r5,_DSISR(r1) 1730d7b45615SSuraj Jitindar Singh li r5,SIGSEGV 1731d7b45615SSuraj Jitindar Singh bl bad_page_fault 1732d7b45615SSuraj Jitindar SinghMMU_FTR_SECTION_ELSE 1733f5c32c1dSNicholas Piggin bl unknown_exception 1734d7b45615SSuraj Jitindar SinghALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX) 1735f5c32c1dSNicholas Piggin b ret_from_except 1736f5c32c1dSNicholas Piggin 17371707dd16SPaul Mackerras 17381a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) 1739da0e7e62SMichael EllermanEXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) 174082517cabSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe20) 174182517cabSNicholas PigginEXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) 174282517cabSNicholas Piggin 17431707dd16SPaul Mackerras 17441a6822d1SNicholas PigginEXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) 17451a6822d1SNicholas PigginEXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) 1746031b4026SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe40) 1747031b4026SNicholas PigginEXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) 1748031b4026SNicholas Piggin 17491707dd16SPaul Mackerras 1750e0319829SNicholas Piggin/* 1751e0319829SNicholas Piggin * hmi_exception trampoline is a special case. It jumps to hmi_exception_early 1752e0319829SNicholas Piggin * first, and then eventaully from there to the trampoline to get into virtual 1753e0319829SNicholas Piggin * mode. 1754e0319829SNicholas Piggin */ 17551a6822d1SNicholas Piggin__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) 1756f14e953bSMadhavan Srinivasan__TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED) 17571a6822d1SNicholas PigginEXC_VIRT_NONE(0x4e60, 0x20) 175862f9b03bSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe60) 175962f9b03bSNicholas PigginTRAMP_REAL_BEGIN(hmi_exception_early) 1760fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0 176162f9b03bSNicholas Piggin mr r10,r1 /* Save r1 */ 1762a4087a4dSNicholas Piggin ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ 176362f9b03bSNicholas Piggin subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ 176462f9b03bSNicholas Piggin mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ 1765a4087a4dSNicholas Piggin mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ 1766a4087a4dSNicholas Piggin EXCEPTION_PROLOG_COMMON_1() 1767890274c2SMichael Ellerman /* We don't touch AMR here, we never go to virtual mode */ 176862f9b03bSNicholas Piggin EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) 176962f9b03bSNicholas Piggin EXCEPTION_PROLOG_COMMON_3(0xe60) 177062f9b03bSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1771505a314fSBenjamin Herrenschmidt BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */ 17725080332cSMichael Neuling cmpdi cr0,r3,0 177367d4160aSNicholas Piggin bne 1f 17745080332cSMichael Neuling 1775*391e941bSNicholas Piggin EXCEPTION_RESTORE_REGS EXC_HV 1776222f20f1SNicholas Piggin HRFI_TO_USER_OR_KERNEL 17775080332cSMichael Neuling 177867d4160aSNicholas Piggin1: 177962f9b03bSNicholas Piggin /* 178062f9b03bSNicholas Piggin * Go to virtual mode and pull the HMI event information from 178162f9b03bSNicholas Piggin * firmware. 178262f9b03bSNicholas Piggin */ 1783*391e941bSNicholas Piggin EXCEPTION_RESTORE_REGS EXC_HV 178462f9b03bSNicholas Piggin SET_SCRATCH0(r13) 17855dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 178662f9b03bSNicholas Piggin b tramp_real_hmi_exception 178762f9b03bSNicholas Piggin 17885080332cSMichael NeulingEXC_COMMON_BEGIN(hmi_exception_common) 178947169fbaSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xe60) 179047169fbaSNicholas Piggin FINISH_NAP 179147169fbaSNicholas Piggin bl save_nvgprs 179247169fbaSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 179347169fbaSNicholas Piggin RUNLATCH_ON 1794c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1795c06075f3SNicholas Piggin bl handle_hmi_exception 1796c06075f3SNicholas Piggin b ret_from_except 17971707dd16SPaul Mackerras 1798f14e953bSMadhavan SrinivasanEXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED) 1799f14e953bSMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED) 18009bcb81bfSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xe80) 18019bcb81bfSNicholas Piggin#ifdef CONFIG_PPC_DOORBELL 18029bcb81bfSNicholas PigginEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) 18039bcb81bfSNicholas Piggin#else 18049bcb81bfSNicholas PigginEXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) 18059bcb81bfSNicholas Piggin#endif 18069bcb81bfSNicholas Piggin 18070ebc4cdaSBenjamin Herrenschmidt 1808f14e953bSMadhavan SrinivasanEXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED) 1809f14e953bSMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED) 181074408776SNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xea0) 181174408776SNicholas PigginEXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) 181274408776SNicholas Piggin 18139baaef0aSBenjamin Herrenschmidt 18141a6822d1SNicholas PigginEXC_REAL_NONE(0xec0, 0x20) 18151a6822d1SNicholas PigginEXC_VIRT_NONE(0x4ec0, 0x20) 18161a6822d1SNicholas PigginEXC_REAL_NONE(0xee0, 0x20) 18171a6822d1SNicholas PigginEXC_VIRT_NONE(0x4ee0, 0x20) 1818bda7fea2SNicholas Piggin 18190ebc4cdaSBenjamin Herrenschmidt 1820f442d004SMadhavan SrinivasanEXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED) 1821f442d004SMadhavan SrinivasanEXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED) 1822b1c7f150SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf00) 1823b1c7f150SNicholas PigginEXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) 1824b1c7f150SNicholas Piggin 18250ebc4cdaSBenjamin Herrenschmidt 18261a6822d1SNicholas PigginEXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) 18271a6822d1SNicholas PigginEXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) 1828d1a0ca9cSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf20) 1829d1a0ca9cSNicholas PigginEXC_COMMON_BEGIN(altivec_unavailable_common) 1830d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xf20) 1831d1a0ca9cSNicholas Piggin#ifdef CONFIG_ALTIVEC 1832d1a0ca9cSNicholas PigginBEGIN_FTR_SECTION 1833d1a0ca9cSNicholas Piggin beq 1f 1834d1a0ca9cSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1835d1a0ca9cSNicholas Piggin BEGIN_FTR_SECTION_NESTED(69) 1836d1a0ca9cSNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1837d1a0ca9cSNicholas Piggin * transaction), go do TM stuff 1838d1a0ca9cSNicholas Piggin */ 1839d1a0ca9cSNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1840d1a0ca9cSNicholas Piggin bne- 2f 1841d1a0ca9cSNicholas Piggin END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1842d1a0ca9cSNicholas Piggin#endif 1843d1a0ca9cSNicholas Piggin bl load_up_altivec 1844d1a0ca9cSNicholas Piggin b fast_exception_return 1845d1a0ca9cSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1846d1a0ca9cSNicholas Piggin2: /* User process was in a transaction */ 1847d1a0ca9cSNicholas Piggin bl save_nvgprs 1848d1a0ca9cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1849d1a0ca9cSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1850d1a0ca9cSNicholas Piggin bl altivec_unavailable_tm 1851d1a0ca9cSNicholas Piggin b ret_from_except 1852d1a0ca9cSNicholas Piggin#endif 1853d1a0ca9cSNicholas Piggin1: 1854d1a0ca9cSNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 1855d1a0ca9cSNicholas Piggin#endif 1856d1a0ca9cSNicholas Piggin bl save_nvgprs 1857d1a0ca9cSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1858d1a0ca9cSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1859d1a0ca9cSNicholas Piggin bl altivec_unavailable_exception 1860d1a0ca9cSNicholas Piggin b ret_from_except 1861d1a0ca9cSNicholas Piggin 18620ebc4cdaSBenjamin Herrenschmidt 18631a6822d1SNicholas PigginEXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) 18641a6822d1SNicholas PigginEXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) 1865792cbdddSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf40) 1866792cbdddSNicholas PigginEXC_COMMON_BEGIN(vsx_unavailable_common) 1867d064151fSNicholas Piggin EXCEPTION_COMMON(PACA_EXGEN, 0xf40) 1868792cbdddSNicholas Piggin#ifdef CONFIG_VSX 1869792cbdddSNicholas PigginBEGIN_FTR_SECTION 1870792cbdddSNicholas Piggin beq 1f 1871792cbdddSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1872792cbdddSNicholas Piggin BEGIN_FTR_SECTION_NESTED(69) 1873792cbdddSNicholas Piggin /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in 1874792cbdddSNicholas Piggin * transaction), go do TM stuff 1875792cbdddSNicholas Piggin */ 1876792cbdddSNicholas Piggin rldicl. r0, r12, (64-MSR_TS_LG), (64-2) 1877792cbdddSNicholas Piggin bne- 2f 1878792cbdddSNicholas Piggin END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) 1879792cbdddSNicholas Piggin#endif 1880792cbdddSNicholas Piggin b load_up_vsx 1881792cbdddSNicholas Piggin#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 1882792cbdddSNicholas Piggin2: /* User process was in a transaction */ 1883792cbdddSNicholas Piggin bl save_nvgprs 1884792cbdddSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1885792cbdddSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1886792cbdddSNicholas Piggin bl vsx_unavailable_tm 1887792cbdddSNicholas Piggin b ret_from_except 1888792cbdddSNicholas Piggin#endif 1889792cbdddSNicholas Piggin1: 1890792cbdddSNicholas PigginEND_FTR_SECTION_IFSET(CPU_FTR_VSX) 1891792cbdddSNicholas Piggin#endif 1892792cbdddSNicholas Piggin bl save_nvgprs 1893792cbdddSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 1894792cbdddSNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 1895792cbdddSNicholas Piggin bl vsx_unavailable_exception 1896792cbdddSNicholas Piggin b ret_from_except 1897792cbdddSNicholas Piggin 1898d0c0c9a1SMichael Neuling 18991a6822d1SNicholas PigginEXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) 19001a6822d1SNicholas PigginEXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) 19011134713cSNicholas PigginTRAMP_KVM(PACA_EXGEN, 0xf60) 19021134713cSNicholas PigginEXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) 19031134713cSNicholas Piggin 1904da2bc464SMichael Ellerman 19051a6822d1SNicholas PigginEXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) 19061a6822d1SNicholas PigginEXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) 190714b0072cSNicholas PigginTRAMP_KVM_HV(PACA_EXGEN, 0xf80) 190814b0072cSNicholas PigginEXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) 190914b0072cSNicholas Piggin 1910da2bc464SMichael Ellerman 19111a6822d1SNicholas PigginEXC_REAL_NONE(0xfa0, 0x20) 19121a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fa0, 0x20) 19131a6822d1SNicholas PigginEXC_REAL_NONE(0xfc0, 0x20) 19141a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fc0, 0x20) 19151a6822d1SNicholas PigginEXC_REAL_NONE(0xfe0, 0x20) 19161a6822d1SNicholas PigginEXC_VIRT_NONE(0x4fe0, 0x20) 19171a6822d1SNicholas Piggin 19181a6822d1SNicholas PigginEXC_REAL_NONE(0x1000, 0x100) 19191a6822d1SNicholas PigginEXC_VIRT_NONE(0x5000, 0x100) 19201a6822d1SNicholas PigginEXC_REAL_NONE(0x1100, 0x100) 19211a6822d1SNicholas PigginEXC_VIRT_NONE(0x5100, 0x100) 1922da2bc464SMichael Ellerman 19230ebc4cdaSBenjamin Herrenschmidt#ifdef CONFIG_CBE_RAS 19241a6822d1SNicholas PigginEXC_REAL_HV(cbe_system_error, 0x1200, 0x100) 19251a6822d1SNicholas PigginEXC_VIRT_NONE(0x5200, 0x100) 1926da2bc464SMichael EllermanTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) 1927ff1b3206SNicholas PigginEXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) 1928da2bc464SMichael Ellerman#else /* CONFIG_CBE_RAS */ 19291a6822d1SNicholas PigginEXC_REAL_NONE(0x1200, 0x100) 19301a6822d1SNicholas PigginEXC_VIRT_NONE(0x5200, 0x100) 1931da2bc464SMichael Ellerman#endif 1932da2bc464SMichael Ellerman 1933ff1b3206SNicholas Piggin 19341a6822d1SNicholas PigginEXC_REAL(instruction_breakpoint, 0x1300, 0x100) 19351a6822d1SNicholas PigginEXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) 1936da2bc464SMichael EllermanTRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) 19374e96dbbfSNicholas PigginEXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) 19384e96dbbfSNicholas Piggin 19391a6822d1SNicholas PigginEXC_REAL_NONE(0x1400, 0x100) 19401a6822d1SNicholas PigginEXC_VIRT_NONE(0x5400, 0x100) 1941da2bc464SMichael Ellerman 19421a6822d1SNicholas PigginEXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) 1943b92a66a6SMichael Neuling mtspr SPRN_SPRG_HSCRATCH0,r13 19445dba1d50SNicholas Piggin EXCEPTION_PROLOG_0 PACA_EXGEN 1945fa4cf6b7SNicholas Piggin EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0 1946b92a66a6SMichael Neuling 1947b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 1948b92a66a6SMichael Neuling mfspr r10,SPRN_HSRR1 1949b92a66a6SMichael Neuling andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ 1950b92a66a6SMichael Neuling bne+ denorm_assist 1951b92a66a6SMichael Neuling#endif 1952b92a66a6SMichael Neuling 1953a7c1ca19SNicholas Piggin KVMTEST EXC_HV 0x1500 19542d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1 19551a6822d1SNicholas PigginEXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) 1956da2bc464SMichael Ellerman 1957d7e89849SNicholas Piggin#ifdef CONFIG_PPC_DENORMALISATION 19581a6822d1SNicholas PigginEXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) 1959d7e89849SNicholas Piggin b exc_real_0x1500_denorm_exception_hv 19601a6822d1SNicholas PigginEXC_VIRT_END(denorm_exception, 0x5500, 0x100) 1961d7e89849SNicholas Piggin#else 19621a6822d1SNicholas PigginEXC_VIRT_NONE(0x5500, 0x100) 1963d7e89849SNicholas Piggin#endif 1964d7e89849SNicholas Piggin 19654bb3c7a0SPaul MackerrasTRAMP_KVM_HV(PACA_EXGEN, 0x1500) 1966b92a66a6SMichael Neuling 1967b92a66a6SMichael Neuling#ifdef CONFIG_PPC_DENORMALISATION 1968da2bc464SMichael EllermanTRAMP_REAL_BEGIN(denorm_assist) 1969b92a66a6SMichael NeulingBEGIN_FTR_SECTION 1970b92a66a6SMichael Neuling/* 1971b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 1972b92a66a6SMichael Neuling * For POWER6 do that here for all FP regs. 1973b92a66a6SMichael Neuling */ 1974b92a66a6SMichael Neuling mfmsr r10 1975b92a66a6SMichael Neuling ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) 1976b92a66a6SMichael Neuling xori r10,r10,(MSR_FE0|MSR_FE1) 1977b92a66a6SMichael Neuling mtmsrd r10 1978b92a66a6SMichael Neuling sync 1979d7c67fb1SMichael Neuling 1980f3c8b6c6SNicholas Piggin .Lreg=0 1981f3c8b6c6SNicholas Piggin .rept 32 1982f3c8b6c6SNicholas Piggin fmr .Lreg,.Lreg 1983f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 1984f3c8b6c6SNicholas Piggin .endr 1985d7c67fb1SMichael Neuling 1986b92a66a6SMichael NeulingFTR_SECTION_ELSE 1987b92a66a6SMichael Neuling/* 1988b92a66a6SMichael Neuling * To denormalise we need to move a copy of the register to itself. 1989b92a66a6SMichael Neuling * For POWER7 do that here for the first 32 VSX registers only. 1990b92a66a6SMichael Neuling */ 1991b92a66a6SMichael Neuling mfmsr r10 1992b92a66a6SMichael Neuling oris r10,r10,MSR_VSX@h 1993b92a66a6SMichael Neuling mtmsrd r10 1994b92a66a6SMichael Neuling sync 1995d7c67fb1SMichael Neuling 1996f3c8b6c6SNicholas Piggin .Lreg=0 1997f3c8b6c6SNicholas Piggin .rept 32 1998f3c8b6c6SNicholas Piggin XVCPSGNDP(.Lreg,.Lreg,.Lreg) 1999f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 2000f3c8b6c6SNicholas Piggin .endr 2001d7c67fb1SMichael Neuling 2002b92a66a6SMichael NeulingALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 2003fb0fce3eSMichael Neuling 2004fb0fce3eSMichael NeulingBEGIN_FTR_SECTION 2005fb0fce3eSMichael Neuling b denorm_done 2006fb0fce3eSMichael NeulingEND_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 2007fb0fce3eSMichael Neuling/* 2008fb0fce3eSMichael Neuling * To denormalise we need to move a copy of the register to itself. 2009fb0fce3eSMichael Neuling * For POWER8 we need to do that for all 64 VSX registers 2010fb0fce3eSMichael Neuling */ 2011f3c8b6c6SNicholas Piggin .Lreg=32 2012f3c8b6c6SNicholas Piggin .rept 32 2013f3c8b6c6SNicholas Piggin XVCPSGNDP(.Lreg,.Lreg,.Lreg) 2014f3c8b6c6SNicholas Piggin .Lreg=.Lreg+1 2015f3c8b6c6SNicholas Piggin .endr 2016f3c8b6c6SNicholas Piggin 2017fb0fce3eSMichael Neulingdenorm_done: 2018f14040bcSMichael Neuling mfspr r11,SPRN_HSRR0 2019f14040bcSMichael Neuling subi r11,r11,4 2020b92a66a6SMichael Neuling mtspr SPRN_HSRR0,r11 2021b92a66a6SMichael Neuling mtcrf 0x80,r9 2022b92a66a6SMichael Neuling ld r9,PACA_EXGEN+EX_R9(r13) 202344e9309fSHaren Myneni RESTORE_PPR_PACA(PACA_EXGEN, r10) 2024630573c1SPaul MackerrasBEGIN_FTR_SECTION 2025630573c1SPaul Mackerras ld r10,PACA_EXGEN+EX_CFAR(r13) 2026630573c1SPaul Mackerras mtspr SPRN_CFAR,r10 2027630573c1SPaul MackerrasEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 2028b92a66a6SMichael Neuling ld r10,PACA_EXGEN+EX_R10(r13) 2029b92a66a6SMichael Neuling ld r11,PACA_EXGEN+EX_R11(r13) 2030b92a66a6SMichael Neuling ld r12,PACA_EXGEN+EX_R12(r13) 2031b92a66a6SMichael Neuling ld r13,PACA_EXGEN+EX_R13(r13) 2032222f20f1SNicholas Piggin HRFI_TO_UNKNOWN 2033b92a66a6SMichael Neuling b . 2034b92a66a6SMichael Neuling#endif 2035b92a66a6SMichael Neuling 2036872e2ae4SBenjamin HerrenschmidtEXC_COMMON(denorm_common, 0x1500, unknown_exception) 2037d7e89849SNicholas Piggin 2038d7e89849SNicholas Piggin 2039d7e89849SNicholas Piggin#ifdef CONFIG_CBE_RAS 20401a6822d1SNicholas PigginEXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) 20411a6822d1SNicholas PigginEXC_VIRT_NONE(0x5600, 0x100) 2042d7e89849SNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) 204369a79344SNicholas PigginEXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) 2044d7e89849SNicholas Piggin#else /* CONFIG_CBE_RAS */ 20451a6822d1SNicholas PigginEXC_REAL_NONE(0x1600, 0x100) 20461a6822d1SNicholas PigginEXC_VIRT_NONE(0x5600, 0x100) 2047d7e89849SNicholas Piggin#endif 2048d7e89849SNicholas Piggin 204969a79344SNicholas Piggin 20501a6822d1SNicholas PigginEXC_REAL(altivec_assist, 0x1700, 0x100) 20511a6822d1SNicholas PigginEXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) 2052d7e89849SNicholas PigginTRAMP_KVM(PACA_EXGEN, 0x1700) 2053b51c079eSNicholas Piggin#ifdef CONFIG_ALTIVEC 2054b51c079eSNicholas PigginEXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) 2055b51c079eSNicholas Piggin#else 2056b51c079eSNicholas PigginEXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) 2057b51c079eSNicholas Piggin#endif 2058b51c079eSNicholas Piggin 2059d7e89849SNicholas Piggin 2060d7e89849SNicholas Piggin#ifdef CONFIG_CBE_RAS 20611a6822d1SNicholas PigginEXC_REAL_HV(cbe_thermal, 0x1800, 0x100) 20621a6822d1SNicholas PigginEXC_VIRT_NONE(0x5800, 0x100) 2063d7e89849SNicholas PigginTRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) 20643965f8abSNicholas PigginEXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) 2065d7e89849SNicholas Piggin#else /* CONFIG_CBE_RAS */ 20661a6822d1SNicholas PigginEXC_REAL_NONE(0x1800, 0x100) 20671a6822d1SNicholas PigginEXC_VIRT_NONE(0x5800, 0x100) 2068d7e89849SNicholas Piggin#endif 2069d7e89849SNicholas Piggin 207075eb767eSNicholas Piggin#ifdef CONFIG_PPC_WATCHDOG 20712104180aSNicholas Piggin 20722104180aSNicholas Piggin#define MASKED_DEC_HANDLER_LABEL 3f 20732104180aSNicholas Piggin 20742104180aSNicholas Piggin#define MASKED_DEC_HANDLER(_H) \ 20752104180aSNicholas Piggin3: /* soft-nmi */ \ 20762104180aSNicholas Piggin std r12,PACA_EXGEN+EX_R12(r13); \ 20772104180aSNicholas Piggin GET_SCRATCH0(r10); \ 20782104180aSNicholas Piggin std r10,PACA_EXGEN+EX_R13(r13); \ 20792d046308SNicholas Piggin EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1 20802104180aSNicholas Piggin 2081cc491f1dSNicholas Piggin/* 2082cc491f1dSNicholas Piggin * Branch to soft_nmi_interrupt using the emergency stack. The emergency 2083cc491f1dSNicholas Piggin * stack is one that is usable by maskable interrupts so long as MSR_EE 2084cc491f1dSNicholas Piggin * remains off. It is used for recovery when something has corrupted the 2085cc491f1dSNicholas Piggin * normal kernel stack, for example. The "soft NMI" must not use the process 2086cc491f1dSNicholas Piggin * stack because we want irq disabled sections to avoid touching the stack 2087cc491f1dSNicholas Piggin * at all (other than PMU interrupts), so use the emergency stack for this, 2088cc491f1dSNicholas Piggin * and run it entirely with interrupts hard disabled. 2089cc491f1dSNicholas Piggin */ 20902104180aSNicholas PigginEXC_COMMON_BEGIN(soft_nmi_common) 20912104180aSNicholas Piggin mr r10,r1 20922104180aSNicholas Piggin ld r1,PACAEMERGSP(r13) 20932104180aSNicholas Piggin subi r1,r1,INT_FRAME_SIZE 209447169fbaSNicholas Piggin EXCEPTION_COMMON_STACK(PACA_EXGEN, 0x900) 209547169fbaSNicholas Piggin bl save_nvgprs 209647169fbaSNicholas Piggin RECONCILE_IRQ_STATE(r10, r11) 2097c06075f3SNicholas Piggin addi r3,r1,STACK_FRAME_OVERHEAD 2098c06075f3SNicholas Piggin bl soft_nmi_interrupt 20992104180aSNicholas Piggin b ret_from_except 21002104180aSNicholas Piggin 210175eb767eSNicholas Piggin#else /* CONFIG_PPC_WATCHDOG */ 21022104180aSNicholas Piggin#define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ 21032104180aSNicholas Piggin#define MASKED_DEC_HANDLER(_H) 210475eb767eSNicholas Piggin#endif /* CONFIG_PPC_WATCHDOG */ 2105d7e89849SNicholas Piggin 21060ebc4cdaSBenjamin Herrenschmidt/* 2107fe9e1d54SIan Munsie * An interrupt came in while soft-disabled. We set paca->irq_happened, then: 2108fe9e1d54SIan Munsie * - If it was a decrementer interrupt, we bump the dec to max and and return. 2109fe9e1d54SIan Munsie * - If it was a doorbell we return immediately since doorbells are edge 2110fe9e1d54SIan Munsie * triggered and won't automatically refire. 21110869b6fdSMahesh Salgaonkar * - If it was a HMI we return immediately since we handled it in realmode 21120869b6fdSMahesh Salgaonkar * and it won't refire. 21136cc3f91bSNicholas Piggin * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return. 2114fe9e1d54SIan Munsie * This is called with r10 containing the value to OR to the paca field. 21150ebc4cdaSBenjamin Herrenschmidt */ 21164508a74aSNicholas Piggin.macro MASKED_INTERRUPT hsrr 21174508a74aSNicholas Piggin .if \hsrr 21184508a74aSNicholas Pigginmasked_Hinterrupt: 21194508a74aSNicholas Piggin .else 21204508a74aSNicholas Pigginmasked_interrupt: 21214508a74aSNicholas Piggin .endif 21224508a74aSNicholas Piggin std r11,PACA_EXGEN+EX_R11(r13) 21234508a74aSNicholas Piggin lbz r11,PACAIRQHAPPENED(r13) 21244508a74aSNicholas Piggin or r11,r11,r10 21254508a74aSNicholas Piggin stb r11,PACAIRQHAPPENED(r13) 21264508a74aSNicholas Piggin cmpwi r10,PACA_IRQ_DEC 21274508a74aSNicholas Piggin bne 1f 21284508a74aSNicholas Piggin lis r10,0x7fff 21294508a74aSNicholas Piggin ori r10,r10,0xffff 21304508a74aSNicholas Piggin mtspr SPRN_DEC,r10 21314508a74aSNicholas Piggin b MASKED_DEC_HANDLER_LABEL 21324508a74aSNicholas Piggin1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK 21334508a74aSNicholas Piggin beq 2f 21344508a74aSNicholas Piggin .if \hsrr 21354508a74aSNicholas Piggin mfspr r10,SPRN_HSRR1 21364508a74aSNicholas Piggin xori r10,r10,MSR_EE /* clear MSR_EE */ 21374508a74aSNicholas Piggin mtspr SPRN_HSRR1,r10 21384508a74aSNicholas Piggin .else 21394508a74aSNicholas Piggin mfspr r10,SPRN_SRR1 21404508a74aSNicholas Piggin xori r10,r10,MSR_EE /* clear MSR_EE */ 21414508a74aSNicholas Piggin mtspr SPRN_SRR1,r10 21424508a74aSNicholas Piggin .endif 21434508a74aSNicholas Piggin ori r11,r11,PACA_IRQ_HARD_DIS 21444508a74aSNicholas Piggin stb r11,PACAIRQHAPPENED(r13) 21454508a74aSNicholas Piggin2: /* done */ 21464508a74aSNicholas Piggin mtcrf 0x80,r9 21474508a74aSNicholas Piggin std r1,PACAR1(r13) 21484508a74aSNicholas Piggin ld r9,PACA_EXGEN+EX_R9(r13) 21494508a74aSNicholas Piggin ld r10,PACA_EXGEN+EX_R10(r13) 21504508a74aSNicholas Piggin ld r11,PACA_EXGEN+EX_R11(r13) 21514508a74aSNicholas Piggin /* returns to kernel where r13 must be set up, so don't restore it */ 21524508a74aSNicholas Piggin .if \hsrr 21534508a74aSNicholas Piggin HRFI_TO_KERNEL 21544508a74aSNicholas Piggin .else 21554508a74aSNicholas Piggin RFI_TO_KERNEL 21564508a74aSNicholas Piggin .endif 21574508a74aSNicholas Piggin b . 21584508a74aSNicholas Piggin MASKED_DEC_HANDLER(\hsrr\()) 21594508a74aSNicholas Piggin.endm 21600ebc4cdaSBenjamin Herrenschmidt 2161a048a07dSNicholas PigginTRAMP_REAL_BEGIN(stf_barrier_fallback) 2162a048a07dSNicholas Piggin std r9,PACA_EXRFI+EX_R9(r13) 2163a048a07dSNicholas Piggin std r10,PACA_EXRFI+EX_R10(r13) 2164a048a07dSNicholas Piggin sync 2165a048a07dSNicholas Piggin ld r9,PACA_EXRFI+EX_R9(r13) 2166a048a07dSNicholas Piggin ld r10,PACA_EXRFI+EX_R10(r13) 2167a048a07dSNicholas Piggin ori 31,31,0 2168a048a07dSNicholas Piggin .rept 14 2169a048a07dSNicholas Piggin b 1f 2170a048a07dSNicholas Piggin1: 2171a048a07dSNicholas Piggin .endr 2172a048a07dSNicholas Piggin blr 2173a048a07dSNicholas Piggin 2174aa8a5e00SMichael EllermanTRAMP_REAL_BEGIN(rfi_flush_fallback) 2175aa8a5e00SMichael Ellerman SET_SCRATCH0(r13); 2176aa8a5e00SMichael Ellerman GET_PACA(r13); 217778ee9946SMichael Ellerman std r1,PACA_EXRFI+EX_R12(r13) 217878ee9946SMichael Ellerman ld r1,PACAKSAVE(r13) 2179aa8a5e00SMichael Ellerman std r9,PACA_EXRFI+EX_R9(r13) 2180aa8a5e00SMichael Ellerman std r10,PACA_EXRFI+EX_R10(r13) 2181aa8a5e00SMichael Ellerman std r11,PACA_EXRFI+EX_R11(r13) 2182aa8a5e00SMichael Ellerman mfctr r9 2183aa8a5e00SMichael Ellerman ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2184bdcb1aefSNicholas Piggin ld r11,PACA_L1D_FLUSH_SIZE(r13) 2185bdcb1aefSNicholas Piggin srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2186aa8a5e00SMichael Ellerman mtctr r11 218715a3204dSNicholas Piggin DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2188aa8a5e00SMichael Ellerman 2189aa8a5e00SMichael Ellerman /* order ld/st prior to dcbt stop all streams with flushing */ 2190aa8a5e00SMichael Ellerman sync 2191bdcb1aefSNicholas Piggin 2192bdcb1aefSNicholas Piggin /* 2193bdcb1aefSNicholas Piggin * The load adresses are at staggered offsets within cachelines, 2194bdcb1aefSNicholas Piggin * which suits some pipelines better (on others it should not 2195bdcb1aefSNicholas Piggin * hurt). 2196bdcb1aefSNicholas Piggin */ 2197bdcb1aefSNicholas Piggin1: 2198bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*0(r10) 2199bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*1(r10) 2200bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*2(r10) 2201bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*3(r10) 2202bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*4(r10) 2203bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*5(r10) 2204bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*6(r10) 2205bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*7(r10) 2206bdcb1aefSNicholas Piggin addi r10,r10,0x80*8 2207aa8a5e00SMichael Ellerman bdnz 1b 2208aa8a5e00SMichael Ellerman 2209aa8a5e00SMichael Ellerman mtctr r9 2210aa8a5e00SMichael Ellerman ld r9,PACA_EXRFI+EX_R9(r13) 2211aa8a5e00SMichael Ellerman ld r10,PACA_EXRFI+EX_R10(r13) 2212aa8a5e00SMichael Ellerman ld r11,PACA_EXRFI+EX_R11(r13) 221378ee9946SMichael Ellerman ld r1,PACA_EXRFI+EX_R12(r13) 2214aa8a5e00SMichael Ellerman GET_SCRATCH0(r13); 2215aa8a5e00SMichael Ellerman rfid 2216aa8a5e00SMichael Ellerman 2217aa8a5e00SMichael EllermanTRAMP_REAL_BEGIN(hrfi_flush_fallback) 2218aa8a5e00SMichael Ellerman SET_SCRATCH0(r13); 2219aa8a5e00SMichael Ellerman GET_PACA(r13); 222078ee9946SMichael Ellerman std r1,PACA_EXRFI+EX_R12(r13) 222178ee9946SMichael Ellerman ld r1,PACAKSAVE(r13) 2222aa8a5e00SMichael Ellerman std r9,PACA_EXRFI+EX_R9(r13) 2223aa8a5e00SMichael Ellerman std r10,PACA_EXRFI+EX_R10(r13) 2224aa8a5e00SMichael Ellerman std r11,PACA_EXRFI+EX_R11(r13) 2225aa8a5e00SMichael Ellerman mfctr r9 2226aa8a5e00SMichael Ellerman ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) 2227bdcb1aefSNicholas Piggin ld r11,PACA_L1D_FLUSH_SIZE(r13) 2228bdcb1aefSNicholas Piggin srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */ 2229aa8a5e00SMichael Ellerman mtctr r11 223015a3204dSNicholas Piggin DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ 2231aa8a5e00SMichael Ellerman 2232aa8a5e00SMichael Ellerman /* order ld/st prior to dcbt stop all streams with flushing */ 2233aa8a5e00SMichael Ellerman sync 2234bdcb1aefSNicholas Piggin 2235bdcb1aefSNicholas Piggin /* 2236bdcb1aefSNicholas Piggin * The load adresses are at staggered offsets within cachelines, 2237bdcb1aefSNicholas Piggin * which suits some pipelines better (on others it should not 2238bdcb1aefSNicholas Piggin * hurt). 2239bdcb1aefSNicholas Piggin */ 2240bdcb1aefSNicholas Piggin1: 2241bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*0(r10) 2242bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*1(r10) 2243bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*2(r10) 2244bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*3(r10) 2245bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*4(r10) 2246bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*5(r10) 2247bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*6(r10) 2248bdcb1aefSNicholas Piggin ld r11,(0x80 + 8)*7(r10) 2249bdcb1aefSNicholas Piggin addi r10,r10,0x80*8 2250aa8a5e00SMichael Ellerman bdnz 1b 2251aa8a5e00SMichael Ellerman 2252aa8a5e00SMichael Ellerman mtctr r9 2253aa8a5e00SMichael Ellerman ld r9,PACA_EXRFI+EX_R9(r13) 2254aa8a5e00SMichael Ellerman ld r10,PACA_EXRFI+EX_R10(r13) 2255aa8a5e00SMichael Ellerman ld r11,PACA_EXRFI+EX_R11(r13) 225678ee9946SMichael Ellerman ld r1,PACA_EXRFI+EX_R12(r13) 2257aa8a5e00SMichael Ellerman GET_SCRATCH0(r13); 2258aa8a5e00SMichael Ellerman hrfid 2259aa8a5e00SMichael Ellerman 226057f26649SNicholas Piggin/* 226157f26649SNicholas Piggin * Real mode exceptions actually use this too, but alternate 226257f26649SNicholas Piggin * instruction code patches (which end up in the common .text area) 226357f26649SNicholas Piggin * cannot reach these if they are put there. 226457f26649SNicholas Piggin */ 226557f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 22664508a74aSNicholas Piggin MASKED_INTERRUPT EXC_STD 22674508a74aSNicholas Piggin MASKED_INTERRUPT EXC_HV 22687230c564SBenjamin Herrenschmidt 22694f6c11dbSPaul Mackerras#ifdef CONFIG_KVM_BOOK3S_64_HANDLER 2270da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_interrupt) 22714f6c11dbSPaul Mackerras /* 22724f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 22734f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 22744f6c11dbSPaul Mackerras */ 22754f6c11dbSPaul Mackerras mfspr r13, SPRN_SRR0 22764f6c11dbSPaul Mackerras addi r13, r13, 4 22774f6c11dbSPaul Mackerras mtspr SPRN_SRR0, r13 22784f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 2279222f20f1SNicholas Piggin RFI_TO_KERNEL 22804f6c11dbSPaul Mackerras b . 22814f6c11dbSPaul Mackerras 2282da2bc464SMichael EllermanTRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) 22834f6c11dbSPaul Mackerras /* 22844f6c11dbSPaul Mackerras * Here all GPRs are unchanged from when the interrupt happened 22854f6c11dbSPaul Mackerras * except for r13, which is saved in SPRG_SCRATCH0. 22864f6c11dbSPaul Mackerras */ 22874f6c11dbSPaul Mackerras mfspr r13, SPRN_HSRR0 22884f6c11dbSPaul Mackerras addi r13, r13, 4 22894f6c11dbSPaul Mackerras mtspr SPRN_HSRR0, r13 22904f6c11dbSPaul Mackerras GET_SCRATCH0(r13) 2291222f20f1SNicholas Piggin HRFI_TO_KERNEL 22924f6c11dbSPaul Mackerras b . 22934f6c11dbSPaul Mackerras#endif 22944f6c11dbSPaul Mackerras 22950ebc4cdaSBenjamin Herrenschmidt/* 2296057b6d7eSHari Bathini * Ensure that any handlers that get invoked from the exception prologs 2297057b6d7eSHari Bathini * above are below the first 64KB (0x10000) of the kernel image because 2298057b6d7eSHari Bathini * the prologs assemble the addresses of these handlers using the 2299057b6d7eSHari Bathini * LOAD_HANDLER macro, which uses an ori instruction. 23000ebc4cdaSBenjamin Herrenschmidt */ 23010ebc4cdaSBenjamin Herrenschmidt 23020ebc4cdaSBenjamin Herrenschmidt/*** Common interrupt handlers ***/ 23030ebc4cdaSBenjamin Herrenschmidt 23040ebc4cdaSBenjamin Herrenschmidt 2305c1fb6816SMichael Neuling /* 2306c1fb6816SMichael Neuling * Relocation-on interrupts: A subset of the interrupts can be delivered 2307c1fb6816SMichael Neuling * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering 2308c1fb6816SMichael Neuling * it. Addresses are the same as the original interrupt addresses, but 2309c1fb6816SMichael Neuling * offset by 0xc000000000004000. 2310c1fb6816SMichael Neuling * It's impossible to receive interrupts below 0x300 via this mechanism. 2311c1fb6816SMichael Neuling * KVM: None of these traps are from the guest ; anything that escalated 2312c1fb6816SMichael Neuling * to HV=1 from HV=0 is delivered via real mode handlers. 2313c1fb6816SMichael Neuling */ 2314c1fb6816SMichael Neuling 2315c1fb6816SMichael Neuling /* 2316c1fb6816SMichael Neuling * This uses the standard macro, since the original 0x300 vector 2317c1fb6816SMichael Neuling * only has extra guff for STAB-based processors -- which never 2318c1fb6816SMichael Neuling * come here. 2319c1fb6816SMichael Neuling */ 2320da2bc464SMichael Ellerman 232157f26649SNicholas PigginEXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) 2322b1576fecSAnton Blanchard b __ppc64_runlatch_on 2323fe1952fcSBenjamin Herrenschmidt 232457f26649SNicholas PigginUSE_FIXED_SECTION(virt_trampolines) 23258ed8ab40SHari Bathini /* 23268ed8ab40SHari Bathini * The __end_interrupts marker must be past the out-of-line (OOL) 23278ed8ab40SHari Bathini * handlers, so that they are copied to real address 0x100 when running 23288ed8ab40SHari Bathini * a relocatable kernel. This ensures they can be reached from the short 23298ed8ab40SHari Bathini * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch 23308ed8ab40SHari Bathini * directly, without using LOAD_HANDLER(). 23318ed8ab40SHari Bathini */ 23328ed8ab40SHari Bathini .align 7 23338ed8ab40SHari Bathini .globl __end_interrupts 23348ed8ab40SHari Bathini__end_interrupts: 233557f26649SNicholas PigginDEFINE_FIXED_SYMBOL(__end_interrupts) 233661383407SBenjamin Herrenschmidt 2337087aa036SChen Gang#ifdef CONFIG_PPC_970_NAP 23387c8cb4b5SNicholas PigginEXC_COMMON_BEGIN(power4_fixup_nap) 2339087aa036SChen Gang andc r9,r9,r10 2340087aa036SChen Gang std r9,TI_LOCAL_FLAGS(r11) 2341087aa036SChen Gang ld r10,_LINK(r1) /* make idle task do the */ 2342087aa036SChen Gang std r10,_NIP(r1) /* equivalent of a blr */ 2343087aa036SChen Gang blr 2344087aa036SChen Gang#endif 2345087aa036SChen Gang 234657f26649SNicholas PigginCLOSE_FIXED_SECTION(real_vectors); 234757f26649SNicholas PigginCLOSE_FIXED_SECTION(real_trampolines); 234857f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_vectors); 234957f26649SNicholas PigginCLOSE_FIXED_SECTION(virt_trampolines); 235057f26649SNicholas Piggin 235157f26649SNicholas PigginUSE_TEXT_SECTION() 235257f26649SNicholas Piggin 2353087aa036SChen Gang/* 23540ebc4cdaSBenjamin Herrenschmidt * Hash table stuff 23550ebc4cdaSBenjamin Herrenschmidt */ 2356f4329f2eSNicholas Piggin .balign IFETCH_ALIGN_BYTES 23576a3bab90SAnton Blancharddo_hash_page: 23584e003747SMichael Ellerman#ifdef CONFIG_PPC_BOOK3S_64 2359e6c2a479SRam Pai lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h 2360398a719dSBenjamin Herrenschmidt ori r0,r0,DSISR_BAD_FAULT_64S@l 2361398a719dSBenjamin Herrenschmidt and. r0,r4,r0 /* weird error? */ 23620ebc4cdaSBenjamin Herrenschmidt bne- handle_page_fault /* if not, try to insert a HPTE */ 2363c911d2e1SChristophe Leroy ld r11, PACA_THREAD_INFO(r13) 23649c1e1052SPaul Mackerras lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ 23659c1e1052SPaul Mackerras andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ 23669c1e1052SPaul Mackerras bne 77f /* then don't call hash_page now */ 23670ebc4cdaSBenjamin Herrenschmidt 23680ebc4cdaSBenjamin Herrenschmidt /* 23690ebc4cdaSBenjamin Herrenschmidt * r3 contains the faulting address 2370106713a1SAneesh Kumar K.V * r4 msr 23710ebc4cdaSBenjamin Herrenschmidt * r5 contains the trap number 2372aefa5688SAneesh Kumar K.V * r6 contains dsisr 23730ebc4cdaSBenjamin Herrenschmidt * 23747230c564SBenjamin Herrenschmidt * at return r3 = 0 for success, 1 for page fault, negative for error 23750ebc4cdaSBenjamin Herrenschmidt */ 2376106713a1SAneesh Kumar K.V mr r4,r12 2377aefa5688SAneesh Kumar K.V ld r6,_DSISR(r1) 2378106713a1SAneesh Kumar K.V bl __hash_page /* build HPTE if possible */ 2379106713a1SAneesh Kumar K.V cmpdi r3,0 /* see if __hash_page succeeded */ 23800ebc4cdaSBenjamin Herrenschmidt 23817230c564SBenjamin Herrenschmidt /* Success */ 23820ebc4cdaSBenjamin Herrenschmidt beq fast_exc_return_irq /* Return from exception on success */ 23830ebc4cdaSBenjamin Herrenschmidt 23847230c564SBenjamin Herrenschmidt /* Error */ 23857230c564SBenjamin Herrenschmidt blt- 13f 2386d89ba535SNaveen N. Rao 2387d89ba535SNaveen N. Rao /* Reload DSISR into r4 for the DABR check below */ 2388d89ba535SNaveen N. Rao ld r4,_DSISR(r1) 23894e003747SMichael Ellerman#endif /* CONFIG_PPC_BOOK3S_64 */ 23900ebc4cdaSBenjamin Herrenschmidt 2391a546498fSBenjamin Herrenschmidt/* Here we have a page fault that hash_page can't handle. */ 2392a546498fSBenjamin Herrenschmidthandle_page_fault: 2393d89ba535SNaveen N. Rao11: andis. r0,r4,DSISR_DABRMATCH@h 2394d89ba535SNaveen N. Rao bne- handle_dabr_fault 2395d89ba535SNaveen N. Rao ld r4,_DAR(r1) 2396a546498fSBenjamin Herrenschmidt ld r5,_DSISR(r1) 2397a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 2398b1576fecSAnton Blanchard bl do_page_fault 2399a546498fSBenjamin Herrenschmidt cmpdi r3,0 2400f474c28fSRavi Bangoria beq+ ret_from_except_lite 2401b1576fecSAnton Blanchard bl save_nvgprs 2402a546498fSBenjamin Herrenschmidt mr r5,r3 2403a546498fSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 2404a546498fSBenjamin Herrenschmidt lwz r4,_DAR(r1) 2405b1576fecSAnton Blanchard bl bad_page_fault 2406b1576fecSAnton Blanchard b ret_from_except 24070ebc4cdaSBenjamin Herrenschmidt 24089c7cc234SK.Prasad/* We have a data breakpoint exception - handle it */ 24099c7cc234SK.Prasadhandle_dabr_fault: 2410b1576fecSAnton Blanchard bl save_nvgprs 24119c7cc234SK.Prasad ld r4,_DAR(r1) 24129c7cc234SK.Prasad ld r5,_DSISR(r1) 24139c7cc234SK.Prasad addi r3,r1,STACK_FRAME_OVERHEAD 2414b1576fecSAnton Blanchard bl do_break 2415f474c28fSRavi Bangoria /* 2416f474c28fSRavi Bangoria * do_break() may have changed the NV GPRS while handling a breakpoint. 2417f474c28fSRavi Bangoria * If so, we need to restore them with their updated values. Don't use 2418f474c28fSRavi Bangoria * ret_from_except_lite here. 2419f474c28fSRavi Bangoria */ 2420f474c28fSRavi Bangoria b ret_from_except 24219c7cc234SK.Prasad 24220ebc4cdaSBenjamin Herrenschmidt 24234e003747SMichael Ellerman#ifdef CONFIG_PPC_BOOK3S_64 24240ebc4cdaSBenjamin Herrenschmidt/* We have a page fault that hash_page could handle but HV refused 24250ebc4cdaSBenjamin Herrenschmidt * the PTE insertion 24260ebc4cdaSBenjamin Herrenschmidt */ 2427b1576fecSAnton Blanchard13: bl save_nvgprs 24280ebc4cdaSBenjamin Herrenschmidt mr r5,r3 24290ebc4cdaSBenjamin Herrenschmidt addi r3,r1,STACK_FRAME_OVERHEAD 24300ebc4cdaSBenjamin Herrenschmidt ld r4,_DAR(r1) 2431b1576fecSAnton Blanchard bl low_hash_fault 2432b1576fecSAnton Blanchard b ret_from_except 2433caca285eSAneesh Kumar K.V#endif 24340ebc4cdaSBenjamin Herrenschmidt 24359c1e1052SPaul Mackerras/* 24369c1e1052SPaul Mackerras * We come here as a result of a DSI at a point where we don't want 24379c1e1052SPaul Mackerras * to call hash_page, such as when we are accessing memory (possibly 24389c1e1052SPaul Mackerras * user memory) inside a PMU interrupt that occurred while interrupts 24399c1e1052SPaul Mackerras * were soft-disabled. We want to invoke the exception handler for 24409c1e1052SPaul Mackerras * the access, or panic if there isn't a handler. 24419c1e1052SPaul Mackerras */ 2442b1576fecSAnton Blanchard77: bl save_nvgprs 24439c1e1052SPaul Mackerras mr r4,r3 24449c1e1052SPaul Mackerras addi r3,r1,STACK_FRAME_OVERHEAD 24459c1e1052SPaul Mackerras li r5,SIGSEGV 2446b1576fecSAnton Blanchard bl bad_page_fault 2447b1576fecSAnton Blanchard b ret_from_except 24484e2bf01bSMichael Ellerman 24494e2bf01bSMichael Ellerman/* 24504e2bf01bSMichael Ellerman * Here we have detected that the kernel stack pointer is bad. 24514e2bf01bSMichael Ellerman * R9 contains the saved CR, r13 points to the paca, 24524e2bf01bSMichael Ellerman * r10 contains the (bad) kernel stack pointer, 24534e2bf01bSMichael Ellerman * r11 and r12 contain the saved SRR0 and SRR1. 24544e2bf01bSMichael Ellerman * We switch to using an emergency stack, save the registers there, 24554e2bf01bSMichael Ellerman * and call kernel_bad_stack(), which panics. 24564e2bf01bSMichael Ellerman */ 24574e2bf01bSMichael Ellermanbad_stack: 24584e2bf01bSMichael Ellerman ld r1,PACAEMERGSP(r13) 24594e2bf01bSMichael Ellerman subi r1,r1,64+INT_FRAME_SIZE 24604e2bf01bSMichael Ellerman std r9,_CCR(r1) 24614e2bf01bSMichael Ellerman std r10,GPR1(r1) 24624e2bf01bSMichael Ellerman std r11,_NIP(r1) 24634e2bf01bSMichael Ellerman std r12,_MSR(r1) 24644e2bf01bSMichael Ellerman mfspr r11,SPRN_DAR 24654e2bf01bSMichael Ellerman mfspr r12,SPRN_DSISR 24664e2bf01bSMichael Ellerman std r11,_DAR(r1) 24674e2bf01bSMichael Ellerman std r12,_DSISR(r1) 24684e2bf01bSMichael Ellerman mflr r10 24694e2bf01bSMichael Ellerman mfctr r11 24704e2bf01bSMichael Ellerman mfxer r12 24714e2bf01bSMichael Ellerman std r10,_LINK(r1) 24724e2bf01bSMichael Ellerman std r11,_CTR(r1) 24734e2bf01bSMichael Ellerman std r12,_XER(r1) 24744e2bf01bSMichael Ellerman SAVE_GPR(0,r1) 24754e2bf01bSMichael Ellerman SAVE_GPR(2,r1) 24764e2bf01bSMichael Ellerman ld r10,EX_R3(r3) 24774e2bf01bSMichael Ellerman std r10,GPR3(r1) 24784e2bf01bSMichael Ellerman SAVE_GPR(4,r1) 24794e2bf01bSMichael Ellerman SAVE_4GPRS(5,r1) 24804e2bf01bSMichael Ellerman ld r9,EX_R9(r3) 24814e2bf01bSMichael Ellerman ld r10,EX_R10(r3) 24824e2bf01bSMichael Ellerman SAVE_2GPRS(9,r1) 24834e2bf01bSMichael Ellerman ld r9,EX_R11(r3) 24844e2bf01bSMichael Ellerman ld r10,EX_R12(r3) 24854e2bf01bSMichael Ellerman ld r11,EX_R13(r3) 24864e2bf01bSMichael Ellerman std r9,GPR11(r1) 24874e2bf01bSMichael Ellerman std r10,GPR12(r1) 24884e2bf01bSMichael Ellerman std r11,GPR13(r1) 24894e2bf01bSMichael EllermanBEGIN_FTR_SECTION 24904e2bf01bSMichael Ellerman ld r10,EX_CFAR(r3) 24914e2bf01bSMichael Ellerman std r10,ORIG_GPR3(r1) 24924e2bf01bSMichael EllermanEND_FTR_SECTION_IFSET(CPU_FTR_CFAR) 24934e2bf01bSMichael Ellerman SAVE_8GPRS(14,r1) 24944e2bf01bSMichael Ellerman SAVE_10GPRS(22,r1) 24954e2bf01bSMichael Ellerman lhz r12,PACA_TRAP_SAVE(r13) 24964e2bf01bSMichael Ellerman std r12,_TRAP(r1) 24974e2bf01bSMichael Ellerman addi r11,r1,INT_FRAME_SIZE 24984e2bf01bSMichael Ellerman std r11,0(r1) 24994e2bf01bSMichael Ellerman li r12,0 25004e2bf01bSMichael Ellerman std r12,0(r11) 25014e2bf01bSMichael Ellerman ld r2,PACATOC(r13) 25024e2bf01bSMichael Ellerman ld r11,exception_marker@toc(r2) 25034e2bf01bSMichael Ellerman std r12,RESULT(r1) 25044e2bf01bSMichael Ellerman std r11,STACK_FRAME_OVERHEAD-16(r1) 25054e2bf01bSMichael Ellerman1: addi r3,r1,STACK_FRAME_OVERHEAD 25064e2bf01bSMichael Ellerman bl kernel_bad_stack 25074e2bf01bSMichael Ellerman b 1b 250815770a13SNaveen N. Rao_ASM_NOKPROBE_SYMBOL(bad_stack); 25090f0c6ca1SNicholas Piggin 25100f0c6ca1SNicholas Piggin/* 2511a9af97aaSNicholas Piggin * When doorbell is triggered from system reset wakeup, the message is 2512a9af97aaSNicholas Piggin * not cleared, so it would fire again when EE is enabled. 2513a9af97aaSNicholas Piggin * 2514a9af97aaSNicholas Piggin * When coming from local_irq_enable, there may be the same problem if 2515a9af97aaSNicholas Piggin * we were hard disabled. 2516a9af97aaSNicholas Piggin * 2517a9af97aaSNicholas Piggin * Execute msgclr to clear pending exceptions before handling it. 2518a9af97aaSNicholas Piggin */ 2519a9af97aaSNicholas Pigginh_doorbell_common_msgclr: 2520a9af97aaSNicholas Piggin LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 2521a9af97aaSNicholas Piggin PPC_MSGCLR(3) 2522a9af97aaSNicholas Piggin b h_doorbell_common 2523a9af97aaSNicholas Piggin 2524a9af97aaSNicholas Piggindoorbell_super_common_msgclr: 2525a9af97aaSNicholas Piggin LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) 2526a9af97aaSNicholas Piggin PPC_MSGCLRP(3) 2527a9af97aaSNicholas Piggin b doorbell_super_common 2528a9af97aaSNicholas Piggin 2529a9af97aaSNicholas Piggin/* 25300f0c6ca1SNicholas Piggin * Called from arch_local_irq_enable when an interrupt needs 25310f0c6ca1SNicholas Piggin * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate 25320f0c6ca1SNicholas Piggin * which kind of interrupt. MSR:EE is already off. We generate a 25330f0c6ca1SNicholas Piggin * stackframe like if a real interrupt had happened. 25340f0c6ca1SNicholas Piggin * 25350f0c6ca1SNicholas Piggin * Note: While MSR:EE is off, we need to make sure that _MSR 25360f0c6ca1SNicholas Piggin * in the generated frame has EE set to 1 or the exception 25370f0c6ca1SNicholas Piggin * handler will not properly re-enable them. 2538b48bbb82SNicholas Piggin * 2539b48bbb82SNicholas Piggin * Note that we don't specify LR as the NIP (return address) for 2540b48bbb82SNicholas Piggin * the interrupt because that would unbalance the return branch 2541b48bbb82SNicholas Piggin * predictor. 25420f0c6ca1SNicholas Piggin */ 25430f0c6ca1SNicholas Piggin_GLOBAL(__replay_interrupt) 25440f0c6ca1SNicholas Piggin /* We are going to jump to the exception common code which 25450f0c6ca1SNicholas Piggin * will retrieve various register values from the PACA which 25460f0c6ca1SNicholas Piggin * we don't give a damn about, so we don't bother storing them. 25470f0c6ca1SNicholas Piggin */ 25480f0c6ca1SNicholas Piggin mfmsr r12 25493e23a12bSMichael Ellerman LOAD_REG_ADDR(r11, replay_interrupt_return) 25500f0c6ca1SNicholas Piggin mfcr r9 25510f0c6ca1SNicholas Piggin ori r12,r12,MSR_EE 25520f0c6ca1SNicholas Piggin cmpwi r3,0x900 25530f0c6ca1SNicholas Piggin beq decrementer_common 25540f0c6ca1SNicholas Piggin cmpwi r3,0x500 2555e6c1203dSNicholas PigginBEGIN_FTR_SECTION 2556e6c1203dSNicholas Piggin beq h_virt_irq_common 2557e6c1203dSNicholas PigginFTR_SECTION_ELSE 25580f0c6ca1SNicholas Piggin beq hardware_interrupt_common 2559e6c1203dSNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) 2560f442d004SMadhavan Srinivasan cmpwi r3,0xf00 2561f442d004SMadhavan Srinivasan beq performance_monitor_common 25620f0c6ca1SNicholas PigginBEGIN_FTR_SECTION 2563d6f73fc6SNicholas Piggin cmpwi r3,0xa00 2564a9af97aaSNicholas Piggin beq h_doorbell_common_msgclr 25650f0c6ca1SNicholas Piggin cmpwi r3,0xe60 25660f0c6ca1SNicholas Piggin beq hmi_exception_common 25670f0c6ca1SNicholas PigginFTR_SECTION_ELSE 25680f0c6ca1SNicholas Piggin cmpwi r3,0xa00 2569a9af97aaSNicholas Piggin beq doorbell_super_common_msgclr 25700f0c6ca1SNicholas PigginALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) 25713e23a12bSMichael Ellermanreplay_interrupt_return: 25720f0c6ca1SNicholas Piggin blr 2573b48bbb82SNicholas Piggin 257415770a13SNaveen N. Rao_ASM_NOKPROBE_SYMBOL(__replay_interrupt) 2575