1/* 2 * Boot code and exception vectors for Book3E processors 3 * 4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/threads.h> 13#include <asm/reg.h> 14#include <asm/page.h> 15#include <asm/ppc_asm.h> 16#include <asm/asm-offsets.h> 17#include <asm/cputable.h> 18#include <asm/setup.h> 19#include <asm/thread_info.h> 20#include <asm/reg_a2.h> 21#include <asm/exception-64e.h> 22#include <asm/bug.h> 23#include <asm/irqflags.h> 24#include <asm/ptrace.h> 25#include <asm/ppc-opcode.h> 26#include <asm/mmu.h> 27#include <asm/hw_irq.h> 28#include <asm/kvm_asm.h> 29#include <asm/kvm_booke_hv_asm.h> 30 31/* XXX This will ultimately add space for a special exception save 32 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... 33 * when taking special interrupts. For now we don't support that, 34 * special interrupts from within a non-standard level will probably 35 * blow you up 36 */ 37#define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE 38 39/* Exception prolog code for all exceptions */ 40#define EXCEPTION_PROLOG(n, intnum, type, addition) \ 41 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ 42 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ 43 std r10,PACA_EX##type+EX_R10(r13); \ 44 std r11,PACA_EX##type+EX_R11(r13); \ 45 PROLOG_STORE_RESTORE_SCRATCH_##type; \ 46 mfcr r10; /* save CR */ \ 47 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ 48 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ 49 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ 50 addition; /* additional code for that exc. */ \ 51 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ 52 type##_SET_KSTACK; /* get special stack if necessary */\ 53 andi. r10,r11,MSR_PR; /* save stack pointer */ \ 54 beq 1f; /* branch around if supervisor */ \ 55 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ 561: cmpdi cr1,r1,0; /* check if SP makes sense */ \ 57 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ 58 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ 59 60/* Exception type-specific macros */ 61#define GEN_SET_KSTACK \ 62 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ 63#define SPRN_GEN_SRR0 SPRN_SRR0 64#define SPRN_GEN_SRR1 SPRN_SRR1 65 66#define GDBELL_SET_KSTACK GEN_SET_KSTACK 67#define SPRN_GDBELL_SRR0 SPRN_GSRR0 68#define SPRN_GDBELL_SRR1 SPRN_GSRR1 69 70#define CRIT_SET_KSTACK \ 71 ld r1,PACA_CRIT_STACK(r13); \ 72 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 73#define SPRN_CRIT_SRR0 SPRN_CSRR0 74#define SPRN_CRIT_SRR1 SPRN_CSRR1 75 76#define DBG_SET_KSTACK \ 77 ld r1,PACA_DBG_STACK(r13); \ 78 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 79#define SPRN_DBG_SRR0 SPRN_DSRR0 80#define SPRN_DBG_SRR1 SPRN_DSRR1 81 82#define MC_SET_KSTACK \ 83 ld r1,PACA_MC_STACK(r13); \ 84 subi r1,r1,SPECIAL_EXC_FRAME_SIZE; 85#define SPRN_MC_SRR0 SPRN_MCSRR0 86#define SPRN_MC_SRR1 SPRN_MCSRR1 87 88#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ 89 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) 90 91#define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \ 92 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n)) 93 94#define DBG_EXCEPTION_PROLOG(n, intnum, addition) \ 95 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n)) 96 97#define MC_EXCEPTION_PROLOG(n, intnum, addition) \ 98 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n)) 99 100#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ 101 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) 102 103/* 104 * Store user-visible scratch in PACA exception slots and restore proper value 105 */ 106#define PROLOG_STORE_RESTORE_SCRATCH_GEN 107#define PROLOG_STORE_RESTORE_SCRATCH_GDBELL 108#define PROLOG_STORE_RESTORE_SCRATCH_DBG 109#define PROLOG_STORE_RESTORE_SCRATCH_MC 110 111#define PROLOG_STORE_RESTORE_SCRATCH_CRIT \ 112 mfspr r10,SPRN_SPRG_CRIT_SCRATCH; /* get r13 */ \ 113 std r10,PACA_EXCRIT+EX_R13(r13); \ 114 ld r11,PACA_SPRG3(r13); \ 115 mtspr SPRN_SPRG_CRIT_SCRATCH,r11; 116 117/* Variants of the "addition" argument for the prolog 118 */ 119#define PROLOG_ADDITION_NONE_GEN(n) 120#define PROLOG_ADDITION_NONE_GDBELL(n) 121#define PROLOG_ADDITION_NONE_CRIT(n) 122#define PROLOG_ADDITION_NONE_DBG(n) 123#define PROLOG_ADDITION_NONE_MC(n) 124 125#define PROLOG_ADDITION_MASKABLE_GEN(n) \ 126 lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \ 127 cmpwi cr0,r10,0; /* yes -> go out of line */ \ 128 beq masked_interrupt_book3e_##n 129 130#define PROLOG_ADDITION_2REGS_GEN(n) \ 131 std r14,PACA_EXGEN+EX_R14(r13); \ 132 std r15,PACA_EXGEN+EX_R15(r13) 133 134#define PROLOG_ADDITION_1REG_GEN(n) \ 135 std r14,PACA_EXGEN+EX_R14(r13); 136 137#define PROLOG_ADDITION_2REGS_CRIT(n) \ 138 std r14,PACA_EXCRIT+EX_R14(r13); \ 139 std r15,PACA_EXCRIT+EX_R15(r13) 140 141#define PROLOG_ADDITION_2REGS_DBG(n) \ 142 std r14,PACA_EXDBG+EX_R14(r13); \ 143 std r15,PACA_EXDBG+EX_R15(r13) 144 145#define PROLOG_ADDITION_2REGS_MC(n) \ 146 std r14,PACA_EXMC+EX_R14(r13); \ 147 std r15,PACA_EXMC+EX_R15(r13) 148 149 150/* Core exception code for all exceptions except TLB misses. 151 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type 152 */ 153#define EXCEPTION_COMMON(n, excf, ints) \ 154exc_##n##_common: \ 155 std r0,GPR0(r1); /* save r0 in stackframe */ \ 156 std r2,GPR2(r1); /* save r2 in stackframe */ \ 157 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 158 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 159 std r9,GPR9(r1); /* save r9 in stackframe */ \ 160 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 161 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 162 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \ 163 ld r3,excf+EX_R10(r13); /* get back r10 */ \ 164 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 165 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \ 166 std r12,GPR12(r1); /* save r12 in stackframe */ \ 167 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 168 mflr r6; /* save LR in stackframe */ \ 169 mfctr r7; /* save CTR in stackframe */ \ 170 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 171 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 172 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 173 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \ 174 ld r12,exception_marker@toc(r2); \ 175 li r0,0; \ 176 std r3,GPR10(r1); /* save r10 to stackframe */ \ 177 std r4,GPR11(r1); /* save r11 to stackframe */ \ 178 std r5,GPR13(r1); /* save it to stackframe */ \ 179 std r6,_LINK(r1); \ 180 std r7,_CTR(r1); \ 181 std r8,_XER(r1); \ 182 li r3,(n)+1; /* indicate partial regs in trap */ \ 183 std r9,0(r1); /* store stack frame back link */ \ 184 std r10,_CCR(r1); /* store orig CR in stackframe */ \ 185 std r9,GPR1(r1); /* store stack frame back link */ \ 186 std r11,SOFTE(r1); /* and save it to stackframe */ \ 187 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 188 std r3,_TRAP(r1); /* set trap number */ \ 189 std r0,RESULT(r1); /* clear regs->result */ \ 190 ints; 191 192/* Variants for the "ints" argument. This one does nothing when we want 193 * to keep interrupts in their original state 194 */ 195#define INTS_KEEP 196 197/* This second version is meant for exceptions that don't immediately 198 * hard-enable. We set a bit in paca->irq_happened to ensure that 199 * a subsequent call to arch_local_irq_restore() will properly 200 * hard-enable and avoid the fast-path 201 */ 202#define INTS_DISABLE SOFT_DISABLE_INTS(r3,r4) 203 204/* This is called by exceptions that used INTS_KEEP (that did not touch 205 * irq indicators in the PACA). This will restore MSR:EE to it's previous 206 * value 207 * 208 * XXX In the long run, we may want to open-code it in order to separate the 209 * load from the wrtee, thus limiting the latency caused by the dependency 210 * but at this point, I'll favor code clarity until we have a near to final 211 * implementation 212 */ 213#define INTS_RESTORE_HARD \ 214 ld r11,_MSR(r1); \ 215 wrtee r11; 216 217/* XXX FIXME: Restore r14/r15 when necessary */ 218#define BAD_STACK_TRAMPOLINE(n) \ 219exc_##n##_bad_stack: \ 220 li r1,(n); /* get exception number */ \ 221 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ 222 b bad_stack_book3e; /* bad stack error */ 223 224/* WARNING: If you change the layout of this stub, make sure you chcek 225 * the debug exception handler which handles single stepping 226 * into exceptions from userspace, and the MM code in 227 * arch/powerpc/mm/tlb_nohash.c which patches the branch here 228 * and would need to be updated if that branch is moved 229 */ 230#define EXCEPTION_STUB(loc, label) \ 231 . = interrupt_base_book3e + loc; \ 232 nop; /* To make debug interrupts happy */ \ 233 b exc_##label##_book3e; 234 235#define ACK_NONE(r) 236#define ACK_DEC(r) \ 237 lis r,TSR_DIS@h; \ 238 mtspr SPRN_TSR,r 239#define ACK_FIT(r) \ 240 lis r,TSR_FIS@h; \ 241 mtspr SPRN_TSR,r 242 243/* Used by asynchronous interrupt that may happen in the idle loop. 244 * 245 * This check if the thread was in the idle loop, and if yes, returns 246 * to the caller rather than the PC. This is to avoid a race if 247 * interrupts happen before the wait instruction. 248 */ 249#define CHECK_NAPPING() \ 250 CURRENT_THREAD_INFO(r11, r1); \ 251 ld r10,TI_LOCAL_FLAGS(r11); \ 252 andi. r9,r10,_TLF_NAPPING; \ 253 beq+ 1f; \ 254 ld r8,_LINK(r1); \ 255 rlwinm r7,r10,0,~_TLF_NAPPING; \ 256 std r8,_NIP(r1); \ 257 std r7,TI_LOCAL_FLAGS(r11); \ 2581: 259 260 261#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ 262 START_EXCEPTION(label); \ 263 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ 264 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE) \ 265 ack(r8); \ 266 CHECK_NAPPING(); \ 267 addi r3,r1,STACK_FRAME_OVERHEAD; \ 268 bl hdlr; \ 269 b .ret_from_except_lite; 270 271/* This value is used to mark exception frames on the stack. */ 272 .section ".toc","aw" 273exception_marker: 274 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 275 276 277/* 278 * And here we have the exception vectors ! 279 */ 280 281 .text 282 .balign 0x1000 283 .globl interrupt_base_book3e 284interrupt_base_book3e: /* fake trap */ 285 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */ 286 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */ 287 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 288 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ 289 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ 290 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ 291 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ 292 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ 293 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ 294 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ 295 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ 296 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ 297 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ 298 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 299 EXCEPTION_STUB(0x1c0, data_tlb_miss) 300 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 301 EXCEPTION_STUB(0x260, perfmon) 302 EXCEPTION_STUB(0x280, doorbell) 303 EXCEPTION_STUB(0x2a0, doorbell_crit) 304 EXCEPTION_STUB(0x2c0, guest_doorbell) 305 EXCEPTION_STUB(0x2e0, guest_doorbell_crit) 306 EXCEPTION_STUB(0x300, hypercall) 307 EXCEPTION_STUB(0x320, ehpriv) 308 309 .globl interrupt_end_book3e 310interrupt_end_book3e: 311 312/* Critical Input Interrupt */ 313 START_EXCEPTION(critical_input); 314 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, 315 PROLOG_ADDITION_NONE) 316// EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE) 317// bl special_reg_save_crit 318// CHECK_NAPPING(); 319// addi r3,r1,STACK_FRAME_OVERHEAD 320// bl .critical_exception 321// b ret_from_crit_except 322 b . 323 324/* Machine Check Interrupt */ 325 START_EXCEPTION(machine_check); 326 MC_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_MACHINE_CHECK, 327 PROLOG_ADDITION_NONE) 328// EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE) 329// bl special_reg_save_mc 330// addi r3,r1,STACK_FRAME_OVERHEAD 331// CHECK_NAPPING(); 332// bl .machine_check_exception 333// b ret_from_mc_except 334 b . 335 336/* Data Storage Interrupt */ 337 START_EXCEPTION(data_storage) 338 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE, 339 PROLOG_ADDITION_2REGS) 340 mfspr r14,SPRN_DEAR 341 mfspr r15,SPRN_ESR 342 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE) 343 b storage_fault_common 344 345/* Instruction Storage Interrupt */ 346 START_EXCEPTION(instruction_storage); 347 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE, 348 PROLOG_ADDITION_2REGS) 349 li r15,0 350 mr r14,r10 351 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE) 352 b storage_fault_common 353 354/* External Input Interrupt */ 355 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL, 356 external_input, .do_IRQ, ACK_NONE) 357 358/* Alignment */ 359 START_EXCEPTION(alignment); 360 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT, 361 PROLOG_ADDITION_2REGS) 362 mfspr r14,SPRN_DEAR 363 mfspr r15,SPRN_ESR 364 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP) 365 b alignment_more /* no room, go out of line */ 366 367/* Program Interrupt */ 368 START_EXCEPTION(program); 369 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, 370 PROLOG_ADDITION_1REG) 371 mfspr r14,SPRN_ESR 372 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE) 373 std r14,_DSISR(r1) 374 addi r3,r1,STACK_FRAME_OVERHEAD 375 ld r14,PACA_EXGEN+EX_R14(r13) 376 bl .save_nvgprs 377 bl .program_check_exception 378 b .ret_from_except 379 380/* Floating Point Unavailable Interrupt */ 381 START_EXCEPTION(fp_unavailable); 382 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, 383 PROLOG_ADDITION_NONE) 384 /* we can probably do a shorter exception entry for that one... */ 385 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP) 386 ld r12,_MSR(r1) 387 andi. r0,r12,MSR_PR; 388 beq- 1f 389 bl .load_up_fpu 390 b fast_exception_return 3911: INTS_DISABLE 392 bl .save_nvgprs 393 addi r3,r1,STACK_FRAME_OVERHEAD 394 bl .kernel_fp_unavailable_exception 395 b .ret_from_except 396 397/* Decrementer Interrupt */ 398 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, 399 decrementer, .timer_interrupt, ACK_DEC) 400 401/* Fixed Interval Timer Interrupt */ 402 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT, 403 fixed_interval, .unknown_exception, ACK_FIT) 404 405/* Watchdog Timer Interrupt */ 406 START_EXCEPTION(watchdog); 407 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, 408 PROLOG_ADDITION_NONE) 409// EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE) 410// bl special_reg_save_crit 411// CHECK_NAPPING(); 412// addi r3,r1,STACK_FRAME_OVERHEAD 413// bl .unknown_exception 414// b ret_from_crit_except 415 b . 416 417/* System Call Interrupt */ 418 START_EXCEPTION(system_call) 419 mr r9,r13 /* keep a copy of userland r13 */ 420 mfspr r11,SPRN_SRR0 /* get return address */ 421 mfspr r12,SPRN_SRR1 /* get previous MSR */ 422 mfspr r13,SPRN_SPRG_PACA /* get our PACA */ 423 b system_call_common 424 425/* Auxiliary Processor Unavailable Interrupt */ 426 START_EXCEPTION(ap_unavailable); 427 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, 428 PROLOG_ADDITION_NONE) 429 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE) 430 bl .save_nvgprs 431 addi r3,r1,STACK_FRAME_OVERHEAD 432 bl .unknown_exception 433 b .ret_from_except 434 435/* Debug exception as a critical interrupt*/ 436 START_EXCEPTION(debug_crit); 437 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 438 PROLOG_ADDITION_2REGS) 439 440 /* 441 * If there is a single step or branch-taken exception in an 442 * exception entry sequence, it was probably meant to apply to 443 * the code where the exception occurred (since exception entry 444 * doesn't turn off DE automatically). We simulate the effect 445 * of turning off DE on entry to an exception handler by turning 446 * off DE in the CSRR1 value and clearing the debug status. 447 */ 448 449 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 450 andis. r15,r14,DBSR_IC@h 451 beq+ 1f 452 453 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 454 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e) 455 cmpld cr0,r10,r14 456 cmpld cr1,r10,r15 457 blt+ cr0,1f 458 bge+ cr1,1f 459 460 /* here it looks like we got an inappropriate debug exception. */ 461 lis r14,DBSR_IC@h /* clear the IC event */ 462 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ 463 mtspr SPRN_DBSR,r14 464 mtspr SPRN_CSRR1,r11 465 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ 466 ld r1,PACA_EXCRIT+EX_R1(r13) 467 ld r14,PACA_EXCRIT+EX_R14(r13) 468 ld r15,PACA_EXCRIT+EX_R15(r13) 469 mtcr r10 470 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ 471 ld r11,PACA_EXCRIT+EX_R11(r13) 472 ld r13,PACA_EXCRIT+EX_R13(r13) 473 rfci 474 475 /* Normal debug exception */ 476 /* XXX We only handle coming from userspace for now since we can't 477 * quite save properly an interrupted kernel state yet 478 */ 4791: andi. r14,r11,MSR_PR; /* check for userspace again */ 480 beq kernel_dbg_exc; /* if from kernel mode */ 481 482 /* Now we mash up things to make it look like we are coming on a 483 * normal exception 484 */ 485 ld r15,PACA_EXCRIT+EX_R13(r13) 486 mtspr SPRN_SPRG_GEN_SCRATCH,r15 487 mfspr r14,SPRN_DBSR 488 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE) 489 std r14,_DSISR(r1) 490 addi r3,r1,STACK_FRAME_OVERHEAD 491 mr r4,r14 492 ld r14,PACA_EXCRIT+EX_R14(r13) 493 ld r15,PACA_EXCRIT+EX_R15(r13) 494 bl .save_nvgprs 495 bl .DebugException 496 b .ret_from_except 497 498kernel_dbg_exc: 499 b . /* NYI */ 500 501/* Debug exception as a debug interrupt*/ 502 START_EXCEPTION(debug_debug); 503 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 504 PROLOG_ADDITION_2REGS) 505 506 /* 507 * If there is a single step or branch-taken exception in an 508 * exception entry sequence, it was probably meant to apply to 509 * the code where the exception occurred (since exception entry 510 * doesn't turn off DE automatically). We simulate the effect 511 * of turning off DE on entry to an exception handler by turning 512 * off DE in the DSRR1 value and clearing the debug status. 513 */ 514 515 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 516 andis. r15,r14,DBSR_IC@h 517 beq+ 1f 518 519 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e) 520 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e) 521 cmpld cr0,r10,r14 522 cmpld cr1,r10,r15 523 blt+ cr0,1f 524 bge+ cr1,1f 525 526 /* here it looks like we got an inappropriate debug exception. */ 527 lis r14,DBSR_IC@h /* clear the IC event */ 528 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */ 529 mtspr SPRN_DBSR,r14 530 mtspr SPRN_DSRR1,r11 531 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */ 532 ld r1,PACA_EXDBG+EX_R1(r13) 533 ld r14,PACA_EXDBG+EX_R14(r13) 534 ld r15,PACA_EXDBG+EX_R15(r13) 535 mtcr r10 536 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */ 537 ld r11,PACA_EXDBG+EX_R11(r13) 538 mfspr r13,SPRN_SPRG_DBG_SCRATCH 539 rfdi 540 541 /* Normal debug exception */ 542 /* XXX We only handle coming from userspace for now since we can't 543 * quite save properly an interrupted kernel state yet 544 */ 5451: andi. r14,r11,MSR_PR; /* check for userspace again */ 546 beq kernel_dbg_exc; /* if from kernel mode */ 547 548 /* Now we mash up things to make it look like we are coming on a 549 * normal exception 550 */ 551 mfspr r15,SPRN_SPRG_DBG_SCRATCH 552 mtspr SPRN_SPRG_GEN_SCRATCH,r15 553 mfspr r14,SPRN_DBSR 554 EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE) 555 std r14,_DSISR(r1) 556 addi r3,r1,STACK_FRAME_OVERHEAD 557 mr r4,r14 558 ld r14,PACA_EXDBG+EX_R14(r13) 559 ld r15,PACA_EXDBG+EX_R15(r13) 560 bl .save_nvgprs 561 bl .DebugException 562 b .ret_from_except 563 564 START_EXCEPTION(perfmon); 565 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, 566 PROLOG_ADDITION_NONE) 567 EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE) 568 addi r3,r1,STACK_FRAME_OVERHEAD 569 bl .performance_monitor_exception 570 b .ret_from_except_lite 571 572/* Doorbell interrupt */ 573 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL, 574 doorbell, .doorbell_exception, ACK_NONE) 575 576/* Doorbell critical Interrupt */ 577 START_EXCEPTION(doorbell_crit); 578 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, 579 PROLOG_ADDITION_NONE) 580// EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE) 581// bl special_reg_save_crit 582// CHECK_NAPPING(); 583// addi r3,r1,STACK_FRAME_OVERHEAD 584// bl .doorbell_critical_exception 585// b ret_from_crit_except 586 b . 587 588/* 589 * Guest doorbell interrupt 590 * This general exception use GSRRx save/restore registers 591 */ 592 START_EXCEPTION(guest_doorbell); 593 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, 594 PROLOG_ADDITION_NONE) 595 EXCEPTION_COMMON(0x2c0, PACA_EXGEN, INTS_KEEP) 596 addi r3,r1,STACK_FRAME_OVERHEAD 597 bl .save_nvgprs 598 INTS_RESTORE_HARD 599 bl .unknown_exception 600 b .ret_from_except 601 602/* Guest Doorbell critical Interrupt */ 603 START_EXCEPTION(guest_doorbell_crit); 604 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, 605 PROLOG_ADDITION_NONE) 606// EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE) 607// bl special_reg_save_crit 608// CHECK_NAPPING(); 609// addi r3,r1,STACK_FRAME_OVERHEAD 610// bl .guest_doorbell_critical_exception 611// b ret_from_crit_except 612 b . 613 614/* Hypervisor call */ 615 START_EXCEPTION(hypercall); 616 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, 617 PROLOG_ADDITION_NONE) 618 EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP) 619 addi r3,r1,STACK_FRAME_OVERHEAD 620 bl .save_nvgprs 621 INTS_RESTORE_HARD 622 bl .unknown_exception 623 b .ret_from_except 624 625/* Embedded Hypervisor priviledged */ 626 START_EXCEPTION(ehpriv); 627 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, 628 PROLOG_ADDITION_NONE) 629 EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP) 630 addi r3,r1,STACK_FRAME_OVERHEAD 631 bl .save_nvgprs 632 INTS_RESTORE_HARD 633 bl .unknown_exception 634 b .ret_from_except 635 636/* 637 * An interrupt came in while soft-disabled; We mark paca->irq_happened 638 * accordingly and if the interrupt is level sensitive, we hard disable 639 */ 640 641.macro masked_interrupt_book3e paca_irq full_mask 642 lbz r10,PACAIRQHAPPENED(r13) 643 ori r10,r10,\paca_irq 644 stb r10,PACAIRQHAPPENED(r13) 645 646 .if \full_mask == 1 647 rldicl r10,r11,48,1 /* clear MSR_EE */ 648 rotldi r11,r10,16 649 mtspr SPRN_SRR1,r11 650 .endif 651 652 lwz r11,PACA_EXGEN+EX_CR(r13) 653 mtcr r11 654 ld r10,PACA_EXGEN+EX_R10(r13) 655 ld r11,PACA_EXGEN+EX_R11(r13) 656 mfspr r13,SPRN_SPRG_GEN_SCRATCH 657 rfi 658 b . 659.endm 660 661masked_interrupt_book3e_0x500: 662 // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE 663 masked_interrupt_book3e PACA_IRQ_EE 1 664 665masked_interrupt_book3e_0x900: 666 ACK_DEC(r10); 667 masked_interrupt_book3e PACA_IRQ_DEC 0 668 669masked_interrupt_book3e_0x980: 670 ACK_FIT(r10); 671 masked_interrupt_book3e PACA_IRQ_DEC 0 672 673masked_interrupt_book3e_0x280: 674masked_interrupt_book3e_0x2c0: 675 masked_interrupt_book3e PACA_IRQ_DBELL 0 676 677/* 678 * Called from arch_local_irq_enable when an interrupt needs 679 * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280 680 * to indicate the kind of interrupt. MSR:EE is already off. 681 * We generate a stackframe like if a real interrupt had happened. 682 * 683 * Note: While MSR:EE is off, we need to make sure that _MSR 684 * in the generated frame has EE set to 1 or the exception 685 * handler will not properly re-enable them. 686 */ 687_GLOBAL(__replay_interrupt) 688 /* We are going to jump to the exception common code which 689 * will retrieve various register values from the PACA which 690 * we don't give a damn about. 691 */ 692 mflr r10 693 mfmsr r11 694 mfcr r4 695 mtspr SPRN_SPRG_GEN_SCRATCH,r13; 696 std r1,PACA_EXGEN+EX_R1(r13); 697 stw r4,PACA_EXGEN+EX_CR(r13); 698 ori r11,r11,MSR_EE 699 subi r1,r1,INT_FRAME_SIZE; 700 cmpwi cr0,r3,0x500 701 beq exc_0x500_common 702 cmpwi cr0,r3,0x900 703 beq exc_0x900_common 704 cmpwi cr0,r3,0x280 705 beq exc_0x280_common 706 blr 707 708 709/* 710 * This is called from 0x300 and 0x400 handlers after the prologs with 711 * r14 and r15 containing the fault address and error code, with the 712 * original values stashed away in the PACA 713 */ 714storage_fault_common: 715 std r14,_DAR(r1) 716 std r15,_DSISR(r1) 717 addi r3,r1,STACK_FRAME_OVERHEAD 718 mr r4,r14 719 mr r5,r15 720 ld r14,PACA_EXGEN+EX_R14(r13) 721 ld r15,PACA_EXGEN+EX_R15(r13) 722 bl .do_page_fault 723 cmpdi r3,0 724 bne- 1f 725 b .ret_from_except_lite 7261: bl .save_nvgprs 727 mr r5,r3 728 addi r3,r1,STACK_FRAME_OVERHEAD 729 ld r4,_DAR(r1) 730 bl .bad_page_fault 731 b .ret_from_except 732 733/* 734 * Alignment exception doesn't fit entirely in the 0x100 bytes so it 735 * continues here. 736 */ 737alignment_more: 738 std r14,_DAR(r1) 739 std r15,_DSISR(r1) 740 addi r3,r1,STACK_FRAME_OVERHEAD 741 ld r14,PACA_EXGEN+EX_R14(r13) 742 ld r15,PACA_EXGEN+EX_R15(r13) 743 bl .save_nvgprs 744 INTS_RESTORE_HARD 745 bl .alignment_exception 746 b .ret_from_except 747 748/* 749 * We branch here from entry_64.S for the last stage of the exception 750 * return code path. MSR:EE is expected to be off at that point 751 */ 752_GLOBAL(exception_return_book3e) 753 b 1f 754 755/* This is the return from load_up_fpu fast path which could do with 756 * less GPR restores in fact, but for now we have a single return path 757 */ 758 .globl fast_exception_return 759fast_exception_return: 760 wrteei 0 7611: mr r0,r13 762 ld r10,_MSR(r1) 763 REST_4GPRS(2, r1) 764 andi. r6,r10,MSR_PR 765 REST_2GPRS(6, r1) 766 beq 1f 767 ACCOUNT_CPU_USER_EXIT(r10, r11) 768 ld r0,GPR13(r1) 769 7701: stdcx. r0,0,r1 /* to clear the reservation */ 771 772 ld r8,_CCR(r1) 773 ld r9,_LINK(r1) 774 ld r10,_CTR(r1) 775 ld r11,_XER(r1) 776 mtcr r8 777 mtlr r9 778 mtctr r10 779 mtxer r11 780 REST_2GPRS(8, r1) 781 ld r10,GPR10(r1) 782 ld r11,GPR11(r1) 783 ld r12,GPR12(r1) 784 mtspr SPRN_SPRG_GEN_SCRATCH,r0 785 786 std r10,PACA_EXGEN+EX_R10(r13); 787 std r11,PACA_EXGEN+EX_R11(r13); 788 ld r10,_NIP(r1) 789 ld r11,_MSR(r1) 790 ld r0,GPR0(r1) 791 ld r1,GPR1(r1) 792 mtspr SPRN_SRR0,r10 793 mtspr SPRN_SRR1,r11 794 ld r10,PACA_EXGEN+EX_R10(r13) 795 ld r11,PACA_EXGEN+EX_R11(r13) 796 mfspr r13,SPRN_SPRG_GEN_SCRATCH 797 rfi 798 799/* 800 * Trampolines used when spotting a bad kernel stack pointer in 801 * the exception entry code. 802 * 803 * TODO: move some bits like SRR0 read to trampoline, pass PACA 804 * index around, etc... to handle crit & mcheck 805 */ 806BAD_STACK_TRAMPOLINE(0x000) 807BAD_STACK_TRAMPOLINE(0x100) 808BAD_STACK_TRAMPOLINE(0x200) 809BAD_STACK_TRAMPOLINE(0x260) 810BAD_STACK_TRAMPOLINE(0x280) 811BAD_STACK_TRAMPOLINE(0x2a0) 812BAD_STACK_TRAMPOLINE(0x2c0) 813BAD_STACK_TRAMPOLINE(0x2e0) 814BAD_STACK_TRAMPOLINE(0x300) 815BAD_STACK_TRAMPOLINE(0x310) 816BAD_STACK_TRAMPOLINE(0x320) 817BAD_STACK_TRAMPOLINE(0x400) 818BAD_STACK_TRAMPOLINE(0x500) 819BAD_STACK_TRAMPOLINE(0x600) 820BAD_STACK_TRAMPOLINE(0x700) 821BAD_STACK_TRAMPOLINE(0x800) 822BAD_STACK_TRAMPOLINE(0x900) 823BAD_STACK_TRAMPOLINE(0x980) 824BAD_STACK_TRAMPOLINE(0x9f0) 825BAD_STACK_TRAMPOLINE(0xa00) 826BAD_STACK_TRAMPOLINE(0xb00) 827BAD_STACK_TRAMPOLINE(0xc00) 828BAD_STACK_TRAMPOLINE(0xd00) 829BAD_STACK_TRAMPOLINE(0xd08) 830BAD_STACK_TRAMPOLINE(0xe00) 831BAD_STACK_TRAMPOLINE(0xf00) 832BAD_STACK_TRAMPOLINE(0xf20) 833 834 .globl bad_stack_book3e 835bad_stack_book3e: 836 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ 837 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ 838 ld r1,PACAEMERGSP(r13) 839 subi r1,r1,64+INT_FRAME_SIZE 840 std r10,_NIP(r1) 841 std r11,_MSR(r1) 842 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ 843 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ 844 std r10,GPR1(r1) 845 std r11,_CCR(r1) 846 mfspr r10,SPRN_DEAR 847 mfspr r11,SPRN_ESR 848 std r10,_DAR(r1) 849 std r11,_DSISR(r1) 850 std r0,GPR0(r1); /* save r0 in stackframe */ \ 851 std r2,GPR2(r1); /* save r2 in stackframe */ \ 852 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 853 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 854 std r9,GPR9(r1); /* save r9 in stackframe */ \ 855 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 856 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 857 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 858 std r3,GPR10(r1); /* save r10 to stackframe */ \ 859 std r4,GPR11(r1); /* save r11 to stackframe */ \ 860 std r12,GPR12(r1); /* save r12 in stackframe */ \ 861 std r5,GPR13(r1); /* save it to stackframe */ \ 862 mflr r10 863 mfctr r11 864 mfxer r12 865 std r10,_LINK(r1) 866 std r11,_CTR(r1) 867 std r12,_XER(r1) 868 SAVE_10GPRS(14,r1) 869 SAVE_8GPRS(24,r1) 870 lhz r12,PACA_TRAP_SAVE(r13) 871 std r12,_TRAP(r1) 872 addi r11,r1,INT_FRAME_SIZE 873 std r11,0(r1) 874 li r12,0 875 std r12,0(r11) 876 ld r2,PACATOC(r13) 8771: addi r3,r1,STACK_FRAME_OVERHEAD 878 bl .kernel_bad_stack 879 b 1b 880 881/* 882 * Setup the initial TLB for a core. This current implementation 883 * assume that whatever we are running off will not conflict with 884 * the new mapping at PAGE_OFFSET. 885 */ 886_GLOBAL(initial_tlb_book3e) 887 888 /* Look for the first TLB with IPROT set */ 889 mfspr r4,SPRN_TLB0CFG 890 andi. r3,r4,TLBnCFG_IPROT 891 lis r3,MAS0_TLBSEL(0)@h 892 bne found_iprot 893 894 mfspr r4,SPRN_TLB1CFG 895 andi. r3,r4,TLBnCFG_IPROT 896 lis r3,MAS0_TLBSEL(1)@h 897 bne found_iprot 898 899 mfspr r4,SPRN_TLB2CFG 900 andi. r3,r4,TLBnCFG_IPROT 901 lis r3,MAS0_TLBSEL(2)@h 902 bne found_iprot 903 904 lis r3,MAS0_TLBSEL(3)@h 905 mfspr r4,SPRN_TLB3CFG 906 /* fall through */ 907 908found_iprot: 909 andi. r5,r4,TLBnCFG_HES 910 bne have_hes 911 912 mflr r8 /* save LR */ 913/* 1. Find the index of the entry we're executing in 914 * 915 * r3 = MAS0_TLBSEL (for the iprot array) 916 * r4 = SPRN_TLBnCFG 917 */ 918 bl invstr /* Find our address */ 919invstr: mflr r6 /* Make it accessible */ 920 mfmsr r7 921 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ 922 mfspr r7,SPRN_PID 923 slwi r7,r7,16 924 or r7,r7,r5 925 mtspr SPRN_MAS6,r7 926 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ 927 928 mfspr r3,SPRN_MAS0 929 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ 930 931 mfspr r7,SPRN_MAS1 /* Insure IPROT set */ 932 oris r7,r7,MAS1_IPROT@h 933 mtspr SPRN_MAS1,r7 934 tlbwe 935 936/* 2. Invalidate all entries except the entry we're executing in 937 * 938 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 939 * r4 = SPRN_TLBnCFG 940 * r5 = ESEL of entry we are running in 941 */ 942 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ 943 li r6,0 /* Set Entry counter to 0 */ 9441: mr r7,r3 /* Set MAS0(TLBSEL) */ 945 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 946 mtspr SPRN_MAS0,r7 947 tlbre 948 mfspr r7,SPRN_MAS1 949 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ 950 cmpw r5,r6 951 beq skpinv /* Dont update the current execution TLB */ 952 mtspr SPRN_MAS1,r7 953 tlbwe 954 isync 955skpinv: addi r6,r6,1 /* Increment */ 956 cmpw r6,r4 /* Are we done? */ 957 bne 1b /* If not, repeat */ 958 959 /* Invalidate all TLBs */ 960 PPC_TLBILX_ALL(0,R0) 961 sync 962 isync 963 964/* 3. Setup a temp mapping and jump to it 965 * 966 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 967 * r5 = ESEL of entry we are running in 968 */ 969 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ 970 addi r7,r7,0x1 971 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ 972 mtspr SPRN_MAS0,r4 973 tlbre 974 975 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ 976 mtspr SPRN_MAS0,r4 977 978 mfspr r7,SPRN_MAS1 979 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ 980 mtspr SPRN_MAS1,r6 981 982 tlbwe 983 984 mfmsr r6 985 xori r6,r6,MSR_IS 986 mtspr SPRN_SRR1,r6 987 bl 1f /* Find our address */ 9881: mflr r6 989 addi r6,r6,(2f - 1b) 990 mtspr SPRN_SRR0,r6 991 rfi 9922: 993 994/* 4. Clear out PIDs & Search info 995 * 996 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 997 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 998 * r5 = MAS3 999 */ 1000 li r6,0 1001 mtspr SPRN_MAS6,r6 1002 mtspr SPRN_PID,r6 1003 1004/* 5. Invalidate mapping we started in 1005 * 1006 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1007 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1008 * r5 = MAS3 1009 */ 1010 mtspr SPRN_MAS0,r3 1011 tlbre 1012 mfspr r6,SPRN_MAS1 1013 rlwinm r6,r6,0,2,0 /* clear IPROT */ 1014 mtspr SPRN_MAS1,r6 1015 tlbwe 1016 1017 /* Invalidate TLB1 */ 1018 PPC_TLBILX_ALL(0,R0) 1019 sync 1020 isync 1021 1022/* The mapping only needs to be cache-coherent on SMP */ 1023#ifdef CONFIG_SMP 1024#define M_IF_SMP MAS2_M 1025#else 1026#define M_IF_SMP 0 1027#endif 1028 1029/* 6. Setup KERNELBASE mapping in TLB[0] 1030 * 1031 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1032 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1033 * r5 = MAS3 1034 */ 1035 rlwinm r3,r3,0,16,3 /* clear ESEL */ 1036 mtspr SPRN_MAS0,r3 1037 lis r6,(MAS1_VALID|MAS1_IPROT)@h 1038 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 1039 mtspr SPRN_MAS1,r6 1040 1041 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP) 1042 mtspr SPRN_MAS2,r6 1043 1044 rlwinm r5,r5,0,0,25 1045 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX 1046 mtspr SPRN_MAS3,r5 1047 li r5,-1 1048 rlwinm r5,r5,0,0,25 1049 1050 tlbwe 1051 1052/* 7. Jump to KERNELBASE mapping 1053 * 1054 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1055 */ 1056 /* Now we branch the new virtual address mapped by this entry */ 1057 LOAD_REG_IMMEDIATE(r6,2f) 1058 lis r7,MSR_KERNEL@h 1059 ori r7,r7,MSR_KERNEL@l 1060 mtspr SPRN_SRR0,r6 1061 mtspr SPRN_SRR1,r7 1062 rfi /* start execution out of TLB1[0] entry */ 10632: 1064 1065/* 8. Clear out the temp mapping 1066 * 1067 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1068 */ 1069 mtspr SPRN_MAS0,r4 1070 tlbre 1071 mfspr r5,SPRN_MAS1 1072 rlwinm r5,r5,0,2,0 /* clear IPROT */ 1073 mtspr SPRN_MAS1,r5 1074 tlbwe 1075 1076 /* Invalidate TLB1 */ 1077 PPC_TLBILX_ALL(0,R0) 1078 sync 1079 isync 1080 1081 /* We translate LR and return */ 1082 tovirt(r8,r8) 1083 mtlr r8 1084 blr 1085 1086have_hes: 1087 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the 1088 * kernel linear mapping. We also set MAS8 once for all here though 1089 * that will have to be made dependent on whether we are running under 1090 * a hypervisor I suppose. 1091 */ 1092 1093 /* BEWARE, MAGIC 1094 * This code is called as an ordinary function on the boot CPU. But to 1095 * avoid duplication, this code is also used in SCOM bringup of 1096 * secondary CPUs. We read the code between the initial_tlb_code_start 1097 * and initial_tlb_code_end labels one instruction at a time and RAM it 1098 * into the new core via SCOM. That doesn't process branches, so there 1099 * must be none between those two labels. It also means if this code 1100 * ever takes any parameters, the SCOM code must also be updated to 1101 * provide them. 1102 */ 1103 .globl a2_tlbinit_code_start 1104a2_tlbinit_code_start: 1105 1106 ori r11,r3,MAS0_WQ_ALLWAYS 1107 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ 1108 mtspr SPRN_MAS0,r11 1109 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1110 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT 1111 mtspr SPRN_MAS1,r3 1112 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) 1113 mtspr SPRN_MAS2,r3 1114 li r3,MAS3_SR | MAS3_SW | MAS3_SX 1115 mtspr SPRN_MAS7_MAS3,r3 1116 li r3,0 1117 mtspr SPRN_MAS8,r3 1118 1119 /* Write the TLB entry */ 1120 tlbwe 1121 1122 .globl a2_tlbinit_after_linear_map 1123a2_tlbinit_after_linear_map: 1124 1125 /* Now we branch the new virtual address mapped by this entry */ 1126 LOAD_REG_IMMEDIATE(r3,1f) 1127 mtctr r3 1128 bctr 1129 11301: /* We are now running at PAGE_OFFSET, clean the TLB of everything 1131 * else (including IPROTed things left by firmware) 1132 * r4 = TLBnCFG 1133 * r3 = current address (more or less) 1134 */ 1135 1136 li r5,0 1137 mtspr SPRN_MAS6,r5 1138 tlbsx 0,r3 1139 1140 rlwinm r9,r4,0,TLBnCFG_N_ENTRY 1141 rlwinm r10,r4,8,0xff 1142 addi r10,r10,-1 /* Get inner loop mask */ 1143 1144 li r3,1 1145 1146 mfspr r5,SPRN_MAS1 1147 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) 1148 1149 mfspr r6,SPRN_MAS2 1150 rldicr r6,r6,0,51 /* Extract EPN */ 1151 1152 mfspr r7,SPRN_MAS0 1153 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ 1154 1155 rlwinm r8,r7,16,0xfff /* Extract ESEL */ 1156 11572: add r4,r3,r8 1158 and r4,r4,r10 1159 1160 rlwimi r7,r4,16,MAS0_ESEL_MASK 1161 1162 mtspr SPRN_MAS0,r7 1163 mtspr SPRN_MAS1,r5 1164 mtspr SPRN_MAS2,r6 1165 tlbwe 1166 1167 addi r3,r3,1 1168 and. r4,r3,r10 1169 1170 bne 3f 1171 addis r6,r6,(1<<30)@h 11723: 1173 cmpw r3,r9 1174 blt 2b 1175 1176 .globl a2_tlbinit_after_iprot_flush 1177a2_tlbinit_after_iprot_flush: 1178 1179#ifdef CONFIG_PPC_EARLY_DEBUG_WSP 1180 /* Now establish early debug mappings if applicable */ 1181 /* Restore the MAS0 we used for linear mapping load */ 1182 mtspr SPRN_MAS0,r11 1183 1184 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1185 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT) 1186 mtspr SPRN_MAS1,r3 1187 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G) 1188 mtspr SPRN_MAS2,r3 1189 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW) 1190 mtspr SPRN_MAS7_MAS3,r3 1191 /* re-use the MAS8 value from the linear mapping */ 1192 tlbwe 1193#endif /* CONFIG_PPC_EARLY_DEBUG_WSP */ 1194 1195 PPC_TLBILX(0,0,R0) 1196 sync 1197 isync 1198 1199 .globl a2_tlbinit_code_end 1200a2_tlbinit_code_end: 1201 1202 /* We translate LR and return */ 1203 mflr r3 1204 tovirt(r3,r3) 1205 mtlr r3 1206 blr 1207 1208/* 1209 * Main entry (boot CPU, thread 0) 1210 * 1211 * We enter here from head_64.S, possibly after the prom_init trampoline 1212 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits 1213 * mode. Anything else is as it was left by the bootloader 1214 * 1215 * Initial requirements of this port: 1216 * 1217 * - Kernel loaded at 0 physical 1218 * - A good lump of memory mapped 0:0 by UTLB entry 0 1219 * - MSR:IS & MSR:DS set to 0 1220 * 1221 * Note that some of the above requirements will be relaxed in the future 1222 * as the kernel becomes smarter at dealing with different initial conditions 1223 * but for now you have to be careful 1224 */ 1225_GLOBAL(start_initialization_book3e) 1226 mflr r28 1227 1228 /* First, we need to setup some initial TLBs to map the kernel 1229 * text, data and bss at PAGE_OFFSET. We don't have a real mode 1230 * and always use AS 0, so we just set it up to match our link 1231 * address and never use 0 based addresses. 1232 */ 1233 bl .initial_tlb_book3e 1234 1235 /* Init global core bits */ 1236 bl .init_core_book3e 1237 1238 /* Init per-thread bits */ 1239 bl .init_thread_book3e 1240 1241 /* Return to common init code */ 1242 tovirt(r28,r28) 1243 mtlr r28 1244 blr 1245 1246 1247/* 1248 * Secondary core/processor entry 1249 * 1250 * This is entered for thread 0 of a secondary core, all other threads 1251 * are expected to be stopped. It's similar to start_initialization_book3e 1252 * except that it's generally entered from the holding loop in head_64.S 1253 * after CPUs have been gathered by Open Firmware. 1254 * 1255 * We assume we are in 32 bits mode running with whatever TLB entry was 1256 * set for us by the firmware or POR engine. 1257 */ 1258_GLOBAL(book3e_secondary_core_init_tlb_set) 1259 li r4,1 1260 b .generic_secondary_smp_init 1261 1262_GLOBAL(book3e_secondary_core_init) 1263 mflr r28 1264 1265 /* Do we need to setup initial TLB entry ? */ 1266 cmplwi r4,0 1267 bne 2f 1268 1269 /* Setup TLB for this core */ 1270 bl .initial_tlb_book3e 1271 1272 /* We can return from the above running at a different 1273 * address, so recalculate r2 (TOC) 1274 */ 1275 bl .relative_toc 1276 1277 /* Init global core bits */ 12782: bl .init_core_book3e 1279 1280 /* Init per-thread bits */ 12813: bl .init_thread_book3e 1282 1283 /* Return to common init code at proper virtual address. 1284 * 1285 * Due to various previous assumptions, we know we entered this 1286 * function at either the final PAGE_OFFSET mapping or using a 1287 * 1:1 mapping at 0, so we don't bother doing a complicated check 1288 * here, we just ensure the return address has the right top bits. 1289 * 1290 * Note that if we ever want to be smarter about where we can be 1291 * started from, we have to be careful that by the time we reach 1292 * the code below we may already be running at a different location 1293 * than the one we were called from since initial_tlb_book3e can 1294 * have moved us already. 1295 */ 1296 cmpdi cr0,r28,0 1297 blt 1f 1298 lis r3,PAGE_OFFSET@highest 1299 sldi r3,r3,32 1300 or r28,r28,r3 13011: mtlr r28 1302 blr 1303 1304_GLOBAL(book3e_secondary_thread_init) 1305 mflr r28 1306 b 3b 1307 1308_STATIC(init_core_book3e) 1309 /* Establish the interrupt vector base */ 1310 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e) 1311 mtspr SPRN_IVPR,r3 1312 sync 1313 blr 1314 1315_STATIC(init_thread_book3e) 1316 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h 1317 mtspr SPRN_EPCR,r3 1318 1319 /* Make sure interrupts are off */ 1320 wrteei 0 1321 1322 /* disable all timers and clear out status */ 1323 li r3,0 1324 mtspr SPRN_TCR,r3 1325 mfspr r3,SPRN_TSR 1326 mtspr SPRN_TSR,r3 1327 1328 blr 1329 1330_GLOBAL(__setup_base_ivors) 1331 SET_IVOR(0, 0x020) /* Critical Input */ 1332 SET_IVOR(1, 0x000) /* Machine Check */ 1333 SET_IVOR(2, 0x060) /* Data Storage */ 1334 SET_IVOR(3, 0x080) /* Instruction Storage */ 1335 SET_IVOR(4, 0x0a0) /* External Input */ 1336 SET_IVOR(5, 0x0c0) /* Alignment */ 1337 SET_IVOR(6, 0x0e0) /* Program */ 1338 SET_IVOR(7, 0x100) /* FP Unavailable */ 1339 SET_IVOR(8, 0x120) /* System Call */ 1340 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 1341 SET_IVOR(10, 0x160) /* Decrementer */ 1342 SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 1343 SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 1344 SET_IVOR(13, 0x1c0) /* Data TLB Error */ 1345 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ 1346 SET_IVOR(15, 0x040) /* Debug */ 1347 1348 sync 1349 1350 blr 1351 1352_GLOBAL(setup_perfmon_ivor) 1353 SET_IVOR(35, 0x260) /* Performance Monitor */ 1354 blr 1355 1356_GLOBAL(setup_doorbell_ivors) 1357 SET_IVOR(36, 0x280) /* Processor Doorbell */ 1358 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ 1359 blr 1360 1361_GLOBAL(setup_ehv_ivors) 1362 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ 1363 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ 1364 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ 1365 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ 1366 blr 1367