1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Boot code and exception vectors for Book3E processors 4 * 5 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. 6 */ 7 8#include <linux/threads.h> 9#include <asm/reg.h> 10#include <asm/page.h> 11#include <asm/ppc_asm.h> 12#include <asm/asm-offsets.h> 13#include <asm/cputable.h> 14#include <asm/setup.h> 15#include <asm/thread_info.h> 16#include <asm/reg_a2.h> 17#include <asm/exception-64e.h> 18#include <asm/bug.h> 19#include <asm/irqflags.h> 20#include <asm/ptrace.h> 21#include <asm/ppc-opcode.h> 22#include <asm/mmu.h> 23#include <asm/hw_irq.h> 24#include <asm/kvm_asm.h> 25#include <asm/kvm_booke_hv_asm.h> 26#include <asm/feature-fixups.h> 27#include <asm/context_tracking.h> 28 29/* 64e interrupt returns always use SRR registers */ 30#define fast_interrupt_return fast_interrupt_return_srr 31#define interrupt_return interrupt_return_srr 32 33/* XXX This will ultimately add space for a special exception save 34 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc... 35 * when taking special interrupts. For now we don't support that, 36 * special interrupts from within a non-standard level will probably 37 * blow you up 38 */ 39#define SPECIAL_EXC_SRR0 0 40#define SPECIAL_EXC_SRR1 1 41#define SPECIAL_EXC_SPRG_GEN 2 42#define SPECIAL_EXC_SPRG_TLB 3 43#define SPECIAL_EXC_MAS0 4 44#define SPECIAL_EXC_MAS1 5 45#define SPECIAL_EXC_MAS2 6 46#define SPECIAL_EXC_MAS3 7 47#define SPECIAL_EXC_MAS6 8 48#define SPECIAL_EXC_MAS7 9 49#define SPECIAL_EXC_MAS5 10 /* E.HV only */ 50#define SPECIAL_EXC_MAS8 11 /* E.HV only */ 51#define SPECIAL_EXC_IRQHAPPENED 12 52#define SPECIAL_EXC_DEAR 13 53#define SPECIAL_EXC_ESR 14 54#define SPECIAL_EXC_SOFTE 15 55#define SPECIAL_EXC_CSRR0 16 56#define SPECIAL_EXC_CSRR1 17 57/* must be even to keep 16-byte stack alignment */ 58#define SPECIAL_EXC_END 18 59 60#define SPECIAL_EXC_FRAME_SIZE (INT_FRAME_SIZE + SPECIAL_EXC_END * 8) 61#define SPECIAL_EXC_FRAME_OFFS (INT_FRAME_SIZE - 288) 62 63#define SPECIAL_EXC_STORE(reg, name) \ 64 std reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 65 66#define SPECIAL_EXC_LOAD(reg, name) \ 67 ld reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1) 68 69special_reg_save: 70 /* 71 * We only need (or have stack space) to save this stuff if 72 * we interrupted the kernel. 73 */ 74 ld r3,_MSR(r1) 75 andi. r3,r3,MSR_PR 76 bnelr 77 78 /* 79 * Advance to the next TLB exception frame for handler 80 * types that don't do it automatically. 81 */ 82 LOAD_REG_ADDR(r11,extlb_level_exc) 83 lwz r12,0(r11) 84 mfspr r10,SPRN_SPRG_TLB_EXFRAME 85 add r10,r10,r12 86 mtspr SPRN_SPRG_TLB_EXFRAME,r10 87 88 /* 89 * Save registers needed to allow nesting of certain exceptions 90 * (such as TLB misses) inside special exception levels 91 */ 92 mfspr r10,SPRN_SRR0 93 SPECIAL_EXC_STORE(r10,SRR0) 94 mfspr r10,SPRN_SRR1 95 SPECIAL_EXC_STORE(r10,SRR1) 96 mfspr r10,SPRN_SPRG_GEN_SCRATCH 97 SPECIAL_EXC_STORE(r10,SPRG_GEN) 98 mfspr r10,SPRN_SPRG_TLB_SCRATCH 99 SPECIAL_EXC_STORE(r10,SPRG_TLB) 100 mfspr r10,SPRN_MAS0 101 SPECIAL_EXC_STORE(r10,MAS0) 102 mfspr r10,SPRN_MAS1 103 SPECIAL_EXC_STORE(r10,MAS1) 104 mfspr r10,SPRN_MAS2 105 SPECIAL_EXC_STORE(r10,MAS2) 106 mfspr r10,SPRN_MAS3 107 SPECIAL_EXC_STORE(r10,MAS3) 108 mfspr r10,SPRN_MAS6 109 SPECIAL_EXC_STORE(r10,MAS6) 110 mfspr r10,SPRN_MAS7 111 SPECIAL_EXC_STORE(r10,MAS7) 112BEGIN_FTR_SECTION 113 mfspr r10,SPRN_MAS5 114 SPECIAL_EXC_STORE(r10,MAS5) 115 mfspr r10,SPRN_MAS8 116 SPECIAL_EXC_STORE(r10,MAS8) 117 118 /* MAS5/8 could have inappropriate values if we interrupted KVM code */ 119 li r10,0 120 mtspr SPRN_MAS5,r10 121 mtspr SPRN_MAS8,r10 122END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 123 mfspr r10,SPRN_DEAR 124 SPECIAL_EXC_STORE(r10,DEAR) 125 mfspr r10,SPRN_ESR 126 SPECIAL_EXC_STORE(r10,ESR) 127 128 ld r10,_NIP(r1) 129 SPECIAL_EXC_STORE(r10,CSRR0) 130 ld r10,_MSR(r1) 131 SPECIAL_EXC_STORE(r10,CSRR1) 132 133 blr 134 135ret_from_level_except: 136 ld r3,_MSR(r1) 137 andi. r3,r3,MSR_PR 138 beq 1f 139 REST_NVGPRS(r1) 140 b interrupt_return 1411: 142 143 LOAD_REG_ADDR(r11,extlb_level_exc) 144 lwz r12,0(r11) 145 mfspr r10,SPRN_SPRG_TLB_EXFRAME 146 sub r10,r10,r12 147 mtspr SPRN_SPRG_TLB_EXFRAME,r10 148 149 /* 150 * It's possible that the special level exception interrupted a 151 * TLB miss handler, and inserted the same entry that the 152 * interrupted handler was about to insert. On CPUs without TLB 153 * write conditional, this can result in a duplicate TLB entry. 154 * Wipe all non-bolted entries to be safe. 155 * 156 * Note that this doesn't protect against any TLB misses 157 * we may take accessing the stack from here to the end of 158 * the special level exception. It's not clear how we can 159 * reasonably protect against that, but only CPUs with 160 * neither TLB write conditional nor bolted kernel memory 161 * are affected. Do any such CPUs even exist? 162 */ 163 PPC_TLBILX_ALL(0,R0) 164 165 REST_NVGPRS(r1) 166 167 SPECIAL_EXC_LOAD(r10,SRR0) 168 mtspr SPRN_SRR0,r10 169 SPECIAL_EXC_LOAD(r10,SRR1) 170 mtspr SPRN_SRR1,r10 171 SPECIAL_EXC_LOAD(r10,SPRG_GEN) 172 mtspr SPRN_SPRG_GEN_SCRATCH,r10 173 SPECIAL_EXC_LOAD(r10,SPRG_TLB) 174 mtspr SPRN_SPRG_TLB_SCRATCH,r10 175 SPECIAL_EXC_LOAD(r10,MAS0) 176 mtspr SPRN_MAS0,r10 177 SPECIAL_EXC_LOAD(r10,MAS1) 178 mtspr SPRN_MAS1,r10 179 SPECIAL_EXC_LOAD(r10,MAS2) 180 mtspr SPRN_MAS2,r10 181 SPECIAL_EXC_LOAD(r10,MAS3) 182 mtspr SPRN_MAS3,r10 183 SPECIAL_EXC_LOAD(r10,MAS6) 184 mtspr SPRN_MAS6,r10 185 SPECIAL_EXC_LOAD(r10,MAS7) 186 mtspr SPRN_MAS7,r10 187BEGIN_FTR_SECTION 188 SPECIAL_EXC_LOAD(r10,MAS5) 189 mtspr SPRN_MAS5,r10 190 SPECIAL_EXC_LOAD(r10,MAS8) 191 mtspr SPRN_MAS8,r10 192END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 193 194 SPECIAL_EXC_LOAD(r10,DEAR) 195 mtspr SPRN_DEAR,r10 196 SPECIAL_EXC_LOAD(r10,ESR) 197 mtspr SPRN_ESR,r10 198 199 stdcx. r0,0,r1 /* to clear the reservation */ 200 201 REST_GPRS(2, 9, r1) 202 203 ld r10,_CTR(r1) 204 ld r11,_XER(r1) 205 mtctr r10 206 mtxer r11 207 208 blr 209 210.macro ret_from_level srr0 srr1 paca_ex scratch 211 bl ret_from_level_except 212 213 ld r10,_LINK(r1) 214 ld r11,_CCR(r1) 215 ld r0,GPR13(r1) 216 mtlr r10 217 mtcr r11 218 219 REST_GPRS(10, 12, r1) 220 mtspr \scratch,r0 221 222 std r10,\paca_ex+EX_R10(r13); 223 std r11,\paca_ex+EX_R11(r13); 224 ld r10,_NIP(r1) 225 ld r11,_MSR(r1) 226 REST_GPR(0, r1) 227 REST_GPR(1, r1) 228 mtspr \srr0,r10 229 mtspr \srr1,r11 230 ld r10,\paca_ex+EX_R10(r13) 231 ld r11,\paca_ex+EX_R11(r13) 232 mfspr r13,\scratch 233.endm 234 235ret_from_crit_except: 236 ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH 237 rfci 238 239ret_from_mc_except: 240 ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH 241 rfmci 242 243/* Exception prolog code for all exceptions */ 244#define EXCEPTION_PROLOG(n, intnum, type, addition) \ 245 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \ 246 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \ 247 std r10,PACA_EX##type+EX_R10(r13); \ 248 std r11,PACA_EX##type+EX_R11(r13); \ 249 mfcr r10; /* save CR */ \ 250 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \ 251 DO_KVM intnum,SPRN_##type##_SRR1; /* KVM hook */ \ 252 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \ 253 addition; /* additional code for that exc. */ \ 254 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \ 255 type##_SET_KSTACK; /* get special stack if necessary */\ 256 andi. r10,r11,MSR_PR; /* save stack pointer */ \ 257 beq 1f; /* branch around if supervisor */ \ 258 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\ 2591: type##_BTB_FLUSH \ 260 cmpdi cr1,r1,0; /* check if SP makes sense */ \ 261 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \ 262 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */ 263 264/* Exception type-specific macros */ 265#define GEN_SET_KSTACK \ 266 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ 267#define SPRN_GEN_SRR0 SPRN_SRR0 268#define SPRN_GEN_SRR1 SPRN_SRR1 269 270#define GDBELL_SET_KSTACK GEN_SET_KSTACK 271#define SPRN_GDBELL_SRR0 SPRN_GSRR0 272#define SPRN_GDBELL_SRR1 SPRN_GSRR1 273 274#define CRIT_SET_KSTACK \ 275 ld r1,PACA_CRIT_STACK(r13); \ 276 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 277#define SPRN_CRIT_SRR0 SPRN_CSRR0 278#define SPRN_CRIT_SRR1 SPRN_CSRR1 279 280#define DBG_SET_KSTACK \ 281 ld r1,PACA_DBG_STACK(r13); \ 282 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 283#define SPRN_DBG_SRR0 SPRN_DSRR0 284#define SPRN_DBG_SRR1 SPRN_DSRR1 285 286#define MC_SET_KSTACK \ 287 ld r1,PACA_MC_STACK(r13); \ 288 subi r1,r1,SPECIAL_EXC_FRAME_SIZE 289#define SPRN_MC_SRR0 SPRN_MCSRR0 290#define SPRN_MC_SRR1 SPRN_MCSRR1 291 292#define GEN_BTB_FLUSH \ 293 START_BTB_FLUSH_SECTION \ 294 beq 1f; \ 295 BTB_FLUSH(r10) \ 296 1: \ 297 END_BTB_FLUSH_SECTION 298 299#define CRIT_BTB_FLUSH \ 300 START_BTB_FLUSH_SECTION \ 301 BTB_FLUSH(r10) \ 302 END_BTB_FLUSH_SECTION 303 304#define DBG_BTB_FLUSH CRIT_BTB_FLUSH 305#define MC_BTB_FLUSH CRIT_BTB_FLUSH 306#define GDBELL_BTB_FLUSH GEN_BTB_FLUSH 307 308#define NORMAL_EXCEPTION_PROLOG(n, intnum, addition) \ 309 EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n)) 310 311#define CRIT_EXCEPTION_PROLOG(n, intnum, addition) \ 312 EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n)) 313 314#define DBG_EXCEPTION_PROLOG(n, intnum, addition) \ 315 EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n)) 316 317#define MC_EXCEPTION_PROLOG(n, intnum, addition) \ 318 EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n)) 319 320#define GDBELL_EXCEPTION_PROLOG(n, intnum, addition) \ 321 EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n)) 322 323/* Variants of the "addition" argument for the prolog 324 */ 325#define PROLOG_ADDITION_NONE_GEN(n) 326#define PROLOG_ADDITION_NONE_GDBELL(n) 327#define PROLOG_ADDITION_NONE_CRIT(n) 328#define PROLOG_ADDITION_NONE_DBG(n) 329#define PROLOG_ADDITION_NONE_MC(n) 330 331#define PROLOG_ADDITION_MASKABLE_GEN(n) \ 332 lbz r10,PACAIRQSOFTMASK(r13); /* are irqs soft-masked? */ \ 333 andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \ 334 bne masked_interrupt_book3e_##n 335 336/* 337 * Additional regs must be re-loaded from paca before EXCEPTION_COMMON* is 338 * called, because that does SAVE_NVGPRS which must see the original register 339 * values, otherwise the scratch values might be restored when exiting the 340 * interrupt. 341 */ 342#define PROLOG_ADDITION_2REGS_GEN(n) \ 343 std r14,PACA_EXGEN+EX_R14(r13); \ 344 std r15,PACA_EXGEN+EX_R15(r13) 345 346#define PROLOG_ADDITION_1REG_GEN(n) \ 347 std r14,PACA_EXGEN+EX_R14(r13); 348 349#define PROLOG_ADDITION_2REGS_CRIT(n) \ 350 std r14,PACA_EXCRIT+EX_R14(r13); \ 351 std r15,PACA_EXCRIT+EX_R15(r13) 352 353#define PROLOG_ADDITION_2REGS_DBG(n) \ 354 std r14,PACA_EXDBG+EX_R14(r13); \ 355 std r15,PACA_EXDBG+EX_R15(r13) 356 357#define PROLOG_ADDITION_2REGS_MC(n) \ 358 std r14,PACA_EXMC+EX_R14(r13); \ 359 std r15,PACA_EXMC+EX_R15(r13) 360 361 362/* Core exception code for all exceptions except TLB misses. */ 363#define EXCEPTION_COMMON_LVL(n, scratch, excf) \ 364exc_##n##_common: \ 365 SAVE_GPR(0, r1); /* save r0 in stackframe */ \ 366 SAVE_GPRS(2, 9, r1); /* save r2 - r9 in stackframe */ \ 367 std r10,_NIP(r1); /* save SRR0 to stackframe */ \ 368 std r11,_MSR(r1); /* save SRR1 to stackframe */ \ 369 beq 2f; /* if from kernel mode */ \ 3702: ld r3,excf+EX_R10(r13); /* get back r10 */ \ 371 ld r4,excf+EX_R11(r13); /* get back r11 */ \ 372 mfspr r5,scratch; /* get back r13 */ \ 373 SAVE_GPR(12, r1); /* save r12 in stackframe */ \ 374 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 375 mflr r6; /* save LR in stackframe */ \ 376 mfctr r7; /* save CTR in stackframe */ \ 377 mfspr r8,SPRN_XER; /* save XER in stackframe */ \ 378 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \ 379 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ 380 lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \ 381 ld r12,exception_marker@toc(r2); \ 382 ZEROIZE_GPR(0); \ 383 std r3,GPR10(r1); /* save r10 to stackframe */ \ 384 std r4,GPR11(r1); /* save r11 to stackframe */ \ 385 std r5,GPR13(r1); /* save it to stackframe */ \ 386 std r6,_LINK(r1); \ 387 std r7,_CTR(r1); \ 388 std r8,_XER(r1); \ 389 li r3,(n); /* regs.trap vector */ \ 390 std r9,0(r1); /* store stack frame back link */ \ 391 std r10,_CCR(r1); /* store orig CR in stackframe */ \ 392 std r9,GPR1(r1); /* store stack frame back link */ \ 393 std r11,SOFTE(r1); /* and save it to stackframe */ \ 394 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \ 395 std r3,_TRAP(r1); /* set trap number */ \ 396 std r0,RESULT(r1); /* clear regs->result */ \ 397 SAVE_NVGPRS(r1); 398 399#define EXCEPTION_COMMON(n) \ 400 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN) 401#define EXCEPTION_COMMON_CRIT(n) \ 402 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT) 403#define EXCEPTION_COMMON_MC(n) \ 404 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC) 405#define EXCEPTION_COMMON_DBG(n) \ 406 EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG) 407 408/* XXX FIXME: Restore r14/r15 when necessary */ 409#define BAD_STACK_TRAMPOLINE(n) \ 410exc_##n##_bad_stack: \ 411 li r1,(n); /* get exception number */ \ 412 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \ 413 b bad_stack_book3e; /* bad stack error */ 414 415/* WARNING: If you change the layout of this stub, make sure you check 416 * the debug exception handler which handles single stepping 417 * into exceptions from userspace, and the MM code in 418 * arch/powerpc/mm/tlb_nohash.c which patches the branch here 419 * and would need to be updated if that branch is moved 420 */ 421#define EXCEPTION_STUB(loc, label) \ 422 . = interrupt_base_book3e + loc; \ 423 nop; /* To make debug interrupts happy */ \ 424 b exc_##label##_book3e; 425 426#define ACK_NONE(r) 427#define ACK_DEC(r) \ 428 lis r,TSR_DIS@h; \ 429 mtspr SPRN_TSR,r 430#define ACK_FIT(r) \ 431 lis r,TSR_FIS@h; \ 432 mtspr SPRN_TSR,r 433 434/* Used by asynchronous interrupt that may happen in the idle loop. 435 * 436 * This check if the thread was in the idle loop, and if yes, returns 437 * to the caller rather than the PC. This is to avoid a race if 438 * interrupts happen before the wait instruction. 439 */ 440#define CHECK_NAPPING() \ 441 ld r11, PACA_THREAD_INFO(r13); \ 442 ld r10,TI_LOCAL_FLAGS(r11); \ 443 andi. r9,r10,_TLF_NAPPING; \ 444 beq+ 1f; \ 445 ld r8,_LINK(r1); \ 446 rlwinm r7,r10,0,~_TLF_NAPPING; \ 447 std r8,_NIP(r1); \ 448 std r7,TI_LOCAL_FLAGS(r11); \ 4491: 450 451 452#define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack) \ 453 START_EXCEPTION(label); \ 454 NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\ 455 EXCEPTION_COMMON(trapnum) \ 456 ack(r8); \ 457 CHECK_NAPPING(); \ 458 addi r3,r1,STACK_FRAME_OVERHEAD; \ 459 bl hdlr; \ 460 b interrupt_return 461 462/* This value is used to mark exception frames on the stack. */ 463 .section ".toc","aw" 464exception_marker: 465 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER 466 467 468/* 469 * And here we have the exception vectors ! 470 */ 471 472 .text 473 .balign 0x1000 474 .globl interrupt_base_book3e 475interrupt_base_book3e: /* fake trap */ 476 EXCEPTION_STUB(0x000, machine_check) 477 EXCEPTION_STUB(0x020, critical_input) /* 0x0100 */ 478 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 479 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */ 480 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */ 481 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */ 482 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */ 483 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */ 484 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */ 485 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */ 486 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */ 487 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */ 488 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */ 489 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 490 EXCEPTION_STUB(0x1c0, data_tlb_miss) 491 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 492 EXCEPTION_STUB(0x200, altivec_unavailable) 493 EXCEPTION_STUB(0x220, altivec_assist) 494 EXCEPTION_STUB(0x260, perfmon) 495 EXCEPTION_STUB(0x280, doorbell) 496 EXCEPTION_STUB(0x2a0, doorbell_crit) 497 EXCEPTION_STUB(0x2c0, guest_doorbell) 498 EXCEPTION_STUB(0x2e0, guest_doorbell_crit) 499 EXCEPTION_STUB(0x300, hypercall) 500 EXCEPTION_STUB(0x320, ehpriv) 501 EXCEPTION_STUB(0x340, lrat_error) 502 503 .globl __end_interrupts 504__end_interrupts: 505 506/* Critical Input Interrupt */ 507 START_EXCEPTION(critical_input); 508 CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL, 509 PROLOG_ADDITION_NONE) 510 EXCEPTION_COMMON_CRIT(0x100) 511 bl special_reg_save 512 CHECK_NAPPING(); 513 addi r3,r1,STACK_FRAME_OVERHEAD 514 bl unknown_nmi_exception 515 b ret_from_crit_except 516 517/* Machine Check Interrupt */ 518 START_EXCEPTION(machine_check); 519 MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK, 520 PROLOG_ADDITION_NONE) 521 EXCEPTION_COMMON_MC(0x000) 522 bl special_reg_save 523 CHECK_NAPPING(); 524 addi r3,r1,STACK_FRAME_OVERHEAD 525 bl machine_check_exception 526 b ret_from_mc_except 527 528/* Data Storage Interrupt */ 529 START_EXCEPTION(data_storage) 530 NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE, 531 PROLOG_ADDITION_2REGS) 532 mfspr r14,SPRN_DEAR 533 mfspr r15,SPRN_ESR 534 std r14,_DEAR(r1) 535 std r15,_ESR(r1) 536 ld r14,PACA_EXGEN+EX_R14(r13) 537 ld r15,PACA_EXGEN+EX_R15(r13) 538 EXCEPTION_COMMON(0x300) 539 b storage_fault_common 540 541/* Instruction Storage Interrupt */ 542 START_EXCEPTION(instruction_storage); 543 NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE, 544 PROLOG_ADDITION_2REGS) 545 li r15,0 546 mr r14,r10 547 std r14,_DEAR(r1) 548 std r15,_ESR(r1) 549 ld r14,PACA_EXGEN+EX_R14(r13) 550 ld r15,PACA_EXGEN+EX_R15(r13) 551 EXCEPTION_COMMON(0x400) 552 b storage_fault_common 553 554/* External Input Interrupt */ 555 MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL, 556 external_input, do_IRQ, ACK_NONE) 557 558/* Alignment */ 559 START_EXCEPTION(alignment); 560 NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT, 561 PROLOG_ADDITION_2REGS) 562 mfspr r14,SPRN_DEAR 563 mfspr r15,SPRN_ESR 564 std r14,_DEAR(r1) 565 std r15,_ESR(r1) 566 ld r14,PACA_EXGEN+EX_R14(r13) 567 ld r15,PACA_EXGEN+EX_R15(r13) 568 EXCEPTION_COMMON(0x600) 569 b alignment_more /* no room, go out of line */ 570 571/* Program Interrupt */ 572 START_EXCEPTION(program); 573 NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM, 574 PROLOG_ADDITION_1REG) 575 mfspr r14,SPRN_ESR 576 std r14,_ESR(r1) 577 ld r14,PACA_EXGEN+EX_R14(r13) 578 EXCEPTION_COMMON(0x700) 579 addi r3,r1,STACK_FRAME_OVERHEAD 580 bl program_check_exception 581 REST_NVGPRS(r1) 582 b interrupt_return 583 584/* Floating Point Unavailable Interrupt */ 585 START_EXCEPTION(fp_unavailable); 586 NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL, 587 PROLOG_ADDITION_NONE) 588 /* we can probably do a shorter exception entry for that one... */ 589 EXCEPTION_COMMON(0x800) 590 ld r12,_MSR(r1) 591 andi. r0,r12,MSR_PR; 592 beq- 1f 593 bl load_up_fpu 594 b fast_interrupt_return 5951: addi r3,r1,STACK_FRAME_OVERHEAD 596 bl kernel_fp_unavailable_exception 597 b interrupt_return 598 599/* Altivec Unavailable Interrupt */ 600 START_EXCEPTION(altivec_unavailable); 601 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, 602 PROLOG_ADDITION_NONE) 603 /* we can probably do a shorter exception entry for that one... */ 604 EXCEPTION_COMMON(0x200) 605#ifdef CONFIG_ALTIVEC 606BEGIN_FTR_SECTION 607 ld r12,_MSR(r1) 608 andi. r0,r12,MSR_PR; 609 beq- 1f 610 bl load_up_altivec 611 b fast_interrupt_return 6121: 613END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 614#endif 615 addi r3,r1,STACK_FRAME_OVERHEAD 616 bl altivec_unavailable_exception 617 b interrupt_return 618 619/* AltiVec Assist */ 620 START_EXCEPTION(altivec_assist); 621 NORMAL_EXCEPTION_PROLOG(0x220, 622 BOOKE_INTERRUPT_ALTIVEC_ASSIST, 623 PROLOG_ADDITION_NONE) 624 EXCEPTION_COMMON(0x220) 625 addi r3,r1,STACK_FRAME_OVERHEAD 626#ifdef CONFIG_ALTIVEC 627BEGIN_FTR_SECTION 628 bl altivec_assist_exception 629END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 630 REST_NVGPRS(r1) 631#else 632 bl unknown_exception 633#endif 634 b interrupt_return 635 636 637/* Decrementer Interrupt */ 638 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, 639 decrementer, timer_interrupt, ACK_DEC) 640 641/* Fixed Interval Timer Interrupt */ 642 MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT, 643 fixed_interval, unknown_exception, ACK_FIT) 644 645/* Watchdog Timer Interrupt */ 646 START_EXCEPTION(watchdog); 647 CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG, 648 PROLOG_ADDITION_NONE) 649 EXCEPTION_COMMON_CRIT(0x9f0) 650 bl special_reg_save 651 CHECK_NAPPING(); 652 addi r3,r1,STACK_FRAME_OVERHEAD 653#ifdef CONFIG_BOOKE_WDT 654 bl WatchdogException 655#else 656 bl unknown_nmi_exception 657#endif 658 b ret_from_crit_except 659 660/* System Call Interrupt */ 661 START_EXCEPTION(system_call) 662 mr r9,r13 /* keep a copy of userland r13 */ 663 mfspr r11,SPRN_SRR0 /* get return address */ 664 mfspr r12,SPRN_SRR1 /* get previous MSR */ 665 mfspr r13,SPRN_SPRG_PACA /* get our PACA */ 666 b system_call_common 667 668/* Auxiliary Processor Unavailable Interrupt */ 669 START_EXCEPTION(ap_unavailable); 670 NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL, 671 PROLOG_ADDITION_NONE) 672 EXCEPTION_COMMON(0xf20) 673 addi r3,r1,STACK_FRAME_OVERHEAD 674 bl unknown_exception 675 b interrupt_return 676 677/* Debug exception as a critical interrupt*/ 678 START_EXCEPTION(debug_crit); 679 CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 680 PROLOG_ADDITION_2REGS) 681 682 /* 683 * If there is a single step or branch-taken exception in an 684 * exception entry sequence, it was probably meant to apply to 685 * the code where the exception occurred (since exception entry 686 * doesn't turn off DE automatically). We simulate the effect 687 * of turning off DE on entry to an exception handler by turning 688 * off DE in the CSRR1 value and clearing the debug status. 689 */ 690 691 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 692 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 693 beq+ 1f 694 695#ifdef CONFIG_RELOCATABLE 696 ld r15,PACATOC(r13) 697 ld r14,interrupt_base_book3e@got(r15) 698 ld r15,__end_interrupts@got(r15) 699 cmpld cr0,r10,r14 700 cmpld cr1,r10,r15 701#else 702 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e) 703 cmpld cr0, r10, r14 704 LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts) 705 cmpld cr1, r10, r14 706#endif 707 blt+ cr0,1f 708 bge+ cr1,1f 709 710 /* here it looks like we got an inappropriate debug exception. */ 711 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 712 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */ 713 mtspr SPRN_DBSR,r14 714 mtspr SPRN_CSRR1,r11 715 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */ 716 ld r1,PACA_EXCRIT+EX_R1(r13) 717 ld r14,PACA_EXCRIT+EX_R14(r13) 718 ld r15,PACA_EXCRIT+EX_R15(r13) 719 mtcr r10 720 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */ 721 ld r11,PACA_EXCRIT+EX_R11(r13) 722 mfspr r13,SPRN_SPRG_CRIT_SCRATCH 723 rfci 724 725 /* Normal debug exception */ 726 /* XXX We only handle coming from userspace for now since we can't 727 * quite save properly an interrupted kernel state yet 728 */ 7291: andi. r14,r11,MSR_PR; /* check for userspace again */ 730 beq kernel_dbg_exc; /* if from kernel mode */ 731 732 /* Now we mash up things to make it look like we are coming on a 733 * normal exception 734 */ 735 mfspr r14,SPRN_DBSR 736 std r14,_DSISR(r1) 737 ld r14,PACA_EXCRIT+EX_R14(r13) 738 ld r15,PACA_EXCRIT+EX_R15(r13) 739 EXCEPTION_COMMON_CRIT(0xd00) 740 addi r3,r1,STACK_FRAME_OVERHEAD 741 bl DebugException 742 REST_NVGPRS(r1) 743 b interrupt_return 744 745kernel_dbg_exc: 746 b . /* NYI */ 747 748/* Debug exception as a debug interrupt*/ 749 START_EXCEPTION(debug_debug); 750 DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG, 751 PROLOG_ADDITION_2REGS) 752 753 /* 754 * If there is a single step or branch-taken exception in an 755 * exception entry sequence, it was probably meant to apply to 756 * the code where the exception occurred (since exception entry 757 * doesn't turn off DE automatically). We simulate the effect 758 * of turning off DE on entry to an exception handler by turning 759 * off DE in the DSRR1 value and clearing the debug status. 760 */ 761 762 mfspr r14,SPRN_DBSR /* check single-step/branch taken */ 763 andis. r15,r14,(DBSR_IC|DBSR_BT)@h 764 beq+ 1f 765 766#ifdef CONFIG_RELOCATABLE 767 ld r15,PACATOC(r13) 768 ld r14,interrupt_base_book3e@got(r15) 769 ld r15,__end_interrupts@got(r15) 770 cmpld cr0,r10,r14 771 cmpld cr1,r10,r15 772#else 773 LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e) 774 cmpld cr0, r10, r14 775 LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts) 776 cmpld cr1, r10, r14 777#endif 778 blt+ cr0,1f 779 bge+ cr1,1f 780 781 /* here it looks like we got an inappropriate debug exception. */ 782 lis r14,(DBSR_IC|DBSR_BT)@h /* clear the event */ 783 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */ 784 mtspr SPRN_DBSR,r14 785 mtspr SPRN_DSRR1,r11 786 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */ 787 ld r1,PACA_EXDBG+EX_R1(r13) 788 ld r14,PACA_EXDBG+EX_R14(r13) 789 ld r15,PACA_EXDBG+EX_R15(r13) 790 mtcr r10 791 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */ 792 ld r11,PACA_EXDBG+EX_R11(r13) 793 mfspr r13,SPRN_SPRG_DBG_SCRATCH 794 rfdi 795 796 /* Normal debug exception */ 797 /* XXX We only handle coming from userspace for now since we can't 798 * quite save properly an interrupted kernel state yet 799 */ 8001: andi. r14,r11,MSR_PR; /* check for userspace again */ 801 beq kernel_dbg_exc; /* if from kernel mode */ 802 803 /* Now we mash up things to make it look like we are coming on a 804 * normal exception 805 */ 806 mfspr r14,SPRN_DBSR 807 std r14,_DSISR(r1) 808 ld r14,PACA_EXDBG+EX_R14(r13) 809 ld r15,PACA_EXDBG+EX_R15(r13) 810 EXCEPTION_COMMON_DBG(0xd08) 811 addi r3,r1,STACK_FRAME_OVERHEAD 812 bl DebugException 813 REST_NVGPRS(r1) 814 b interrupt_return 815 816 START_EXCEPTION(perfmon); 817 NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR, 818 PROLOG_ADDITION_NONE) 819 EXCEPTION_COMMON(0x260) 820 CHECK_NAPPING() 821 addi r3,r1,STACK_FRAME_OVERHEAD 822 bl performance_monitor_exception 823 b interrupt_return 824 825/* Doorbell interrupt */ 826 MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL, 827 doorbell, doorbell_exception, ACK_NONE) 828 829/* Doorbell critical Interrupt */ 830 START_EXCEPTION(doorbell_crit); 831 CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL, 832 PROLOG_ADDITION_NONE) 833 EXCEPTION_COMMON_CRIT(0x2a0) 834 bl special_reg_save 835 CHECK_NAPPING(); 836 addi r3,r1,STACK_FRAME_OVERHEAD 837 bl unknown_nmi_exception 838 b ret_from_crit_except 839 840/* 841 * Guest doorbell interrupt 842 * This general exception use GSRRx save/restore registers 843 */ 844 START_EXCEPTION(guest_doorbell); 845 GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL, 846 PROLOG_ADDITION_NONE) 847 EXCEPTION_COMMON(0x2c0) 848 addi r3,r1,STACK_FRAME_OVERHEAD 849 bl unknown_exception 850 b interrupt_return 851 852/* Guest Doorbell critical Interrupt */ 853 START_EXCEPTION(guest_doorbell_crit); 854 CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT, 855 PROLOG_ADDITION_NONE) 856 EXCEPTION_COMMON_CRIT(0x2e0) 857 bl special_reg_save 858 CHECK_NAPPING(); 859 addi r3,r1,STACK_FRAME_OVERHEAD 860 bl unknown_nmi_exception 861 b ret_from_crit_except 862 863/* Hypervisor call */ 864 START_EXCEPTION(hypercall); 865 NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL, 866 PROLOG_ADDITION_NONE) 867 EXCEPTION_COMMON(0x310) 868 addi r3,r1,STACK_FRAME_OVERHEAD 869 bl unknown_exception 870 b interrupt_return 871 872/* Embedded Hypervisor priviledged */ 873 START_EXCEPTION(ehpriv); 874 NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV, 875 PROLOG_ADDITION_NONE) 876 EXCEPTION_COMMON(0x320) 877 addi r3,r1,STACK_FRAME_OVERHEAD 878 bl unknown_exception 879 b interrupt_return 880 881/* LRAT Error interrupt */ 882 START_EXCEPTION(lrat_error); 883 NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR, 884 PROLOG_ADDITION_NONE) 885 EXCEPTION_COMMON(0x340) 886 addi r3,r1,STACK_FRAME_OVERHEAD 887 bl unknown_exception 888 b interrupt_return 889 890.macro SEARCH_RESTART_TABLE 891#ifdef CONFIG_RELOCATABLE 892 ld r11,PACATOC(r13) 893 ld r14,__start___restart_table@got(r11) 894 ld r15,__stop___restart_table@got(r11) 895#else 896 LOAD_REG_IMMEDIATE_SYM(r14, r11, __start___restart_table) 897 LOAD_REG_IMMEDIATE_SYM(r15, r11, __stop___restart_table) 898#endif 899300: 900 cmpd r14,r15 901 beq 302f 902 ld r11,0(r14) 903 cmpld r10,r11 904 blt 301f 905 ld r11,8(r14) 906 cmpld r10,r11 907 bge 301f 908 ld r11,16(r14) 909 b 303f 910301: 911 addi r14,r14,24 912 b 300b 913302: 914 li r11,0 915303: 916.endm 917 918/* 919 * An interrupt came in while soft-disabled; We mark paca->irq_happened 920 * accordingly and if the interrupt is level sensitive, we hard disable 921 * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so 922 * keep these in synch. 923 */ 924 925.macro masked_interrupt_book3e paca_irq full_mask 926 std r14,PACA_EXGEN+EX_R14(r13) 927 std r15,PACA_EXGEN+EX_R15(r13) 928 929 lbz r10,PACAIRQHAPPENED(r13) 930 .if \full_mask == 1 931 ori r10,r10,\paca_irq | PACA_IRQ_HARD_DIS 932 .else 933 ori r10,r10,\paca_irq 934 .endif 935 stb r10,PACAIRQHAPPENED(r13) 936 937 .if \full_mask == 1 938 xori r11,r11,MSR_EE /* clear MSR_EE */ 939 mtspr SPRN_SRR1,r11 940 .endif 941 942 mfspr r10,SPRN_SRR0 943 SEARCH_RESTART_TABLE 944 cmpdi r11,0 945 beq 1f 946 mtspr SPRN_SRR0,r11 /* return to restart address */ 9471: 948 949 lwz r11,PACA_EXGEN+EX_CR(r13) 950 mtcr r11 951 ld r10,PACA_EXGEN+EX_R10(r13) 952 ld r11,PACA_EXGEN+EX_R11(r13) 953 ld r14,PACA_EXGEN+EX_R14(r13) 954 ld r15,PACA_EXGEN+EX_R15(r13) 955 mfspr r13,SPRN_SPRG_GEN_SCRATCH 956 rfi 957 b . 958.endm 959 960masked_interrupt_book3e_0x500: 961 masked_interrupt_book3e PACA_IRQ_EE 1 962 963masked_interrupt_book3e_0x900: 964 ACK_DEC(r10); 965 masked_interrupt_book3e PACA_IRQ_DEC 0 966 967masked_interrupt_book3e_0x980: 968 ACK_FIT(r10); 969 masked_interrupt_book3e PACA_IRQ_DEC 0 970 971masked_interrupt_book3e_0x280: 972masked_interrupt_book3e_0x2c0: 973 masked_interrupt_book3e PACA_IRQ_DBELL 0 974 975/* 976 * This is called from 0x300 and 0x400 handlers after the prologs with 977 * r14 and r15 containing the fault address and error code, with the 978 * original values stashed away in the PACA 979 */ 980storage_fault_common: 981 addi r3,r1,STACK_FRAME_OVERHEAD 982 bl do_page_fault 983 b interrupt_return 984 985/* 986 * Alignment exception doesn't fit entirely in the 0x100 bytes so it 987 * continues here. 988 */ 989alignment_more: 990 addi r3,r1,STACK_FRAME_OVERHEAD 991 bl alignment_exception 992 REST_NVGPRS(r1) 993 b interrupt_return 994 995/* 996 * Trampolines used when spotting a bad kernel stack pointer in 997 * the exception entry code. 998 * 999 * TODO: move some bits like SRR0 read to trampoline, pass PACA 1000 * index around, etc... to handle crit & mcheck 1001 */ 1002BAD_STACK_TRAMPOLINE(0x000) 1003BAD_STACK_TRAMPOLINE(0x100) 1004BAD_STACK_TRAMPOLINE(0x200) 1005BAD_STACK_TRAMPOLINE(0x220) 1006BAD_STACK_TRAMPOLINE(0x260) 1007BAD_STACK_TRAMPOLINE(0x280) 1008BAD_STACK_TRAMPOLINE(0x2a0) 1009BAD_STACK_TRAMPOLINE(0x2c0) 1010BAD_STACK_TRAMPOLINE(0x2e0) 1011BAD_STACK_TRAMPOLINE(0x300) 1012BAD_STACK_TRAMPOLINE(0x310) 1013BAD_STACK_TRAMPOLINE(0x320) 1014BAD_STACK_TRAMPOLINE(0x340) 1015BAD_STACK_TRAMPOLINE(0x400) 1016BAD_STACK_TRAMPOLINE(0x500) 1017BAD_STACK_TRAMPOLINE(0x600) 1018BAD_STACK_TRAMPOLINE(0x700) 1019BAD_STACK_TRAMPOLINE(0x800) 1020BAD_STACK_TRAMPOLINE(0x900) 1021BAD_STACK_TRAMPOLINE(0x980) 1022BAD_STACK_TRAMPOLINE(0x9f0) 1023BAD_STACK_TRAMPOLINE(0xa00) 1024BAD_STACK_TRAMPOLINE(0xb00) 1025BAD_STACK_TRAMPOLINE(0xc00) 1026BAD_STACK_TRAMPOLINE(0xd00) 1027BAD_STACK_TRAMPOLINE(0xd08) 1028BAD_STACK_TRAMPOLINE(0xe00) 1029BAD_STACK_TRAMPOLINE(0xf00) 1030BAD_STACK_TRAMPOLINE(0xf20) 1031 1032 .globl bad_stack_book3e 1033bad_stack_book3e: 1034 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ 1035 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ 1036 ld r1,PACAEMERGSP(r13) 1037 subi r1,r1,64+INT_FRAME_SIZE 1038 std r10,_NIP(r1) 1039 std r11,_MSR(r1) 1040 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ 1041 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ 1042 std r10,GPR1(r1) 1043 std r11,_CCR(r1) 1044 mfspr r10,SPRN_DEAR 1045 mfspr r11,SPRN_ESR 1046 std r10,_DEAR(r1) 1047 std r11,_ESR(r1) 1048 SAVE_GPR(0, r1); /* save r0 in stackframe */ \ 1049 SAVE_GPRS(2, 9, r1); /* save r2 - r9 in stackframe */ \ 1050 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ 1051 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ 1052 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ 1053 std r3,GPR10(r1); /* save r10 to stackframe */ \ 1054 std r4,GPR11(r1); /* save r11 to stackframe */ \ 1055 SAVE_GPR(12, r1); /* save r12 in stackframe */ \ 1056 std r5,GPR13(r1); /* save it to stackframe */ \ 1057 mflr r10 1058 mfctr r11 1059 mfxer r12 1060 std r10,_LINK(r1) 1061 std r11,_CTR(r1) 1062 std r12,_XER(r1) 1063 SAVE_NVGPRS(r1) 1064 lhz r12,PACA_TRAP_SAVE(r13) 1065 std r12,_TRAP(r1) 1066 addi r11,r1,INT_FRAME_SIZE 1067 std r11,0(r1) 1068 ZEROIZE_GPR(12) 1069 std r12,0(r11) 1070 ld r2,PACATOC(r13) 10711: addi r3,r1,STACK_FRAME_OVERHEAD 1072 bl kernel_bad_stack 1073 b 1b 1074 1075/* 1076 * Setup the initial TLB for a core. This current implementation 1077 * assume that whatever we are running off will not conflict with 1078 * the new mapping at PAGE_OFFSET. 1079 */ 1080_GLOBAL(initial_tlb_book3e) 1081 1082 /* Look for the first TLB with IPROT set */ 1083 mfspr r4,SPRN_TLB0CFG 1084 andi. r3,r4,TLBnCFG_IPROT 1085 lis r3,MAS0_TLBSEL(0)@h 1086 bne found_iprot 1087 1088 mfspr r4,SPRN_TLB1CFG 1089 andi. r3,r4,TLBnCFG_IPROT 1090 lis r3,MAS0_TLBSEL(1)@h 1091 bne found_iprot 1092 1093 mfspr r4,SPRN_TLB2CFG 1094 andi. r3,r4,TLBnCFG_IPROT 1095 lis r3,MAS0_TLBSEL(2)@h 1096 bne found_iprot 1097 1098 lis r3,MAS0_TLBSEL(3)@h 1099 mfspr r4,SPRN_TLB3CFG 1100 /* fall through */ 1101 1102found_iprot: 1103 andi. r5,r4,TLBnCFG_HES 1104 bne have_hes 1105 1106 mflr r8 /* save LR */ 1107/* 1. Find the index of the entry we're executing in 1108 * 1109 * r3 = MAS0_TLBSEL (for the iprot array) 1110 * r4 = SPRN_TLBnCFG 1111 */ 1112 bcl 20,31,$+4 /* Find our address */ 1113invstr: mflr r6 /* Make it accessible */ 1114 mfmsr r7 1115 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ 1116 mfspr r7,SPRN_PID 1117 slwi r7,r7,16 1118 or r7,r7,r5 1119 mtspr SPRN_MAS6,r7 1120 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ 1121 1122 mfspr r3,SPRN_MAS0 1123 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ 1124 1125 mfspr r7,SPRN_MAS1 /* Insure IPROT set */ 1126 oris r7,r7,MAS1_IPROT@h 1127 mtspr SPRN_MAS1,r7 1128 tlbwe 1129 1130/* 2. Invalidate all entries except the entry we're executing in 1131 * 1132 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1133 * r4 = SPRN_TLBnCFG 1134 * r5 = ESEL of entry we are running in 1135 */ 1136 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ 1137 li r6,0 /* Set Entry counter to 0 */ 11381: mr r7,r3 /* Set MAS0(TLBSEL) */ 1139 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ 1140 mtspr SPRN_MAS0,r7 1141 tlbre 1142 mfspr r7,SPRN_MAS1 1143 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ 1144 cmpw r5,r6 1145 beq skpinv /* Dont update the current execution TLB */ 1146 mtspr SPRN_MAS1,r7 1147 tlbwe 1148 isync 1149skpinv: addi r6,r6,1 /* Increment */ 1150 cmpw r6,r4 /* Are we done? */ 1151 bne 1b /* If not, repeat */ 1152 1153 /* Invalidate all TLBs */ 1154 PPC_TLBILX_ALL(0,R0) 1155 sync 1156 isync 1157 1158/* 3. Setup a temp mapping and jump to it 1159 * 1160 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1161 * r5 = ESEL of entry we are running in 1162 */ 1163 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ 1164 addi r7,r7,0x1 1165 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ 1166 mtspr SPRN_MAS0,r4 1167 tlbre 1168 1169 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ 1170 mtspr SPRN_MAS0,r4 1171 1172 mfspr r7,SPRN_MAS1 1173 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ 1174 mtspr SPRN_MAS1,r6 1175 1176 tlbwe 1177 1178 mfmsr r6 1179 xori r6,r6,MSR_IS 1180 mtspr SPRN_SRR1,r6 1181 bcl 20,31,$+4 /* Find our address */ 11821: mflr r6 1183 addi r6,r6,(2f - 1b) 1184 mtspr SPRN_SRR0,r6 1185 rfi 11862: 1187 1188/* 4. Clear out PIDs & Search info 1189 * 1190 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1191 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1192 * r5 = MAS3 1193 */ 1194 li r6,0 1195 mtspr SPRN_MAS6,r6 1196 mtspr SPRN_PID,r6 1197 1198/* 5. Invalidate mapping we started in 1199 * 1200 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1201 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1202 * r5 = MAS3 1203 */ 1204 mtspr SPRN_MAS0,r3 1205 tlbre 1206 mfspr r6,SPRN_MAS1 1207 rlwinm r6,r6,0,2,31 /* clear IPROT and VALID */ 1208 mtspr SPRN_MAS1,r6 1209 tlbwe 1210 sync 1211 isync 1212 1213/* 6. Setup KERNELBASE mapping in TLB[0] 1214 * 1215 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in 1216 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1217 * r5 = MAS3 1218 */ 1219 rlwinm r3,r3,0,16,3 /* clear ESEL */ 1220 mtspr SPRN_MAS0,r3 1221 lis r6,(MAS1_VALID|MAS1_IPROT)@h 1222 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l 1223 mtspr SPRN_MAS1,r6 1224 1225 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | MAS2_M_IF_NEEDED) 1226 mtspr SPRN_MAS2,r6 1227 1228 rlwinm r5,r5,0,0,25 1229 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX 1230 mtspr SPRN_MAS3,r5 1231 li r5,-1 1232 rlwinm r5,r5,0,0,25 1233 1234 tlbwe 1235 1236/* 7. Jump to KERNELBASE mapping 1237 * 1238 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping 1239 */ 1240 /* Now we branch the new virtual address mapped by this entry */ 1241 bcl 20,31,$+4 /* Find our address */ 12421: mflr r6 1243 addi r6,r6,(2f - 1b) 1244 tovirt(r6,r6) 1245 lis r7,MSR_KERNEL@h 1246 ori r7,r7,MSR_KERNEL@l 1247 mtspr SPRN_SRR0,r6 1248 mtspr SPRN_SRR1,r7 1249 rfi /* start execution out of TLB1[0] entry */ 12502: 1251 1252/* 8. Clear out the temp mapping 1253 * 1254 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in 1255 */ 1256 mtspr SPRN_MAS0,r4 1257 tlbre 1258 mfspr r5,SPRN_MAS1 1259 rlwinm r5,r5,0,2,31 /* clear IPROT and VALID */ 1260 mtspr SPRN_MAS1,r5 1261 tlbwe 1262 sync 1263 isync 1264 1265 /* We translate LR and return */ 1266 tovirt(r8,r8) 1267 mtlr r8 1268 blr 1269 1270have_hes: 1271 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the 1272 * kernel linear mapping. We also set MAS8 once for all here though 1273 * that will have to be made dependent on whether we are running under 1274 * a hypervisor I suppose. 1275 */ 1276 1277 /* BEWARE, MAGIC 1278 * This code is called as an ordinary function on the boot CPU. But to 1279 * avoid duplication, this code is also used in SCOM bringup of 1280 * secondary CPUs. We read the code between the initial_tlb_code_start 1281 * and initial_tlb_code_end labels one instruction at a time and RAM it 1282 * into the new core via SCOM. That doesn't process branches, so there 1283 * must be none between those two labels. It also means if this code 1284 * ever takes any parameters, the SCOM code must also be updated to 1285 * provide them. 1286 */ 1287 .globl a2_tlbinit_code_start 1288a2_tlbinit_code_start: 1289 1290 ori r11,r3,MAS0_WQ_ALLWAYS 1291 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ 1292 mtspr SPRN_MAS0,r11 1293 lis r3,(MAS1_VALID | MAS1_IPROT)@h 1294 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT 1295 mtspr SPRN_MAS1,r3 1296 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) 1297 mtspr SPRN_MAS2,r3 1298 li r3,MAS3_SR | MAS3_SW | MAS3_SX 1299 mtspr SPRN_MAS7_MAS3,r3 1300 li r3,0 1301 mtspr SPRN_MAS8,r3 1302 1303 /* Write the TLB entry */ 1304 tlbwe 1305 1306 .globl a2_tlbinit_after_linear_map 1307a2_tlbinit_after_linear_map: 1308 1309 /* Now we branch the new virtual address mapped by this entry */ 1310#ifdef CONFIG_RELOCATABLE 1311 ld r5,PACATOC(r13) 1312 ld r3,1f@got(r5) 1313#else 1314 LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f) 1315#endif 1316 mtctr r3 1317 bctr 1318 13191: /* We are now running at PAGE_OFFSET, clean the TLB of everything 1320 * else (including IPROTed things left by firmware) 1321 * r4 = TLBnCFG 1322 * r3 = current address (more or less) 1323 */ 1324 1325 li r5,0 1326 mtspr SPRN_MAS6,r5 1327 tlbsx 0,r3 1328 1329 rlwinm r9,r4,0,TLBnCFG_N_ENTRY 1330 rlwinm r10,r4,8,0xff 1331 addi r10,r10,-1 /* Get inner loop mask */ 1332 1333 li r3,1 1334 1335 mfspr r5,SPRN_MAS1 1336 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) 1337 1338 mfspr r6,SPRN_MAS2 1339 rldicr r6,r6,0,51 /* Extract EPN */ 1340 1341 mfspr r7,SPRN_MAS0 1342 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ 1343 1344 rlwinm r8,r7,16,0xfff /* Extract ESEL */ 1345 13462: add r4,r3,r8 1347 and r4,r4,r10 1348 1349 rlwimi r7,r4,16,MAS0_ESEL_MASK 1350 1351 mtspr SPRN_MAS0,r7 1352 mtspr SPRN_MAS1,r5 1353 mtspr SPRN_MAS2,r6 1354 tlbwe 1355 1356 addi r3,r3,1 1357 and. r4,r3,r10 1358 1359 bne 3f 1360 addis r6,r6,(1<<30)@h 13613: 1362 cmpw r3,r9 1363 blt 2b 1364 1365 .globl a2_tlbinit_after_iprot_flush 1366a2_tlbinit_after_iprot_flush: 1367 1368 PPC_TLBILX(0,0,R0) 1369 sync 1370 isync 1371 1372 .globl a2_tlbinit_code_end 1373a2_tlbinit_code_end: 1374 1375 /* We translate LR and return */ 1376 mflr r3 1377 tovirt(r3,r3) 1378 mtlr r3 1379 blr 1380 1381/* 1382 * Main entry (boot CPU, thread 0) 1383 * 1384 * We enter here from head_64.S, possibly after the prom_init trampoline 1385 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits 1386 * mode. Anything else is as it was left by the bootloader 1387 * 1388 * Initial requirements of this port: 1389 * 1390 * - Kernel loaded at 0 physical 1391 * - A good lump of memory mapped 0:0 by UTLB entry 0 1392 * - MSR:IS & MSR:DS set to 0 1393 * 1394 * Note that some of the above requirements will be relaxed in the future 1395 * as the kernel becomes smarter at dealing with different initial conditions 1396 * but for now you have to be careful 1397 */ 1398_GLOBAL(start_initialization_book3e) 1399 mflr r28 1400 1401 /* First, we need to setup some initial TLBs to map the kernel 1402 * text, data and bss at PAGE_OFFSET. We don't have a real mode 1403 * and always use AS 0, so we just set it up to match our link 1404 * address and never use 0 based addresses. 1405 */ 1406 bl initial_tlb_book3e 1407 1408 /* Init global core bits */ 1409 bl init_core_book3e 1410 1411 /* Init per-thread bits */ 1412 bl init_thread_book3e 1413 1414 /* Return to common init code */ 1415 tovirt(r28,r28) 1416 mtlr r28 1417 blr 1418 1419 1420/* 1421 * Secondary core/processor entry 1422 * 1423 * This is entered for thread 0 of a secondary core, all other threads 1424 * are expected to be stopped. It's similar to start_initialization_book3e 1425 * except that it's generally entered from the holding loop in head_64.S 1426 * after CPUs have been gathered by Open Firmware. 1427 * 1428 * We assume we are in 32 bits mode running with whatever TLB entry was 1429 * set for us by the firmware or POR engine. 1430 */ 1431_GLOBAL(book3e_secondary_core_init_tlb_set) 1432 li r4,1 1433 b generic_secondary_smp_init 1434 1435_GLOBAL(book3e_secondary_core_init) 1436 mflr r28 1437 1438 /* Do we need to setup initial TLB entry ? */ 1439 cmplwi r4,0 1440 bne 2f 1441 1442 /* Setup TLB for this core */ 1443 bl initial_tlb_book3e 1444 1445 /* We can return from the above running at a different 1446 * address, so recalculate r2 (TOC) 1447 */ 1448 bl relative_toc 1449 1450 /* Init global core bits */ 14512: bl init_core_book3e 1452 1453 /* Init per-thread bits */ 14543: bl init_thread_book3e 1455 1456 /* Return to common init code at proper virtual address. 1457 * 1458 * Due to various previous assumptions, we know we entered this 1459 * function at either the final PAGE_OFFSET mapping or using a 1460 * 1:1 mapping at 0, so we don't bother doing a complicated check 1461 * here, we just ensure the return address has the right top bits. 1462 * 1463 * Note that if we ever want to be smarter about where we can be 1464 * started from, we have to be careful that by the time we reach 1465 * the code below we may already be running at a different location 1466 * than the one we were called from since initial_tlb_book3e can 1467 * have moved us already. 1468 */ 1469 cmpdi cr0,r28,0 1470 blt 1f 1471 lis r3,PAGE_OFFSET@highest 1472 sldi r3,r3,32 1473 or r28,r28,r3 14741: mtlr r28 1475 blr 1476 1477_GLOBAL(book3e_secondary_thread_init) 1478 mflr r28 1479 b 3b 1480 1481 .globl init_core_book3e 1482init_core_book3e: 1483 /* Establish the interrupt vector base */ 1484 tovirt(r2,r2) 1485 LOAD_REG_ADDR(r3, interrupt_base_book3e) 1486 mtspr SPRN_IVPR,r3 1487 sync 1488 blr 1489 1490init_thread_book3e: 1491 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h 1492 mtspr SPRN_EPCR,r3 1493 1494 /* Make sure interrupts are off */ 1495 wrteei 0 1496 1497 /* disable all timers and clear out status */ 1498 li r3,0 1499 mtspr SPRN_TCR,r3 1500 mfspr r3,SPRN_TSR 1501 mtspr SPRN_TSR,r3 1502 1503 blr 1504 1505_GLOBAL(__setup_base_ivors) 1506 SET_IVOR(0, 0x020) /* Critical Input */ 1507 SET_IVOR(1, 0x000) /* Machine Check */ 1508 SET_IVOR(2, 0x060) /* Data Storage */ 1509 SET_IVOR(3, 0x080) /* Instruction Storage */ 1510 SET_IVOR(4, 0x0a0) /* External Input */ 1511 SET_IVOR(5, 0x0c0) /* Alignment */ 1512 SET_IVOR(6, 0x0e0) /* Program */ 1513 SET_IVOR(7, 0x100) /* FP Unavailable */ 1514 SET_IVOR(8, 0x120) /* System Call */ 1515 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 1516 SET_IVOR(10, 0x160) /* Decrementer */ 1517 SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 1518 SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 1519 SET_IVOR(13, 0x1c0) /* Data TLB Error */ 1520 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ 1521 SET_IVOR(15, 0x040) /* Debug */ 1522 1523 sync 1524 1525 blr 1526 1527_GLOBAL(setup_altivec_ivors) 1528 SET_IVOR(32, 0x200) /* AltiVec Unavailable */ 1529 SET_IVOR(33, 0x220) /* AltiVec Assist */ 1530 blr 1531 1532_GLOBAL(setup_perfmon_ivor) 1533 SET_IVOR(35, 0x260) /* Performance Monitor */ 1534 blr 1535 1536_GLOBAL(setup_doorbell_ivors) 1537 SET_IVOR(36, 0x280) /* Processor Doorbell */ 1538 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ 1539 blr 1540 1541_GLOBAL(setup_ehv_ivors) 1542 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ 1543 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ 1544 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ 1545 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ 1546 blr 1547 1548_GLOBAL(setup_lrat_ivor) 1549 SET_IVOR(42, 0x340) /* LRAT Error */ 1550 blr 1551