1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This program is used to generate definitions needed by 4 * assembly language modules. 5 * 6 * We use the technique used in the OSF Mach kernel code: 7 * generate asm statements containing #defines, 8 * compile this file to assembler, and then extract the 9 * #defines from the assembly-language output. 10 */ 11 12 #define GENERATING_ASM_OFFSETS /* asm/smp.h */ 13 14 #include <linux/compat.h> 15 #include <linux/signal.h> 16 #include <linux/sched.h> 17 #include <linux/kernel.h> 18 #include <linux/errno.h> 19 #include <linux/string.h> 20 #include <linux/types.h> 21 #include <linux/mman.h> 22 #include <linux/mm.h> 23 #include <linux/suspend.h> 24 #include <linux/hrtimer.h> 25 #ifdef CONFIG_PPC64 26 #include <linux/time.h> 27 #include <linux/hardirq.h> 28 #endif 29 #include <linux/kbuild.h> 30 31 #include <asm/io.h> 32 #include <asm/page.h> 33 #include <asm/processor.h> 34 #include <asm/cputable.h> 35 #include <asm/thread_info.h> 36 #include <asm/rtas.h> 37 #include <asm/vdso_datapage.h> 38 #include <asm/dbell.h> 39 #ifdef CONFIG_PPC64 40 #include <asm/paca.h> 41 #include <asm/lppaca.h> 42 #include <asm/cache.h> 43 #include <asm/mmu.h> 44 #include <asm/hvcall.h> 45 #include <asm/xics.h> 46 #endif 47 #ifdef CONFIG_PPC_POWERNV 48 #include <asm/opal.h> 49 #endif 50 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST) 51 #include <linux/kvm_host.h> 52 #endif 53 #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S) 54 #include <asm/kvm_book3s.h> 55 #include <asm/kvm_ppc.h> 56 #endif 57 58 #ifdef CONFIG_PPC32 59 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 60 #include "head_booke.h" 61 #endif 62 #endif 63 64 #if defined(CONFIG_PPC_FSL_BOOK3E) 65 #include "../mm/mmu_decl.h" 66 #endif 67 68 #ifdef CONFIG_PPC_8xx 69 #include <asm/fixmap.h> 70 #endif 71 72 #ifdef CONFIG_XMON 73 #include "../xmon/xmon_bpts.h" 74 #endif 75 76 #define STACK_PT_REGS_OFFSET(sym, val) \ 77 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val)) 78 79 int main(void) 80 { 81 OFFSET(THREAD, task_struct, thread); 82 OFFSET(MM, task_struct, mm); 83 #ifdef CONFIG_STACKPROTECTOR 84 OFFSET(TASK_CANARY, task_struct, stack_canary); 85 #ifdef CONFIG_PPC64 86 OFFSET(PACA_CANARY, paca_struct, canary); 87 #endif 88 #endif 89 #ifdef CONFIG_PPC32 90 #ifdef CONFIG_PPC_RTAS 91 OFFSET(RTAS_SP, thread_struct, rtas_sp); 92 #endif 93 #endif /* CONFIG_PPC64 */ 94 OFFSET(TASK_STACK, task_struct, stack); 95 #ifdef CONFIG_SMP 96 OFFSET(TASK_CPU, task_struct, cpu); 97 #endif 98 99 #ifdef CONFIG_LIVEPATCH 100 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp); 101 #endif 102 103 OFFSET(KSP, thread_struct, ksp); 104 OFFSET(PT_REGS, thread_struct, regs); 105 #ifdef CONFIG_BOOKE 106 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]); 107 #endif 108 #ifdef CONFIG_PPC_FPU 109 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode); 110 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr); 111 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area); 112 #endif 113 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr); 114 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp); 115 #ifdef CONFIG_ALTIVEC 116 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr); 117 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area); 118 OFFSET(THREAD_USED_VR, thread_struct, used_vr); 119 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr); 120 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec); 121 #endif /* CONFIG_ALTIVEC */ 122 #ifdef CONFIG_VSX 123 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr); 124 #endif /* CONFIG_VSX */ 125 #ifdef CONFIG_PPC64 126 OFFSET(KSP_VSID, thread_struct, ksp_vsid); 127 #else /* CONFIG_PPC64 */ 128 OFFSET(PGDIR, thread_struct, pgdir); 129 OFFSET(SRR0, thread_struct, srr0); 130 OFFSET(SRR1, thread_struct, srr1); 131 OFFSET(DAR, thread_struct, dar); 132 OFFSET(DSISR, thread_struct, dsisr); 133 #ifdef CONFIG_PPC_BOOK3S_32 134 OFFSET(THR0, thread_struct, r0); 135 OFFSET(THR3, thread_struct, r3); 136 OFFSET(THR4, thread_struct, r4); 137 OFFSET(THR5, thread_struct, r5); 138 OFFSET(THR6, thread_struct, r6); 139 OFFSET(THR8, thread_struct, r8); 140 OFFSET(THR9, thread_struct, r9); 141 OFFSET(THR11, thread_struct, r11); 142 OFFSET(THLR, thread_struct, lr); 143 OFFSET(THCTR, thread_struct, ctr); 144 #endif 145 #ifdef CONFIG_SPE 146 OFFSET(THREAD_EVR0, thread_struct, evr[0]); 147 OFFSET(THREAD_ACC, thread_struct, acc); 148 OFFSET(THREAD_USED_SPE, thread_struct, used_spe); 149 #endif /* CONFIG_SPE */ 150 #endif /* CONFIG_PPC64 */ 151 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 152 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu); 153 #endif 154 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 155 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu); 156 #endif 157 158 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 159 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch); 160 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar); 161 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr); 162 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar); 163 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar); 164 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr); 165 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr); 166 OFFSET(THREAD_TM_AMR, thread_struct, tm_amr); 167 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs); 168 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr); 169 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave); 170 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr); 171 /* Local pt_regs on stack for Transactional Memory funcs. */ 172 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD + 173 sizeof(struct pt_regs) + 16); 174 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 175 176 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags); 177 178 #ifdef CONFIG_PPC64 179 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size); 180 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size); 181 /* paca */ 182 OFFSET(PACAPACAINDEX, paca_struct, paca_index); 183 OFFSET(PACAPROCSTART, paca_struct, cpu_start); 184 OFFSET(PACAKSAVE, paca_struct, kstack); 185 OFFSET(PACACURRENT, paca_struct, __current); 186 DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) + 187 offsetof(struct task_struct, thread_info)); 188 OFFSET(PACASAVEDMSR, paca_struct, saved_msr); 189 OFFSET(PACAR1, paca_struct, saved_r1); 190 OFFSET(PACATOC, paca_struct, kernel_toc); 191 OFFSET(PACAKBASE, paca_struct, kernelbase); 192 OFFSET(PACAKMSR, paca_struct, kernel_msr); 193 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask); 194 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened); 195 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled); 196 197 #ifdef CONFIG_PPC_BOOK3E 198 OFFSET(PACAPGD, paca_struct, pgd); 199 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd); 200 OFFSET(PACA_EXGEN, paca_struct, exgen); 201 OFFSET(PACA_EXTLB, paca_struct, extlb); 202 OFFSET(PACA_EXMC, paca_struct, exmc); 203 OFFSET(PACA_EXCRIT, paca_struct, excrit); 204 OFFSET(PACA_EXDBG, paca_struct, exdbg); 205 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack); 206 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack); 207 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack); 208 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr); 209 210 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next); 211 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max); 212 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first); 213 #endif /* CONFIG_PPC_BOOK3E */ 214 215 #ifdef CONFIG_PPC_BOOK3S_64 216 OFFSET(PACA_EXGEN, paca_struct, exgen); 217 OFFSET(PACA_EXMC, paca_struct, exmc); 218 OFFSET(PACA_EXNMI, paca_struct, exnmi); 219 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr); 220 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid); 221 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid); 222 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area); 223 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use); 224 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 225 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use); 226 #endif 227 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count); 228 #endif /* CONFIG_PPC_BOOK3S_64 */ 229 OFFSET(PACAEMERGSP, paca_struct, emergency_sp); 230 #ifdef CONFIG_PPC_BOOK3S_64 231 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp); 232 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp); 233 OFFSET(PACA_IN_MCE, paca_struct, in_mce); 234 OFFSET(PACA_IN_NMI, paca_struct, in_nmi); 235 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area); 236 OFFSET(PACA_EXRFI, paca_struct, exrfi); 237 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size); 238 239 #endif 240 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id); 241 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state); 242 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default); 243 #ifdef CONFIG_PPC_BOOK3E 244 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save); 245 #endif 246 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso); 247 #else /* CONFIG_PPC64 */ 248 #endif /* CONFIG_PPC64 */ 249 250 /* RTAS */ 251 OFFSET(RTASBASE, rtas_t, base); 252 OFFSET(RTASENTRY, rtas_t, entry); 253 254 /* Interrupt register frame */ 255 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); 256 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_WITH_PT_REGS); 257 STACK_PT_REGS_OFFSET(GPR0, gpr[0]); 258 STACK_PT_REGS_OFFSET(GPR1, gpr[1]); 259 STACK_PT_REGS_OFFSET(GPR2, gpr[2]); 260 STACK_PT_REGS_OFFSET(GPR3, gpr[3]); 261 STACK_PT_REGS_OFFSET(GPR4, gpr[4]); 262 STACK_PT_REGS_OFFSET(GPR5, gpr[5]); 263 STACK_PT_REGS_OFFSET(GPR6, gpr[6]); 264 STACK_PT_REGS_OFFSET(GPR7, gpr[7]); 265 STACK_PT_REGS_OFFSET(GPR8, gpr[8]); 266 STACK_PT_REGS_OFFSET(GPR9, gpr[9]); 267 STACK_PT_REGS_OFFSET(GPR10, gpr[10]); 268 STACK_PT_REGS_OFFSET(GPR11, gpr[11]); 269 STACK_PT_REGS_OFFSET(GPR12, gpr[12]); 270 STACK_PT_REGS_OFFSET(GPR13, gpr[13]); 271 /* 272 * Note: these symbols include _ because they overlap with special 273 * register names 274 */ 275 STACK_PT_REGS_OFFSET(_NIP, nip); 276 STACK_PT_REGS_OFFSET(_MSR, msr); 277 STACK_PT_REGS_OFFSET(_CTR, ctr); 278 STACK_PT_REGS_OFFSET(_LINK, link); 279 STACK_PT_REGS_OFFSET(_CCR, ccr); 280 STACK_PT_REGS_OFFSET(_XER, xer); 281 STACK_PT_REGS_OFFSET(_DAR, dar); 282 STACK_PT_REGS_OFFSET(_DSISR, dsisr); 283 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3); 284 STACK_PT_REGS_OFFSET(RESULT, result); 285 STACK_PT_REGS_OFFSET(_TRAP, trap); 286 #ifndef CONFIG_PPC64 287 /* 288 * The PowerPC 400-class & Book-E processors have neither the DAR 289 * nor the DSISR SPRs. Hence, we overload them to hold the similar 290 * DEAR and ESR SPRs for such processors. For critical interrupts 291 * we use them to hold SRR0 and SRR1. 292 */ 293 STACK_PT_REGS_OFFSET(_DEAR, dar); 294 STACK_PT_REGS_OFFSET(_ESR, dsisr); 295 #else /* CONFIG_PPC64 */ 296 STACK_PT_REGS_OFFSET(SOFTE, softe); 297 STACK_PT_REGS_OFFSET(_PPR, ppr); 298 #endif /* CONFIG_PPC64 */ 299 300 #ifdef CONFIG_PPC_PKEY 301 STACK_PT_REGS_OFFSET(STACK_REGS_AMR, amr); 302 STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr); 303 #endif 304 305 #if defined(CONFIG_PPC32) 306 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 307 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE); 308 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); 309 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */ 310 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); 311 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1)); 312 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2)); 313 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3)); 314 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6)); 315 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7)); 316 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0)); 317 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1)); 318 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0)); 319 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1)); 320 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0)); 321 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1)); 322 #endif 323 #endif 324 325 /* About the CPU features table */ 326 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features); 327 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup); 328 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore); 329 330 OFFSET(pbe_address, pbe, address); 331 OFFSET(pbe_orig_address, pbe, orig_address); 332 OFFSET(pbe_next, pbe, next); 333 334 #ifndef CONFIG_PPC64 335 DEFINE(TASK_SIZE, TASK_SIZE); 336 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); 337 #endif /* ! CONFIG_PPC64 */ 338 339 /* datapage offsets for use by vdso */ 340 OFFSET(VDSO_DATA_OFFSET, vdso_arch_data, data); 341 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_arch_data, tb_ticks_per_sec); 342 #ifdef CONFIG_PPC64 343 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_arch_data, icache_block_size); 344 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_arch_data, dcache_block_size); 345 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_arch_data, icache_log_block_size); 346 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_arch_data, dcache_log_block_size); 347 OFFSET(CFG_SYSCALL_MAP64, vdso_arch_data, syscall_map); 348 OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, compat_syscall_map); 349 #else 350 OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, syscall_map); 351 #endif 352 353 #ifdef CONFIG_BUG 354 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry)); 355 #endif 356 357 #ifdef CONFIG_PPC_BOOK3S_64 358 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE))); 359 #else 360 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE); 361 #endif 362 DEFINE(PTE_SIZE, sizeof(pte_t)); 363 364 #ifdef CONFIG_KVM 365 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack); 366 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid); 367 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid); 368 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr); 369 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave); 370 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr); 371 #ifdef CONFIG_ALTIVEC 372 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr); 373 #endif 374 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer); 375 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); 376 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link); 377 #ifdef CONFIG_PPC_BOOK3S 378 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar); 379 #endif 380 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr); 381 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip); 382 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 383 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr); 384 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0); 385 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1); 386 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0); 387 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1); 388 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2); 389 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3); 390 #endif 391 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING 392 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry); 393 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr); 394 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit); 395 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time); 396 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time); 397 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity); 398 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start); 399 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount); 400 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total); 401 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min); 402 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max); 403 #endif 404 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3); 405 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4); 406 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5); 407 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6); 408 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7); 409 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid); 410 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1); 411 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared); 412 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr); 413 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr); 414 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE) 415 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian); 416 #endif 417 418 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0); 419 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1); 420 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2); 421 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3); 422 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4); 423 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6); 424 425 OFFSET(VCPU_KVM, kvm_vcpu, kvm); 426 OFFSET(KVM_LPID, kvm, arch.lpid); 427 428 /* book3s */ 429 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 430 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets); 431 OFFSET(KVM_SDR1, kvm, arch.sdr1); 432 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid); 433 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr); 434 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1); 435 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls); 436 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v); 437 OFFSET(KVM_RADIX, kvm, arch.radix); 438 OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest); 439 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr); 440 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar); 441 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr); 442 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty); 443 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst); 444 OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested); 445 OFFSET(VCPU_CPU, kvm_vcpu, cpu); 446 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu); 447 #endif 448 #ifdef CONFIG_PPC_BOOK3S 449 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr); 450 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr); 451 OFFSET(VCPU_IC, kvm_vcpu, arch.ic); 452 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr); 453 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr); 454 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor); 455 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr); 456 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl); 457 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr); 458 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx); 459 OFFSET(VCPU_DAWR0, kvm_vcpu, arch.dawr0); 460 OFFSET(VCPU_DAWRX0, kvm_vcpu, arch.dawrx0); 461 OFFSET(VCPU_DAWR1, kvm_vcpu, arch.dawr1); 462 OFFSET(VCPU_DAWRX1, kvm_vcpu, arch.dawrx1); 463 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr); 464 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags); 465 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires); 466 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions); 467 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded); 468 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded); 469 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending); 470 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request); 471 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr); 472 OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra); 473 OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs); 474 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc); 475 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar); 476 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar); 477 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier); 478 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb); 479 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max); 480 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr); 481 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr); 482 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar); 483 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa); 484 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr); 485 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst); 486 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap); 487 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar); 488 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr); 489 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr); 490 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb); 491 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr); 492 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr); 493 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr); 494 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr); 495 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr); 496 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr); 497 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop); 498 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort); 499 OFFSET(VCPU_TID, kvm_vcpu, arch.tid); 500 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr); 501 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr); 502 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map); 503 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest); 504 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads); 505 OFFSET(VCORE_KVM, kvmppc_vcore, kvm); 506 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset); 507 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied); 508 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr); 509 OFFSET(VCORE_PCR, kvmppc_vcore, pcr); 510 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes); 511 OFFSET(VCORE_VTB, kvmppc_vcore, vtb); 512 OFFSET(VCPU_SLB_E, kvmppc_slb, orige); 513 OFFSET(VCPU_SLB_V, kvmppc_slb, origv); 514 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb)); 515 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 516 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar); 517 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar); 518 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr); 519 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr); 520 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm); 521 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr); 522 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr); 523 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm); 524 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm); 525 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm); 526 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm); 527 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm); 528 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm); 529 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm); 530 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm); 531 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm); 532 #endif 533 534 #ifdef CONFIG_PPC_BOOK3S_64 535 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 536 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu); 537 # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f)) 538 #else 539 # define SVCPU_FIELD(x, f) 540 #endif 541 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f)) 542 #else /* 32-bit */ 543 # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f)) 544 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f)) 545 #endif 546 547 SVCPU_FIELD(SVCPU_CR, cr); 548 SVCPU_FIELD(SVCPU_XER, xer); 549 SVCPU_FIELD(SVCPU_CTR, ctr); 550 SVCPU_FIELD(SVCPU_LR, lr); 551 SVCPU_FIELD(SVCPU_PC, pc); 552 SVCPU_FIELD(SVCPU_R0, gpr[0]); 553 SVCPU_FIELD(SVCPU_R1, gpr[1]); 554 SVCPU_FIELD(SVCPU_R2, gpr[2]); 555 SVCPU_FIELD(SVCPU_R3, gpr[3]); 556 SVCPU_FIELD(SVCPU_R4, gpr[4]); 557 SVCPU_FIELD(SVCPU_R5, gpr[5]); 558 SVCPU_FIELD(SVCPU_R6, gpr[6]); 559 SVCPU_FIELD(SVCPU_R7, gpr[7]); 560 SVCPU_FIELD(SVCPU_R8, gpr[8]); 561 SVCPU_FIELD(SVCPU_R9, gpr[9]); 562 SVCPU_FIELD(SVCPU_R10, gpr[10]); 563 SVCPU_FIELD(SVCPU_R11, gpr[11]); 564 SVCPU_FIELD(SVCPU_R12, gpr[12]); 565 SVCPU_FIELD(SVCPU_R13, gpr[13]); 566 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr); 567 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar); 568 SVCPU_FIELD(SVCPU_LAST_INST, last_inst); 569 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1); 570 #ifdef CONFIG_PPC_BOOK3S_32 571 SVCPU_FIELD(SVCPU_SR, sr); 572 #endif 573 #ifdef CONFIG_PPC64 574 SVCPU_FIELD(SVCPU_SLB, slb); 575 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max); 576 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr); 577 #endif 578 579 HSTATE_FIELD(HSTATE_HOST_R1, host_r1); 580 HSTATE_FIELD(HSTATE_HOST_R2, host_r2); 581 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr); 582 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler); 583 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0); 584 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1); 585 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2); 586 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest); 587 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5); 588 HSTATE_FIELD(HSTATE_NAPPING, napping); 589 590 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 591 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req); 592 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state); 593 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu); 594 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore); 595 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys); 596 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt); 597 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi); 598 HSTATE_FIELD(HSTATE_PTID, ptid); 599 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend); 600 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]); 601 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]); 602 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]); 603 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]); 604 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]); 605 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]); 606 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]); 607 HSTATE_FIELD(HSTATE_MMCR3, host_mmcr[7]); 608 HSTATE_FIELD(HSTATE_SIER2, host_mmcr[8]); 609 HSTATE_FIELD(HSTATE_SIER3, host_mmcr[9]); 610 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]); 611 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]); 612 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]); 613 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]); 614 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]); 615 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]); 616 HSTATE_FIELD(HSTATE_PURR, host_purr); 617 HSTATE_FIELD(HSTATE_SPURR, host_spurr); 618 HSTATE_FIELD(HSTATE_DSCR, host_dscr); 619 HSTATE_FIELD(HSTATE_DABR, dabr); 620 HSTATE_FIELD(HSTATE_DECEXP, dec_expires); 621 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode); 622 DEFINE(IPI_PRIORITY, IPI_PRIORITY); 623 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr); 624 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar); 625 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar); 626 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap); 627 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped); 628 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 629 630 #ifdef CONFIG_PPC_BOOK3S_64 631 HSTATE_FIELD(HSTATE_CFAR, cfar); 632 HSTATE_FIELD(HSTATE_PPR, ppr); 633 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr); 634 #endif /* CONFIG_PPC_BOOK3S_64 */ 635 636 #else /* CONFIG_PPC_BOOK3S */ 637 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr); 638 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer); 639 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link); 640 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); 641 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip); 642 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9); 643 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst); 644 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear); 645 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr); 646 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save); 647 #endif /* CONFIG_PPC_BOOK3S */ 648 #endif /* CONFIG_KVM */ 649 650 #ifdef CONFIG_KVM_GUEST 651 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1); 652 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2); 653 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3); 654 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending); 655 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr); 656 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical); 657 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr); 658 #endif 659 660 #ifdef CONFIG_44x 661 DEFINE(PGD_T_LOG2, PGD_T_LOG2); 662 DEFINE(PTE_T_LOG2, PTE_T_LOG2); 663 #endif 664 #ifdef CONFIG_PPC_FSL_BOOK3E 665 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); 666 OFFSET(TLBCAM_MAS0, tlbcam, MAS0); 667 OFFSET(TLBCAM_MAS1, tlbcam, MAS1); 668 OFFSET(TLBCAM_MAS2, tlbcam, MAS2); 669 OFFSET(TLBCAM_MAS3, tlbcam, MAS3); 670 OFFSET(TLBCAM_MAS7, tlbcam, MAS7); 671 #endif 672 673 #if defined(CONFIG_KVM) && defined(CONFIG_SPE) 674 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]); 675 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc); 676 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr); 677 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr); 678 #endif 679 680 #ifdef CONFIG_KVM_BOOKE_HV 681 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4); 682 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6); 683 #endif 684 685 #ifdef CONFIG_KVM_XICS 686 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu, 687 arch.xive_saved_state)); 688 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu, 689 arch.xive_cam_word)); 690 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed)); 691 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on)); 692 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr)); 693 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr)); 694 #endif 695 696 #ifdef CONFIG_KVM_EXIT_TIMING 697 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu); 698 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl); 699 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu); 700 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl); 701 #endif 702 703 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); 704 705 #ifdef CONFIG_PPC_8xx 706 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE)); 707 #endif 708 709 #ifdef CONFIG_XMON 710 DEFINE(BPT_SIZE, BPT_SIZE); 711 #endif 712 713 return 0; 714 } 715