1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2001 PPC64 Team, IBM Corp 4 * 5 * This struct defines the way the registers are stored on the 6 * kernel stack during a system call or other kernel entry. 7 * 8 * this should only contain volatile regs 9 * since we can keep non-volatile in the thread_struct 10 * should set this up when only volatiles are saved 11 * by intr code. 12 * 13 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure 14 * that the overall structure is a multiple of 16 bytes in length. 15 * 16 * Note that the offsets of the fields in this struct correspond with 17 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 #ifndef _UAPI_ASM_POWERPC_PTRACE_H 25 #define _UAPI_ASM_POWERPC_PTRACE_H 26 27 28 #include <linux/types.h> 29 30 #ifndef __ASSEMBLER__ 31 32 #ifdef __KERNEL__ 33 struct user_pt_regs 34 #else 35 struct pt_regs 36 #endif 37 { 38 unsigned long gpr[32]; 39 unsigned long nip; 40 unsigned long msr; 41 unsigned long orig_gpr3; /* Used for restarting system calls */ 42 unsigned long ctr; 43 unsigned long link; 44 unsigned long xer; 45 unsigned long ccr; 46 #ifdef __powerpc64__ 47 unsigned long softe; /* Soft enabled/disabled */ 48 #else 49 unsigned long mq; /* 601 only (not used at present) */ 50 /* Used on APUS to hold IPL value. */ 51 #endif 52 unsigned long trap; /* Reason for being here */ 53 /* N.B. for critical exceptions on 4xx, the dar and dsisr 54 fields are overloaded to hold srr0 and srr1. */ 55 unsigned long dar; /* Fault registers */ 56 unsigned long dsisr; /* on 4xx/Book-E used for ESR */ 57 unsigned long result; /* Result of a system call */ 58 unsigned long exit_flags; /* System call exit flags */ 59 unsigned long __pt_regs_pad[3]; /* Maintain 16 byte interrupt stack alignment */ 60 }; 61 62 #endif /* __ASSEMBLER__ */ 63 64 65 /* 66 * Offsets used by 'ptrace' system call interface. 67 * These can't be changed without breaking binary compatibility 68 * with MkLinux, etc. 69 */ 70 #define PT_R0 0 71 #define PT_R1 1 72 #define PT_R2 2 73 #define PT_R3 3 74 #define PT_R4 4 75 #define PT_R5 5 76 #define PT_R6 6 77 #define PT_R7 7 78 #define PT_R8 8 79 #define PT_R9 9 80 #define PT_R10 10 81 #define PT_R11 11 82 #define PT_R12 12 83 #define PT_R13 13 84 #define PT_R14 14 85 #define PT_R15 15 86 #define PT_R16 16 87 #define PT_R17 17 88 #define PT_R18 18 89 #define PT_R19 19 90 #define PT_R20 20 91 #define PT_R21 21 92 #define PT_R22 22 93 #define PT_R23 23 94 #define PT_R24 24 95 #define PT_R25 25 96 #define PT_R26 26 97 #define PT_R27 27 98 #define PT_R28 28 99 #define PT_R29 29 100 #define PT_R30 30 101 #define PT_R31 31 102 103 #define PT_NIP 32 104 #define PT_MSR 33 105 #define PT_ORIG_R3 34 106 #define PT_CTR 35 107 #define PT_LNK 36 108 #define PT_XER 37 109 #define PT_CCR 38 110 #ifndef __powerpc64__ 111 #define PT_MQ 39 112 #else 113 #define PT_SOFTE 39 114 #endif 115 #define PT_TRAP 40 116 #define PT_DAR 41 117 #define PT_DSISR 42 118 #define PT_RESULT 43 119 #define PT_EXIT_FLAGS 44 120 #define PT_PAD 47 /* 3 times */ 121 #define PT_DSCR 48 122 #define PT_REGS_COUNT 48 123 124 #define PT_FPR0 (PT_REGS_COUNT + 4) /* each FP reg occupies 2 slots in this space */ 125 126 #ifndef __powerpc64__ 127 128 #define PT_FPR31 (PT_FPR0 + 2*31) 129 #define PT_FPSCR (PT_FPR0 + 2*32 + 1) 130 131 #else /* __powerpc64__ */ 132 133 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ 134 135 136 #define PT_VR0 (PT_FPSCR + 2) /* <82> each Vector reg occupies 2 slots in 64-bit */ 137 #define PT_VSCR (PT_VR0 + 32*2 + 1) 138 #define PT_VRSAVE (PT_VR0 + 33*2) 139 140 141 /* 142 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 143 */ 144 #define PT_VSR0 (PT_VRSAVE + 2) /* each VSR reg occupies 2 slots in 64-bit */ 145 #define PT_VSR31 (PT_VSR0 + 2*31) 146 #endif /* __powerpc64__ */ 147 148 /* 149 * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go. 150 * The transfer totals 34 quadword. Quadwords 0-31 contain the 151 * corresponding vector registers. Quadword 32 contains the vscr as the 152 * last word (offset 12) within that quadword. Quadword 33 contains the 153 * vrsave as the first word (offset 0) within the quadword. 154 * 155 * This definition of the VMX state is compatible with the current PPC32 156 * ptrace interface. This allows signal handling and ptrace to use the same 157 * structures. This also simplifies the implementation of a bi-arch 158 * (combined (32- and 64-bit) gdb. 159 */ 160 #define PTRACE_GETVRREGS 0x12 161 #define PTRACE_SETVRREGS 0x13 162 163 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and 164 * spefscr, in one go */ 165 #define PTRACE_GETEVRREGS 0x14 166 #define PTRACE_SETEVRREGS 0x15 167 168 /* Get the first 32 128bit VSX registers */ 169 #define PTRACE_GETVSRREGS 0x1b 170 #define PTRACE_SETVSRREGS 0x1c 171 172 /* Syscall emulation defines */ 173 #define PTRACE_SYSEMU 0x1d 174 #define PTRACE_SYSEMU_SINGLESTEP 0x1e 175 176 /* 177 * Get or set a debug register. The first 16 are DABR registers and the 178 * second 16 are IABR registers. 179 */ 180 #define PTRACE_GET_DEBUGREG 0x19 181 #define PTRACE_SET_DEBUGREG 0x1a 182 183 /* (new) PTRACE requests using the same numbers as x86 and the same 184 * argument ordering. Additionally, they support more registers too 185 */ 186 #define PTRACE_GETREGS 0xc 187 #define PTRACE_SETREGS 0xd 188 #define PTRACE_GETFPREGS 0xe 189 #define PTRACE_SETFPREGS 0xf 190 #define PTRACE_GETREGS64 0x16 191 #define PTRACE_SETREGS64 0x17 192 193 /* Calls to trace a 64bit program from a 32bit program */ 194 #define PPC_PTRACE_PEEKTEXT_3264 0x95 195 #define PPC_PTRACE_PEEKDATA_3264 0x94 196 #define PPC_PTRACE_POKETEXT_3264 0x93 197 #define PPC_PTRACE_POKEDATA_3264 0x92 198 #define PPC_PTRACE_PEEKUSR_3264 0x91 199 #define PPC_PTRACE_POKEUSR_3264 0x90 200 201 #define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 202 203 #define PPC_PTRACE_GETHWDBGINFO 0x89 204 #define PPC_PTRACE_SETHWDEBUG 0x88 205 #define PPC_PTRACE_DELHWDEBUG 0x87 206 207 #ifndef __ASSEMBLER__ 208 209 struct ppc_debug_info { 210 __u32 version; /* Only version 1 exists to date */ 211 __u32 num_instruction_bps; 212 __u32 num_data_bps; 213 __u32 num_condition_regs; 214 __u32 data_bp_alignment; 215 __u32 sizeof_condition; /* size of the DVC register */ 216 __u64 features; 217 }; 218 219 #endif /* __ASSEMBLER__ */ 220 221 /* 222 * features will have bits indication whether there is support for: 223 */ 224 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001 225 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002 226 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004 227 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008 228 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x0000000000000010 229 #define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 0x0000000000000020 230 231 #ifndef __ASSEMBLER__ 232 233 struct ppc_hw_breakpoint { 234 __u32 version; /* currently, version must be 1 */ 235 __u32 trigger_type; /* only some combinations allowed */ 236 __u32 addr_mode; /* address match mode */ 237 __u32 condition_mode; /* break/watchpoint condition flags */ 238 __u64 addr; /* break/watchpoint address */ 239 __u64 addr2; /* range end or mask */ 240 __u64 condition_value; /* contents of the DVC register */ 241 }; 242 243 #endif /* __ASSEMBLER__ */ 244 245 /* 246 * Trigger Type 247 */ 248 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001 249 #define PPC_BREAKPOINT_TRIGGER_READ 0x00000002 250 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004 251 #define PPC_BREAKPOINT_TRIGGER_RW \ 252 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE) 253 254 /* 255 * Address Mode 256 */ 257 #define PPC_BREAKPOINT_MODE_EXACT 0x00000000 258 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001 259 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002 260 #define PPC_BREAKPOINT_MODE_MASK 0x00000003 261 262 /* 263 * Condition Mode 264 */ 265 #define PPC_BREAKPOINT_CONDITION_MODE 0x00000003 266 #define PPC_BREAKPOINT_CONDITION_NONE 0x00000000 267 #define PPC_BREAKPOINT_CONDITION_AND 0x00000001 268 #define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND 269 #define PPC_BREAKPOINT_CONDITION_OR 0x00000002 270 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003 271 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 272 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 273 #define PPC_BREAKPOINT_CONDITION_BE(n) \ 274 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) 275 276 #endif /* _UAPI_ASM_POWERPC_PTRACE_H */ 277