1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * 17 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 18 */ 19 20 #ifndef __LINUX_KVM_POWERPC_H 21 #define __LINUX_KVM_POWERPC_H 22 23 #include <linux/types.h> 24 25 /* Select powerpc specific features in <linux/kvm.h> */ 26 #define __KVM_HAVE_SPAPR_TCE 27 #define __KVM_HAVE_PPC_SMT 28 29 struct kvm_regs { 30 __u64 pc; 31 __u64 cr; 32 __u64 ctr; 33 __u64 lr; 34 __u64 xer; 35 __u64 msr; 36 __u64 srr0; 37 __u64 srr1; 38 __u64 pid; 39 40 __u64 sprg0; 41 __u64 sprg1; 42 __u64 sprg2; 43 __u64 sprg3; 44 __u64 sprg4; 45 __u64 sprg5; 46 __u64 sprg6; 47 __u64 sprg7; 48 49 __u64 gpr[32]; 50 }; 51 52 #define KVM_SREGS_E_IMPL_NONE 0 53 #define KVM_SREGS_E_IMPL_FSL 1 54 55 #define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */ 56 57 /* 58 * Feature bits indicate which sections of the sregs struct are valid, 59 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers 60 * corresponding to unset feature bits will not be modified. This allows 61 * restoring a checkpoint made without that feature, while keeping the 62 * default values of the new registers. 63 * 64 * KVM_SREGS_E_BASE contains: 65 * CSRR0/1 (refers to SRR2/3 on 40x) 66 * ESR 67 * DEAR 68 * MCSR 69 * TSR 70 * TCR 71 * DEC 72 * TB 73 * VRSAVE (USPRG0) 74 */ 75 #define KVM_SREGS_E_BASE (1 << 0) 76 77 /* 78 * KVM_SREGS_E_ARCH206 contains: 79 * 80 * PIR 81 * MCSRR0/1 82 * DECAR 83 * IVPR 84 */ 85 #define KVM_SREGS_E_ARCH206 (1 << 1) 86 87 /* 88 * Contains EPCR, plus the upper half of 64-bit registers 89 * that are 32-bit on 32-bit implementations. 90 */ 91 #define KVM_SREGS_E_64 (1 << 2) 92 93 #define KVM_SREGS_E_SPRG8 (1 << 3) 94 #define KVM_SREGS_E_MCIVPR (1 << 4) 95 96 /* 97 * IVORs are used -- contains IVOR0-15, plus additional IVORs 98 * in combination with an appropriate feature bit. 99 */ 100 #define KVM_SREGS_E_IVOR (1 << 5) 101 102 /* 103 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG. 104 * Also TLBnPS if MMUCFG[MAVN] = 1. 105 */ 106 #define KVM_SREGS_E_ARCH206_MMU (1 << 6) 107 108 /* DBSR, DBCR, IAC, DAC, DVC */ 109 #define KVM_SREGS_E_DEBUG (1 << 7) 110 111 /* Enhanced debug -- DSRR0/1, SPRG9 */ 112 #define KVM_SREGS_E_ED (1 << 8) 113 114 /* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */ 115 #define KVM_SREGS_E_SPE (1 << 9) 116 117 /* External Proxy (EXP) -- EPR */ 118 #define KVM_SREGS_EXP (1 << 10) 119 120 /* External PID (E.PD) -- EPSC/EPLC */ 121 #define KVM_SREGS_E_PD (1 << 11) 122 123 /* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */ 124 #define KVM_SREGS_E_PC (1 << 12) 125 126 /* Page table (E.PT) -- EPTCFG */ 127 #define KVM_SREGS_E_PT (1 << 13) 128 129 /* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */ 130 #define KVM_SREGS_E_PM (1 << 14) 131 132 /* 133 * Special updates: 134 * 135 * Some registers may change even while a vcpu is not running. 136 * To avoid losing these changes, by default these registers are 137 * not updated by KVM_SET_SREGS. To force an update, set the bit 138 * in u.e.update_special corresponding to the register to be updated. 139 * 140 * The update_special field is zero on return from KVM_GET_SREGS. 141 * 142 * When restoring a checkpoint, the caller can set update_special 143 * to 0xffffffff to ensure that everything is restored, even new features 144 * that the caller doesn't know about. 145 */ 146 #define KVM_SREGS_E_UPDATE_MCSR (1 << 0) 147 #define KVM_SREGS_E_UPDATE_TSR (1 << 1) 148 #define KVM_SREGS_E_UPDATE_DEC (1 << 2) 149 #define KVM_SREGS_E_UPDATE_DBSR (1 << 3) 150 151 /* 152 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a 153 * previous KVM_GET_REGS. 154 * 155 * Unless otherwise indicated, setting any register with KVM_SET_SREGS 156 * directly sets its value. It does not trigger any special semantics such 157 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct 158 * just received from KVM_GET_SREGS is always a no-op. 159 */ 160 struct kvm_sregs { 161 __u32 pvr; 162 union { 163 struct { 164 __u64 sdr1; 165 struct { 166 struct { 167 __u64 slbe; 168 __u64 slbv; 169 } slb[64]; 170 } ppc64; 171 struct { 172 __u32 sr[16]; 173 __u64 ibat[8]; 174 __u64 dbat[8]; 175 } ppc32; 176 } s; 177 struct { 178 union { 179 struct { /* KVM_SREGS_E_IMPL_FSL */ 180 __u32 features; /* KVM_SREGS_E_FSL_ */ 181 __u32 svr; 182 __u64 mcar; 183 __u32 hid0; 184 185 /* KVM_SREGS_E_FSL_PIDn */ 186 __u32 pid1, pid2; 187 } fsl; 188 __u8 pad[256]; 189 } impl; 190 191 __u32 features; /* KVM_SREGS_E_ */ 192 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */ 193 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */ 194 __u32 pir; /* read-only */ 195 __u64 sprg8; 196 __u64 sprg9; /* E.ED */ 197 __u64 csrr0; 198 __u64 dsrr0; /* E.ED */ 199 __u64 mcsrr0; 200 __u32 csrr1; 201 __u32 dsrr1; /* E.ED */ 202 __u32 mcsrr1; 203 __u32 esr; 204 __u64 dear; 205 __u64 ivpr; 206 __u64 mcivpr; 207 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */ 208 209 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */ 210 __u32 tcr; 211 __u32 decar; 212 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */ 213 214 /* 215 * Userspace can read TB directly, but the 216 * value reported here is consistent with "dec". 217 * 218 * Read-only. 219 */ 220 __u64 tb; 221 222 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */ 223 __u32 dbcr[3]; 224 /* 225 * iac/dac registers are 64bit wide, while this API 226 * interface provides only lower 32 bits on 64 bit 227 * processors. ONE_REG interface is added for 64bit 228 * iac/dac registers. 229 */ 230 __u32 iac[4]; 231 __u32 dac[2]; 232 __u32 dvc[2]; 233 __u8 num_iac; /* read-only */ 234 __u8 num_dac; /* read-only */ 235 __u8 num_dvc; /* read-only */ 236 __u8 pad; 237 238 __u32 epr; /* EXP */ 239 __u32 vrsave; /* a.k.a. USPRG0 */ 240 __u32 epcr; /* KVM_SREGS_E_64 */ 241 242 __u32 mas0; 243 __u32 mas1; 244 __u64 mas2; 245 __u64 mas7_3; 246 __u32 mas4; 247 __u32 mas6; 248 249 __u32 ivor_low[16]; /* IVOR0-15 */ 250 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */ 251 252 __u32 mmucfg; /* read-only */ 253 __u32 eptcfg; /* E.PT, read-only */ 254 __u32 tlbcfg[4];/* read-only */ 255 __u32 tlbps[4]; /* read-only */ 256 257 __u32 eplc, epsc; /* E.PD */ 258 } e; 259 __u8 pad[1020]; 260 } u; 261 }; 262 263 struct kvm_fpu { 264 __u64 fpr[32]; 265 }; 266 267 struct kvm_debug_exit_arch { 268 }; 269 270 /* for KVM_SET_GUEST_DEBUG */ 271 struct kvm_guest_debug_arch { 272 }; 273 274 /* definition of registers in kvm_run */ 275 struct kvm_sync_regs { 276 }; 277 278 #define KVM_INTERRUPT_SET -1U 279 #define KVM_INTERRUPT_UNSET -2U 280 #define KVM_INTERRUPT_SET_LEVEL -3U 281 282 #define KVM_CPU_440 1 283 #define KVM_CPU_E500V2 2 284 #define KVM_CPU_3S_32 3 285 #define KVM_CPU_3S_64 4 286 #define KVM_CPU_E500MC 5 287 288 /* for KVM_CAP_SPAPR_TCE */ 289 struct kvm_create_spapr_tce { 290 __u64 liobn; 291 __u32 window_size; 292 }; 293 294 /* for KVM_ALLOCATE_RMA */ 295 struct kvm_allocate_rma { 296 __u64 rma_size; 297 }; 298 299 struct kvm_book3e_206_tlb_entry { 300 __u32 mas8; 301 __u32 mas1; 302 __u64 mas2; 303 __u64 mas7_3; 304 }; 305 306 struct kvm_book3e_206_tlb_params { 307 /* 308 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV: 309 * 310 * - The number of ways of TLB0 must be a power of two between 2 and 311 * 16. 312 * - TLB1 must be fully associative. 313 * - The size of TLB0 must be a multiple of the number of ways, and 314 * the number of sets must be a power of two. 315 * - The size of TLB1 may not exceed 64 entries. 316 * - TLB0 supports 4 KiB pages. 317 * - The page sizes supported by TLB1 are as indicated by 318 * TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1) 319 * as returned by KVM_GET_SREGS. 320 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[] 321 * and tlb_ways[] must be zero. 322 * 323 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative. 324 * 325 * KVM will adjust TLBnCFG based on the sizes configured here, 326 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY] 327 * set to zero. 328 */ 329 __u32 tlb_sizes[4]; 330 __u32 tlb_ways[4]; 331 __u32 reserved[8]; 332 }; 333 334 /* For KVM_PPC_GET_HTAB_FD */ 335 struct kvm_get_htab_fd { 336 __u64 flags; 337 __u64 start_index; 338 __u64 reserved[2]; 339 }; 340 341 /* Values for kvm_get_htab_fd.flags */ 342 #define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1) 343 #define KVM_GET_HTAB_WRITE ((__u64)0x2) 344 345 /* 346 * Data read on the file descriptor is formatted as a series of 347 * records, each consisting of a header followed by a series of 348 * `n_valid' HPTEs (16 bytes each), which are all valid. Following 349 * those valid HPTEs there are `n_invalid' invalid HPTEs, which 350 * are not represented explicitly in the stream. The same format 351 * is used for writing. 352 */ 353 struct kvm_get_htab_header { 354 __u32 index; 355 __u16 n_valid; 356 __u16 n_invalid; 357 }; 358 359 #define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1) 360 #define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2) 361 #define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3) 362 #define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4) 363 #define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5) 364 #define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6) 365 #define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7) 366 #define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8) 367 #define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9) 368 #define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa) 369 #define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb) 370 #define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc) 371 #define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd) 372 #define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe) 373 #define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf) 374 375 #define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10) 376 #define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11) 377 #define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12) 378 379 #define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18) 380 #define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19) 381 #define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a) 382 #define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b) 383 #define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c) 384 #define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d) 385 #define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e) 386 #define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f) 387 388 /* 32 floating-point registers */ 389 #define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20) 390 #define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n)) 391 #define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f) 392 393 /* 32 VMX/Altivec vector registers */ 394 #define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40) 395 #define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n)) 396 #define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f) 397 398 /* 32 double-width FP registers for VSX */ 399 /* High-order halves overlap with FP regs */ 400 #define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60) 401 #define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n)) 402 #define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f) 403 404 /* FP and vector status/control registers */ 405 #define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80) 406 #define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81) 407 408 /* Virtual processor areas */ 409 /* For SLB & DTL, address in high (first) half, length in low half */ 410 #define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82) 411 #define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83) 412 #define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84) 413 414 #define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85) 415 416 #endif /* __LINUX_KVM_POWERPC_H */ 417