1b8b572e1SStephen Rothwell /* 2b8b572e1SStephen Rothwell * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM 3b8b572e1SStephen Rothwell * 4b8b572e1SStephen Rothwell * This program is free software; you can redistribute it and/or 5b8b572e1SStephen Rothwell * modify it under the terms of the GNU General Public License 6b8b572e1SStephen Rothwell * as published by the Free Software Foundation; either version 7b8b572e1SStephen Rothwell * 2 of the License, or (at your option) any later version. 8b8b572e1SStephen Rothwell */ 9b8b572e1SStephen Rothwell 10b8b572e1SStephen Rothwell struct pt_regs; 11b8b572e1SStephen Rothwell 12b8b572e1SStephen Rothwell /* 13b8b572e1SStephen Rothwell * We don't allow single-stepping an mtmsrd that would clear 14b8b572e1SStephen Rothwell * MSR_RI, since that would make the exception unrecoverable. 15b8b572e1SStephen Rothwell * Since we need to single-step to proceed from a breakpoint, 16b8b572e1SStephen Rothwell * we don't allow putting a breakpoint on an mtmsrd instruction. 17b8b572e1SStephen Rothwell * Similarly we don't allow breakpoints on rfid instructions. 18b8b572e1SStephen Rothwell * These macros tell us if an instruction is a mtmsrd or rfid. 19b8b572e1SStephen Rothwell * Note that IS_MTMSRD returns true for both an mtmsr (32-bit) 20b8b572e1SStephen Rothwell * and an mtmsrd (64-bit). 21b8b572e1SStephen Rothwell */ 22b8b572e1SStephen Rothwell #define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124) 23b8b572e1SStephen Rothwell #define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024) 24b8b572e1SStephen Rothwell #define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064) 25b8b572e1SStephen Rothwell 26be96f633SPaul Mackerras enum instruction_type { 27be96f633SPaul Mackerras COMPUTE, /* arith/logical/CR op, etc. */ 28d120cdbcSPaul Mackerras LOAD, /* load and store types need to be contiguous */ 29be96f633SPaul Mackerras LOAD_MULTI, 30be96f633SPaul Mackerras LOAD_FP, 31be96f633SPaul Mackerras LOAD_VMX, 32be96f633SPaul Mackerras LOAD_VSX, 33be96f633SPaul Mackerras STORE, 34be96f633SPaul Mackerras STORE_MULTI, 35be96f633SPaul Mackerras STORE_FP, 36be96f633SPaul Mackerras STORE_VMX, 37be96f633SPaul Mackerras STORE_VSX, 38be96f633SPaul Mackerras LARX, 39be96f633SPaul Mackerras STCX, 40be96f633SPaul Mackerras BRANCH, 41be96f633SPaul Mackerras MFSPR, 42be96f633SPaul Mackerras MTSPR, 43be96f633SPaul Mackerras CACHEOP, 44be96f633SPaul Mackerras BARRIER, 45be96f633SPaul Mackerras SYSCALL, 46be96f633SPaul Mackerras MFMSR, 47be96f633SPaul Mackerras MTMSR, 48be96f633SPaul Mackerras RFI, 49be96f633SPaul Mackerras INTERRUPT, 50be96f633SPaul Mackerras UNKNOWN 51be96f633SPaul Mackerras }; 52be96f633SPaul Mackerras 53be96f633SPaul Mackerras #define INSTR_TYPE_MASK 0x1f 54be96f633SPaul Mackerras 55d120cdbcSPaul Mackerras #define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX) 56d120cdbcSPaul Mackerras 573cdfcbfdSPaul Mackerras /* Compute flags, ORed in with type */ 583cdfcbfdSPaul Mackerras #define SETREG 0x20 593cdfcbfdSPaul Mackerras #define SETCC 0x40 603cdfcbfdSPaul Mackerras #define SETXER 0x80 613cdfcbfdSPaul Mackerras 623cdfcbfdSPaul Mackerras /* Branch flags, ORed in with type */ 633cdfcbfdSPaul Mackerras #define SETLK 0x20 643cdfcbfdSPaul Mackerras #define BRTAKEN 0x40 653cdfcbfdSPaul Mackerras #define DECCTR 0x80 663cdfcbfdSPaul Mackerras 67be96f633SPaul Mackerras /* Load/store flags, ORed in with type */ 68be96f633SPaul Mackerras #define SIGNEXT 0x20 69be96f633SPaul Mackerras #define UPDATE 0x40 /* matches bit in opcode 31 instructions */ 70be96f633SPaul Mackerras #define BYTEREV 0x80 71*d2b65ac6SPaul Mackerras #define FPCONV 0x100 72be96f633SPaul Mackerras 733cdfcbfdSPaul Mackerras /* Barrier type field, ORed in with type */ 743cdfcbfdSPaul Mackerras #define BARRIER_MASK 0xe0 753cdfcbfdSPaul Mackerras #define BARRIER_SYNC 0x00 763cdfcbfdSPaul Mackerras #define BARRIER_ISYNC 0x20 773cdfcbfdSPaul Mackerras #define BARRIER_EIEIO 0x40 783cdfcbfdSPaul Mackerras #define BARRIER_LWSYNC 0x60 793cdfcbfdSPaul Mackerras #define BARRIER_PTESYNC 0x80 803cdfcbfdSPaul Mackerras 81be96f633SPaul Mackerras /* Cacheop values, ORed in with type */ 82be96f633SPaul Mackerras #define CACHEOP_MASK 0x700 83be96f633SPaul Mackerras #define DCBST 0 84be96f633SPaul Mackerras #define DCBF 0x100 85be96f633SPaul Mackerras #define DCBTST 0x200 86be96f633SPaul Mackerras #define DCBT 0x300 87cf87c3f6SPaul Mackerras #define ICBI 0x400 88b2543f7bSPaul Mackerras #define DCBZ 0x500 89be96f633SPaul Mackerras 90350779a2SPaul Mackerras /* VSX flags values */ 91350779a2SPaul Mackerras #define VSX_FPCONV 1 /* do floating point SP/DP conversion */ 92350779a2SPaul Mackerras #define VSX_SPLAT 2 /* store loaded value into all elements */ 93350779a2SPaul Mackerras #define VSX_LDLEFT 4 /* load VSX register from left */ 94350779a2SPaul Mackerras #define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */ 95350779a2SPaul Mackerras 96be96f633SPaul Mackerras /* Size field in type word */ 97*d2b65ac6SPaul Mackerras #define SIZE(n) ((n) << 12) 98*d2b65ac6SPaul Mackerras #define GETSIZE(w) ((w) >> 12) 99be96f633SPaul Mackerras 100be96f633SPaul Mackerras #define MKOP(t, f, s) ((t) | (f) | SIZE(s)) 101be96f633SPaul Mackerras 102be96f633SPaul Mackerras struct instruction_op { 103be96f633SPaul Mackerras int type; 104be96f633SPaul Mackerras int reg; 105be96f633SPaul Mackerras unsigned long val; 106be96f633SPaul Mackerras /* For LOAD/STORE/LARX/STCX */ 107be96f633SPaul Mackerras unsigned long ea; 108be96f633SPaul Mackerras int update_reg; 109be96f633SPaul Mackerras /* For MFSPR */ 110be96f633SPaul Mackerras int spr; 1113cdfcbfdSPaul Mackerras u32 ccval; 1123cdfcbfdSPaul Mackerras u32 xerval; 113350779a2SPaul Mackerras u8 element_size; /* for VSX/VMX loads/stores */ 114350779a2SPaul Mackerras u8 vsx_flags; 115350779a2SPaul Mackerras }; 116350779a2SPaul Mackerras 117350779a2SPaul Mackerras union vsx_reg { 118350779a2SPaul Mackerras u8 b[16]; 119350779a2SPaul Mackerras u16 h[8]; 120350779a2SPaul Mackerras u32 w[4]; 121350779a2SPaul Mackerras unsigned long d[2]; 122350779a2SPaul Mackerras float fp[4]; 123350779a2SPaul Mackerras double dp[2]; 124c22435a5SPaul Mackerras __vector128 v; 125be96f633SPaul Mackerras }; 126be96f633SPaul Mackerras 1273cdfcbfdSPaul Mackerras /* 1283cdfcbfdSPaul Mackerras * Decode an instruction, and return information about it in *op 1293cdfcbfdSPaul Mackerras * without changing *regs. 1303cdfcbfdSPaul Mackerras * 1313cdfcbfdSPaul Mackerras * Return value is 1 if the instruction can be emulated just by 1323cdfcbfdSPaul Mackerras * updating *regs with the information in *op, -1 if we need the 1333cdfcbfdSPaul Mackerras * GPRs but *regs doesn't contain the full register set, or 0 1343cdfcbfdSPaul Mackerras * otherwise. 1353cdfcbfdSPaul Mackerras */ 1363cdfcbfdSPaul Mackerras extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, 137be96f633SPaul Mackerras unsigned int instr); 1383cdfcbfdSPaul Mackerras 1393cdfcbfdSPaul Mackerras /* 1403cdfcbfdSPaul Mackerras * Emulate an instruction that can be executed just by updating 1413cdfcbfdSPaul Mackerras * fields in *regs. 1423cdfcbfdSPaul Mackerras */ 1433cdfcbfdSPaul Mackerras void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op); 1443cdfcbfdSPaul Mackerras 1453cdfcbfdSPaul Mackerras /* 1463cdfcbfdSPaul Mackerras * Emulate instructions that cause a transfer of control, 1473cdfcbfdSPaul Mackerras * arithmetic/logical instructions, loads and stores, 1483cdfcbfdSPaul Mackerras * cache operations and barriers. 1493cdfcbfdSPaul Mackerras * 1503cdfcbfdSPaul Mackerras * Returns 1 if the instruction was emulated successfully, 1513cdfcbfdSPaul Mackerras * 0 if it could not be emulated, or -1 for an instruction that 1523cdfcbfdSPaul Mackerras * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.). 1533cdfcbfdSPaul Mackerras */ 1543cdfcbfdSPaul Mackerras extern int emulate_step(struct pt_regs *regs, unsigned int instr); 1553cdfcbfdSPaul Mackerras 156a53d5182SPaul Mackerras /* 157a53d5182SPaul Mackerras * Emulate a load or store instruction by reading/writing the 158a53d5182SPaul Mackerras * memory of the current process. FP/VMX/VSX registers are assumed 159a53d5182SPaul Mackerras * to hold live values if the appropriate enable bit in regs->msr is 160a53d5182SPaul Mackerras * set; otherwise this will use the saved values in the thread struct 161a53d5182SPaul Mackerras * for user-mode accesses. 162a53d5182SPaul Mackerras */ 163a53d5182SPaul Mackerras extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op); 164a53d5182SPaul Mackerras 165350779a2SPaul Mackerras extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, 166d955189aSPaul Mackerras const void *mem, bool cross_endian); 167d955189aSPaul Mackerras extern void emulate_vsx_store(struct instruction_op *op, 168d955189aSPaul Mackerras const union vsx_reg *reg, void *mem, 169d955189aSPaul Mackerras bool cross_endian); 170b2543f7bSPaul Mackerras extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs); 171