1 #ifndef _ASM_POWERPC_PTRACE_H 2 #define _ASM_POWERPC_PTRACE_H 3 4 /* 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This struct defines the way the registers are stored on the 8 * kernel stack during a system call or other kernel entry. 9 * 10 * this should only contain volatile regs 11 * since we can keep non-volatile in the thread_struct 12 * should set this up when only volatiles are saved 13 * by intr code. 14 * 15 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure 16 * that the overall structure is a multiple of 16 bytes in length. 17 * 18 * Note that the offsets of the fields in this struct correspond with 19 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. 20 * 21 * This program is free software; you can redistribute it and/or 22 * modify it under the terms of the GNU General Public License 23 * as published by the Free Software Foundation; either version 24 * 2 of the License, or (at your option) any later version. 25 */ 26 27 #ifdef __KERNEL__ 28 #include <linux/types.h> 29 #else 30 #include <stdint.h> 31 #endif 32 33 #ifndef __ASSEMBLY__ 34 35 struct pt_regs { 36 unsigned long gpr[32]; 37 unsigned long nip; 38 unsigned long msr; 39 unsigned long orig_gpr3; /* Used for restarting system calls */ 40 unsigned long ctr; 41 unsigned long link; 42 unsigned long xer; 43 unsigned long ccr; 44 #ifdef __powerpc64__ 45 unsigned long softe; /* Soft enabled/disabled */ 46 #else 47 unsigned long mq; /* 601 only (not used at present) */ 48 /* Used on APUS to hold IPL value. */ 49 #endif 50 unsigned long trap; /* Reason for being here */ 51 /* N.B. for critical exceptions on 4xx, the dar and dsisr 52 fields are overloaded to hold srr0 and srr1. */ 53 unsigned long dar; /* Fault registers */ 54 unsigned long dsisr; /* on 4xx/Book-E used for ESR */ 55 unsigned long result; /* Result of a system call */ 56 }; 57 58 #endif /* __ASSEMBLY__ */ 59 60 #ifdef __KERNEL__ 61 62 #ifdef __powerpc64__ 63 64 #define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ 65 #define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */ 66 #define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265) 67 #define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \ 68 STACK_FRAME_OVERHEAD + 288) 69 #define STACK_FRAME_MARKER 12 70 71 /* Size of dummy stack frame allocated when calling signal handler. */ 72 #define __SIGNAL_FRAMESIZE 128 73 #define __SIGNAL_FRAMESIZE32 64 74 75 #else /* __powerpc64__ */ 76 77 #define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ 78 #define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */ 79 #define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773) 80 #define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD) 81 #define STACK_FRAME_MARKER 2 82 83 /* Size of stack frame allocated when calling signal handler. */ 84 #define __SIGNAL_FRAMESIZE 64 85 86 #endif /* __powerpc64__ */ 87 88 #ifndef __ASSEMBLY__ 89 90 #define instruction_pointer(regs) ((regs)->nip) 91 #define user_stack_pointer(regs) ((regs)->gpr[1]) 92 #define regs_return_value(regs) ((regs)->gpr[3]) 93 94 #ifdef CONFIG_SMP 95 extern unsigned long profile_pc(struct pt_regs *regs); 96 #else 97 #define profile_pc(regs) instruction_pointer(regs) 98 #endif 99 100 #ifdef __powerpc64__ 101 #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1) 102 #else 103 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0) 104 #endif 105 106 #define force_successful_syscall_return() \ 107 do { \ 108 set_thread_flag(TIF_NOERROR); \ 109 } while(0) 110 111 struct task_struct; 112 extern unsigned long ptrace_get_reg(struct task_struct *task, int regno); 113 extern int ptrace_put_reg(struct task_struct *task, int regno, 114 unsigned long data); 115 116 /* 117 * We use the least-significant bit of the trap field to indicate 118 * whether we have saved the full set of registers, or only a 119 * partial set. A 1 there means the partial set. 120 * On 4xx we use the next bit to indicate whether the exception 121 * is a critical exception (1 means it is). 122 */ 123 #define FULL_REGS(regs) (((regs)->trap & 1) == 0) 124 #ifndef __powerpc64__ 125 #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0) 126 #define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0) 127 #define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0) 128 #endif /* ! __powerpc64__ */ 129 #define TRAP(regs) ((regs)->trap & ~0xF) 130 #ifdef __powerpc64__ 131 #define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1) 132 #else 133 #define CHECK_FULL_REGS(regs) \ 134 do { \ 135 if ((regs)->trap & 1) \ 136 printk(KERN_CRIT "%s: partial register set\n", __func__); \ 137 } while (0) 138 #endif /* __powerpc64__ */ 139 140 /* 141 * These are defined as per linux/ptrace.h, which see. 142 */ 143 #define arch_has_single_step() (1) 144 #define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601)) 145 extern void user_enable_single_step(struct task_struct *); 146 extern void user_enable_block_step(struct task_struct *); 147 extern void user_disable_single_step(struct task_struct *); 148 149 #define ARCH_HAS_USER_SINGLE_STEP_INFO 150 151 #endif /* __ASSEMBLY__ */ 152 153 #endif /* __KERNEL__ */ 154 155 /* 156 * Offsets used by 'ptrace' system call interface. 157 * These can't be changed without breaking binary compatibility 158 * with MkLinux, etc. 159 */ 160 #define PT_R0 0 161 #define PT_R1 1 162 #define PT_R2 2 163 #define PT_R3 3 164 #define PT_R4 4 165 #define PT_R5 5 166 #define PT_R6 6 167 #define PT_R7 7 168 #define PT_R8 8 169 #define PT_R9 9 170 #define PT_R10 10 171 #define PT_R11 11 172 #define PT_R12 12 173 #define PT_R13 13 174 #define PT_R14 14 175 #define PT_R15 15 176 #define PT_R16 16 177 #define PT_R17 17 178 #define PT_R18 18 179 #define PT_R19 19 180 #define PT_R20 20 181 #define PT_R21 21 182 #define PT_R22 22 183 #define PT_R23 23 184 #define PT_R24 24 185 #define PT_R25 25 186 #define PT_R26 26 187 #define PT_R27 27 188 #define PT_R28 28 189 #define PT_R29 29 190 #define PT_R30 30 191 #define PT_R31 31 192 193 #define PT_NIP 32 194 #define PT_MSR 33 195 #define PT_ORIG_R3 34 196 #define PT_CTR 35 197 #define PT_LNK 36 198 #define PT_XER 37 199 #define PT_CCR 38 200 #ifndef __powerpc64__ 201 #define PT_MQ 39 202 #else 203 #define PT_SOFTE 39 204 #endif 205 #define PT_TRAP 40 206 #define PT_DAR 41 207 #define PT_DSISR 42 208 #define PT_RESULT 43 209 #define PT_REGS_COUNT 44 210 211 #define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ 212 213 #ifndef __powerpc64__ 214 215 #define PT_FPR31 (PT_FPR0 + 2*31) 216 #define PT_FPSCR (PT_FPR0 + 2*32 + 1) 217 218 #else /* __powerpc64__ */ 219 220 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ 221 222 #ifdef __KERNEL__ 223 #define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */ 224 #endif 225 226 #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ 227 #define PT_VSCR (PT_VR0 + 32*2 + 1) 228 #define PT_VRSAVE (PT_VR0 + 33*2) 229 230 #ifdef __KERNEL__ 231 #define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */ 232 #define PT_VSCR_32 (PT_VR0 + 32*4 + 3) 233 #define PT_VRSAVE_32 (PT_VR0 + 33*4) 234 #endif 235 236 /* 237 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31 238 */ 239 #define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ 240 #define PT_VSR31 (PT_VSR0 + 2*31) 241 #ifdef __KERNEL__ 242 #define PT_VSR0_32 300 /* each VSR reg occupies 4 slots in 32-bit */ 243 #endif 244 #endif /* __powerpc64__ */ 245 246 /* 247 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. 248 * The transfer totals 34 quadword. Quadwords 0-31 contain the 249 * corresponding vector registers. Quadword 32 contains the vscr as the 250 * last word (offset 12) within that quadword. Quadword 33 contains the 251 * vrsave as the first word (offset 0) within the quadword. 252 * 253 * This definition of the VMX state is compatible with the current PPC32 254 * ptrace interface. This allows signal handling and ptrace to use the same 255 * structures. This also simplifies the implementation of a bi-arch 256 * (combined (32- and 64-bit) gdb. 257 */ 258 #define PTRACE_GETVRREGS 18 259 #define PTRACE_SETVRREGS 19 260 261 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and 262 * spefscr, in one go */ 263 #define PTRACE_GETEVRREGS 20 264 #define PTRACE_SETEVRREGS 21 265 266 /* Get the first 32 128bit VSX registers */ 267 #define PTRACE_GETVSRREGS 27 268 #define PTRACE_SETVSRREGS 28 269 270 /* 271 * Get or set a debug register. The first 16 are DABR registers and the 272 * second 16 are IABR registers. 273 */ 274 #define PTRACE_GET_DEBUGREG 25 275 #define PTRACE_SET_DEBUGREG 26 276 277 /* (new) PTRACE requests using the same numbers as x86 and the same 278 * argument ordering. Additionally, they support more registers too 279 */ 280 #define PTRACE_GETREGS 12 281 #define PTRACE_SETREGS 13 282 #define PTRACE_GETFPREGS 14 283 #define PTRACE_SETFPREGS 15 284 #define PTRACE_GETREGS64 22 285 #define PTRACE_SETREGS64 23 286 287 /* (old) PTRACE requests with inverted arguments */ 288 #define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */ 289 #define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */ 290 #define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */ 291 #define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */ 292 293 /* Calls to trace a 64bit program from a 32bit program */ 294 #define PPC_PTRACE_PEEKTEXT_3264 0x95 295 #define PPC_PTRACE_PEEKDATA_3264 0x94 296 #define PPC_PTRACE_POKETEXT_3264 0x93 297 #define PPC_PTRACE_POKEDATA_3264 0x92 298 #define PPC_PTRACE_PEEKUSR_3264 0x91 299 #define PPC_PTRACE_POKEUSR_3264 0x90 300 301 #define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 302 303 #define PPC_PTRACE_GETHWDBGINFO 0x89 304 #define PPC_PTRACE_SETHWDEBUG 0x88 305 #define PPC_PTRACE_DELHWDEBUG 0x87 306 307 #ifndef __ASSEMBLY__ 308 309 struct ppc_debug_info { 310 uint32_t version; /* Only version 1 exists to date */ 311 uint32_t num_instruction_bps; 312 uint32_t num_data_bps; 313 uint32_t num_condition_regs; 314 uint32_t data_bp_alignment; 315 uint32_t sizeof_condition; /* size of the DVC register */ 316 uint64_t features; 317 }; 318 319 #endif /* __ASSEMBLY__ */ 320 321 /* 322 * features will have bits indication whether there is support for: 323 */ 324 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001 325 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002 326 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004 327 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008 328 329 #ifndef __ASSEMBLY__ 330 331 struct ppc_hw_breakpoint { 332 uint32_t version; /* currently, version must be 1 */ 333 uint32_t trigger_type; /* only some combinations allowed */ 334 uint32_t addr_mode; /* address match mode */ 335 uint32_t condition_mode; /* break/watchpoint condition flags */ 336 uint64_t addr; /* break/watchpoint address */ 337 uint64_t addr2; /* range end or mask */ 338 uint64_t condition_value; /* contents of the DVC register */ 339 }; 340 341 #endif /* __ASSEMBLY__ */ 342 343 /* 344 * Trigger Type 345 */ 346 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001 347 #define PPC_BREAKPOINT_TRIGGER_READ 0x00000002 348 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004 349 #define PPC_BREAKPOINT_TRIGGER_RW \ 350 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE) 351 352 /* 353 * Address Mode 354 */ 355 #define PPC_BREAKPOINT_MODE_EXACT 0x00000000 356 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001 357 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002 358 #define PPC_BREAKPOINT_MODE_MASK 0x00000003 359 360 /* 361 * Condition Mode 362 */ 363 #define PPC_BREAKPOINT_CONDITION_MODE 0x00000003 364 #define PPC_BREAKPOINT_CONDITION_NONE 0x00000000 365 #define PPC_BREAKPOINT_CONDITION_AND 0x00000001 366 #define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND 367 #define PPC_BREAKPOINT_CONDITION_OR 0x00000002 368 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003 369 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 370 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 371 #define PPC_BREAKPOINT_CONDITION_BE(n) \ 372 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) 373 374 #endif /* _ASM_POWERPC_PTRACE_H */ 375