1 #ifndef _ASM_POWERPC_PROCESSOR_H 2 #define _ASM_POWERPC_PROCESSOR_H 3 4 /* 5 * Copyright (C) 2001 PPC 64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <asm/reg.h> 14 15 #ifdef CONFIG_VSX 16 #define TS_FPRWIDTH 2 17 #else 18 #define TS_FPRWIDTH 1 19 #endif 20 21 #ifndef __ASSEMBLY__ 22 #include <linux/compiler.h> 23 #include <linux/cache.h> 24 #include <asm/ptrace.h> 25 #include <asm/types.h> 26 27 /* We do _not_ want to define new machine types at all, those must die 28 * in favor of using the device-tree 29 * -- BenH. 30 */ 31 32 /* PREP sub-platform types see residual.h for these */ 33 #define _PREP_Motorola 0x01 /* motorola prep */ 34 #define _PREP_Firm 0x02 /* firmworks prep */ 35 #define _PREP_IBM 0x00 /* ibm prep */ 36 #define _PREP_Bull 0x03 /* bull prep */ 37 38 /* CHRP sub-platform types. These are arbitrary */ 39 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ 40 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ 41 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ 42 #define _CHRP_briq 0x07 /* TotalImpact's briQ */ 43 44 #if defined(__KERNEL__) && defined(CONFIG_PPC32) 45 46 extern int _chrp_type; 47 48 #ifdef CONFIG_PPC_PREP 49 50 /* what kind of prep workstation we are */ 51 extern int _prep_type; 52 53 #endif /* CONFIG_PPC_PREP */ 54 55 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 56 57 /* 58 * Default implementation of macro that returns current 59 * instruction pointer ("program counter"). 60 */ 61 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 62 63 /* Macros for adjusting thread priority (hardware multi-threading) */ 64 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority") 65 #define HMT_low() asm volatile("or 1,1,1 # low priority") 66 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority") 67 #define HMT_medium() asm volatile("or 2,2,2 # medium priority") 68 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority") 69 #define HMT_high() asm volatile("or 3,3,3 # high priority") 70 71 #ifdef __KERNEL__ 72 73 struct task_struct; 74 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); 75 void release_thread(struct task_struct *); 76 77 /* Lazy FPU handling on uni-processor */ 78 extern struct task_struct *last_task_used_math; 79 extern struct task_struct *last_task_used_altivec; 80 extern struct task_struct *last_task_used_vsx; 81 extern struct task_struct *last_task_used_spe; 82 83 #ifdef CONFIG_PPC32 84 85 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START 86 #error User TASK_SIZE overlaps with KERNEL_START address 87 #endif 88 #define TASK_SIZE (CONFIG_TASK_SIZE) 89 90 /* This decides where the kernel will search for a free chunk of vm 91 * space during mmap's. 92 */ 93 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) 94 #endif 95 96 #ifdef CONFIG_PPC64 97 /* 64-bit user address space is 46-bits (64TB user VM) */ 98 #define TASK_SIZE_USER64 (0x0000400000000000UL) 99 100 /* 101 * 32-bit user address space is 4GB - 1 page 102 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT 103 */ 104 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE)) 105 106 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 107 TASK_SIZE_USER32 : TASK_SIZE_USER64) 108 #define TASK_SIZE TASK_SIZE_OF(current) 109 110 /* This decides where the kernel will search for a free chunk of vm 111 * space during mmap's. 112 */ 113 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4)) 114 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4)) 115 116 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \ 117 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) 118 #endif 119 120 #ifdef __powerpc64__ 121 122 #define STACK_TOP_USER64 TASK_SIZE_USER64 123 #define STACK_TOP_USER32 TASK_SIZE_USER32 124 125 #define STACK_TOP (is_32bit_task() ? \ 126 STACK_TOP_USER32 : STACK_TOP_USER64) 127 128 #define STACK_TOP_MAX STACK_TOP_USER64 129 130 #else /* __powerpc64__ */ 131 132 #define STACK_TOP TASK_SIZE 133 #define STACK_TOP_MAX STACK_TOP 134 135 #endif /* __powerpc64__ */ 136 137 typedef struct { 138 unsigned long seg; 139 } mm_segment_t; 140 141 #define TS_FPROFFSET 0 142 #define TS_VSRLOWOFFSET 1 143 #define TS_FPR(i) fpr[i][TS_FPROFFSET] 144 145 struct thread_struct { 146 unsigned long ksp; /* Kernel stack pointer */ 147 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ 148 149 #ifdef CONFIG_PPC64 150 unsigned long ksp_vsid; 151 #endif 152 struct pt_regs *regs; /* Pointer to saved register state */ 153 mm_segment_t fs; /* for get_fs() validation */ 154 #ifdef CONFIG_BOOKE 155 /* BookE base exception scratch space; align on cacheline */ 156 unsigned long normsave[8] ____cacheline_aligned; 157 #endif 158 #ifdef CONFIG_PPC32 159 void *pgdir; /* root of page-table tree */ 160 #endif 161 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 162 /* 163 * The following help to manage the use of Debug Control Registers 164 * om the BookE platforms. 165 */ 166 unsigned long dbcr0; 167 unsigned long dbcr1; 168 #ifdef CONFIG_BOOKE 169 unsigned long dbcr2; 170 #endif 171 /* 172 * The stored value of the DBSR register will be the value at the 173 * last debug interrupt. This register can only be read from the 174 * user (will never be written to) and has value while helping to 175 * describe the reason for the last debug trap. Torez 176 */ 177 unsigned long dbsr; 178 /* 179 * The following will contain addresses used by debug applications 180 * to help trace and trap on particular address locations. 181 * The bits in the Debug Control Registers above help define which 182 * of the following registers will contain valid data and/or addresses. 183 */ 184 unsigned long iac1; 185 unsigned long iac2; 186 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 187 unsigned long iac3; 188 unsigned long iac4; 189 #endif 190 unsigned long dac1; 191 unsigned long dac2; 192 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 193 unsigned long dvc1; 194 unsigned long dvc2; 195 #endif 196 #endif 197 /* FP and VSX 0-31 register set */ 198 double fpr[32][TS_FPRWIDTH]; 199 struct { 200 201 unsigned int pad; 202 unsigned int val; /* Floating point status */ 203 } fpscr; 204 int fpexc_mode; /* floating-point exception mode */ 205 unsigned int align_ctl; /* alignment handling control */ 206 #ifdef CONFIG_PPC64 207 unsigned long start_tb; /* Start purr when proc switched in */ 208 unsigned long accum_tb; /* Total accumilated purr for process */ 209 #ifdef CONFIG_HAVE_HW_BREAKPOINT 210 struct perf_event *ptrace_bps[HBP_NUM]; 211 /* 212 * Helps identify source of single-step exception and subsequent 213 * hw-breakpoint enablement 214 */ 215 struct perf_event *last_hit_ubp; 216 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 217 #endif 218 unsigned long dabr; /* Data address breakpoint register */ 219 unsigned long dabrx; /* ... extension */ 220 unsigned long trap_nr; /* last trap # on this thread */ 221 #ifdef CONFIG_ALTIVEC 222 /* Complete AltiVec register set */ 223 vector128 vr[32] __attribute__((aligned(16))); 224 /* AltiVec status */ 225 vector128 vscr __attribute__((aligned(16))); 226 unsigned long vrsave; 227 int used_vr; /* set if process has used altivec */ 228 #endif /* CONFIG_ALTIVEC */ 229 #ifdef CONFIG_VSX 230 /* VSR status */ 231 int used_vsr; /* set if process has used altivec */ 232 #endif /* CONFIG_VSX */ 233 #ifdef CONFIG_SPE 234 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 235 u64 acc; /* Accumulator */ 236 unsigned long spefscr; /* SPE & eFP status */ 237 int used_spe; /* set if process has used spe */ 238 #endif /* CONFIG_SPE */ 239 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 240 void* kvm_shadow_vcpu; /* KVM internal data */ 241 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 242 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 243 struct kvm_vcpu *kvm_vcpu; 244 #endif 245 #ifdef CONFIG_PPC64 246 unsigned long dscr; 247 int dscr_inherit; 248 #endif 249 }; 250 251 #define ARCH_MIN_TASKALIGN 16 252 253 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 254 #define INIT_SP_LIMIT \ 255 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack) 256 257 #ifdef CONFIG_SPE 258 #define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 259 #else 260 #define SPEFSCR_INIT 261 #endif 262 263 #ifdef CONFIG_PPC32 264 #define INIT_THREAD { \ 265 .ksp = INIT_SP, \ 266 .ksp_limit = INIT_SP_LIMIT, \ 267 .fs = KERNEL_DS, \ 268 .pgdir = swapper_pg_dir, \ 269 .fpexc_mode = MSR_FE0 | MSR_FE1, \ 270 SPEFSCR_INIT \ 271 } 272 #else 273 #define INIT_THREAD { \ 274 .ksp = INIT_SP, \ 275 .ksp_limit = INIT_SP_LIMIT, \ 276 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ 277 .fs = KERNEL_DS, \ 278 .fpr = {{0}}, \ 279 .fpscr = { .val = 0, }, \ 280 .fpexc_mode = 0, \ 281 } 282 #endif 283 284 /* 285 * Return saved PC of a blocked thread. For now, this is the "user" PC 286 */ 287 #define thread_saved_pc(tsk) \ 288 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 289 290 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs) 291 292 unsigned long get_wchan(struct task_struct *p); 293 294 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 295 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) 296 297 /* Get/set floating-point exception mode */ 298 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) 299 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) 300 301 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); 302 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); 303 304 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr)) 305 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) 306 307 extern int get_endian(struct task_struct *tsk, unsigned long adr); 308 extern int set_endian(struct task_struct *tsk, unsigned int val); 309 310 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr)) 311 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 312 313 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); 314 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); 315 316 static inline unsigned int __unpack_fe01(unsigned long msr_bits) 317 { 318 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); 319 } 320 321 static inline unsigned long __pack_fe01(unsigned int fpmode) 322 { 323 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); 324 } 325 326 #ifdef CONFIG_PPC64 327 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) 328 #else 329 #define cpu_relax() barrier() 330 #endif 331 332 /* Check that a certain kernel stack pointer is valid in task_struct p */ 333 int validate_sp(unsigned long sp, struct task_struct *p, 334 unsigned long nbytes); 335 336 /* 337 * Prefetch macros. 338 */ 339 #define ARCH_HAS_PREFETCH 340 #define ARCH_HAS_PREFETCHW 341 #define ARCH_HAS_SPINLOCK_PREFETCH 342 343 static inline void prefetch(const void *x) 344 { 345 if (unlikely(!x)) 346 return; 347 348 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); 349 } 350 351 static inline void prefetchw(const void *x) 352 { 353 if (unlikely(!x)) 354 return; 355 356 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); 357 } 358 359 #define spin_lock_prefetch(x) prefetchw(x) 360 361 #ifdef CONFIG_PPC64 362 #define HAVE_ARCH_PICK_MMAP_LAYOUT 363 #endif 364 365 #ifdef CONFIG_PPC64 366 static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32) 367 { 368 unsigned long sp; 369 370 if (is_32) 371 sp = regs->gpr[1] & 0x0ffffffffUL; 372 else 373 sp = regs->gpr[1]; 374 375 return sp; 376 } 377 #else 378 static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32) 379 { 380 return regs->gpr[1]; 381 } 382 #endif 383 384 extern unsigned long cpuidle_disable; 385 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF}; 386 387 extern int powersave_nap; /* set if nap mode can be used in idle loop */ 388 extern void power7_nap(void); 389 390 #ifdef CONFIG_PSERIES_IDLE 391 extern void update_smt_snooze_delay(int cpu, int residency); 392 #else 393 static inline void update_smt_snooze_delay(int cpu, int residency) {} 394 #endif 395 396 extern void flush_instruction_cache(void); 397 extern void hard_reset_now(void); 398 extern void poweroff_now(void); 399 extern int fix_alignment(struct pt_regs *); 400 extern void cvt_fd(float *from, double *to); 401 extern void cvt_df(double *from, float *to); 402 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 403 404 #ifdef CONFIG_PPC64 405 /* 406 * We handle most unaligned accesses in hardware. On the other hand 407 * unaligned DMA can be very expensive on some ppc64 IO chips (it does 408 * powers of 2 writes until it reaches sufficient alignment). 409 * 410 * Based on this we disable the IP header alignment in network drivers. 411 */ 412 #define NET_IP_ALIGN 0 413 #endif 414 415 #endif /* __KERNEL__ */ 416 #endif /* __ASSEMBLY__ */ 417 #endif /* _ASM_POWERPC_PROCESSOR_H */ 418