1 #ifndef _ASM_POWERPC_PROCESSOR_H 2 #define _ASM_POWERPC_PROCESSOR_H 3 4 /* 5 * Copyright (C) 2001 PPC 64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <asm/reg.h> 14 15 #ifdef CONFIG_VSX 16 #define TS_FPRWIDTH 2 17 18 #ifdef __BIG_ENDIAN__ 19 #define TS_FPROFFSET 0 20 #define TS_VSRLOWOFFSET 1 21 #else 22 #define TS_FPROFFSET 1 23 #define TS_VSRLOWOFFSET 0 24 #endif 25 26 #else 27 #define TS_FPRWIDTH 1 28 #define TS_FPROFFSET 0 29 #endif 30 31 #ifdef CONFIG_PPC64 32 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */ 33 #define PPR_PRIORITY 3 34 #ifdef __ASSEMBLY__ 35 #define INIT_PPR (PPR_PRIORITY << 50) 36 #else 37 #define INIT_PPR ((u64)PPR_PRIORITY << 50) 38 #endif /* __ASSEMBLY__ */ 39 #endif /* CONFIG_PPC64 */ 40 41 #ifndef __ASSEMBLY__ 42 #include <linux/compiler.h> 43 #include <linux/cache.h> 44 #include <asm/ptrace.h> 45 #include <asm/types.h> 46 #include <asm/hw_breakpoint.h> 47 48 /* We do _not_ want to define new machine types at all, those must die 49 * in favor of using the device-tree 50 * -- BenH. 51 */ 52 53 /* PREP sub-platform types. Unused */ 54 #define _PREP_Motorola 0x01 /* motorola prep */ 55 #define _PREP_Firm 0x02 /* firmworks prep */ 56 #define _PREP_IBM 0x00 /* ibm prep */ 57 #define _PREP_Bull 0x03 /* bull prep */ 58 59 /* CHRP sub-platform types. These are arbitrary */ 60 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ 61 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ 62 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ 63 #define _CHRP_briq 0x07 /* TotalImpact's briQ */ 64 65 #if defined(__KERNEL__) && defined(CONFIG_PPC32) 66 67 extern int _chrp_type; 68 69 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */ 70 71 /* 72 * Default implementation of macro that returns current 73 * instruction pointer ("program counter"). 74 */ 75 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 76 77 /* Macros for adjusting thread priority (hardware multi-threading) */ 78 #define HMT_very_low() asm volatile("or 31,31,31 # very low priority") 79 #define HMT_low() asm volatile("or 1,1,1 # low priority") 80 #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority") 81 #define HMT_medium() asm volatile("or 2,2,2 # medium priority") 82 #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority") 83 #define HMT_high() asm volatile("or 3,3,3 # high priority") 84 85 #ifdef __KERNEL__ 86 87 struct task_struct; 88 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); 89 void release_thread(struct task_struct *); 90 91 #ifdef CONFIG_PPC32 92 93 #if CONFIG_TASK_SIZE > CONFIG_KERNEL_START 94 #error User TASK_SIZE overlaps with KERNEL_START address 95 #endif 96 #define TASK_SIZE (CONFIG_TASK_SIZE) 97 98 /* This decides where the kernel will search for a free chunk of vm 99 * space during mmap's. 100 */ 101 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) 102 #endif 103 104 #ifdef CONFIG_PPC64 105 /* 106 * 64-bit user address space can have multiple limits 107 * For now supported values are: 108 */ 109 #define TASK_SIZE_64TB (0x0000400000000000UL) 110 #define TASK_SIZE_128TB (0x0000800000000000UL) 111 #define TASK_SIZE_512TB (0x0002000000000000UL) 112 113 #ifdef CONFIG_PPC_BOOK3S_64 114 /* 115 * Max value currently used: 116 */ 117 #define TASK_SIZE_USER64 TASK_SIZE_512TB 118 #else 119 #define TASK_SIZE_USER64 TASK_SIZE_64TB 120 #endif 121 122 /* 123 * 32-bit user address space is 4GB - 1 page 124 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT 125 */ 126 #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE)) 127 128 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 129 TASK_SIZE_USER32 : TASK_SIZE_USER64) 130 #define TASK_SIZE TASK_SIZE_OF(current) 131 /* This decides where the kernel will search for a free chunk of vm 132 * space during mmap's. 133 */ 134 #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4)) 135 #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_128TB / 4)) 136 137 #define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \ 138 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) 139 #endif 140 141 /* 142 * Initial task size value for user applications. For book3s 64 we start 143 * with 128TB and conditionally enable upto 512TB 144 */ 145 #ifdef CONFIG_PPC_BOOK3S_64 146 #define DEFAULT_MAP_WINDOW ((is_32bit_task()) ? \ 147 TASK_SIZE_USER32 : TASK_SIZE_128TB) 148 #else 149 #define DEFAULT_MAP_WINDOW TASK_SIZE 150 #endif 151 152 #ifdef __powerpc64__ 153 154 /* Limit stack to 128TB */ 155 #define STACK_TOP_USER64 TASK_SIZE_128TB 156 #define STACK_TOP_USER32 TASK_SIZE_USER32 157 158 #define STACK_TOP (is_32bit_task() ? \ 159 STACK_TOP_USER32 : STACK_TOP_USER64) 160 161 #define STACK_TOP_MAX TASK_SIZE_USER64 162 163 #else /* __powerpc64__ */ 164 165 #define STACK_TOP TASK_SIZE 166 #define STACK_TOP_MAX STACK_TOP 167 168 #endif /* __powerpc64__ */ 169 170 typedef struct { 171 unsigned long seg; 172 } mm_segment_t; 173 174 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET] 175 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET] 176 177 /* FP and VSX 0-31 register set */ 178 struct thread_fp_state { 179 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16))); 180 u64 fpscr; /* Floating point status */ 181 }; 182 183 /* Complete AltiVec register set including VSCR */ 184 struct thread_vr_state { 185 vector128 vr[32] __attribute__((aligned(16))); 186 vector128 vscr __attribute__((aligned(16))); 187 }; 188 189 struct debug_reg { 190 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 191 /* 192 * The following help to manage the use of Debug Control Registers 193 * om the BookE platforms. 194 */ 195 uint32_t dbcr0; 196 uint32_t dbcr1; 197 #ifdef CONFIG_BOOKE 198 uint32_t dbcr2; 199 #endif 200 /* 201 * The stored value of the DBSR register will be the value at the 202 * last debug interrupt. This register can only be read from the 203 * user (will never be written to) and has value while helping to 204 * describe the reason for the last debug trap. Torez 205 */ 206 uint32_t dbsr; 207 /* 208 * The following will contain addresses used by debug applications 209 * to help trace and trap on particular address locations. 210 * The bits in the Debug Control Registers above help define which 211 * of the following registers will contain valid data and/or addresses. 212 */ 213 unsigned long iac1; 214 unsigned long iac2; 215 #if CONFIG_PPC_ADV_DEBUG_IACS > 2 216 unsigned long iac3; 217 unsigned long iac4; 218 #endif 219 unsigned long dac1; 220 unsigned long dac2; 221 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 222 unsigned long dvc1; 223 unsigned long dvc2; 224 #endif 225 #endif 226 }; 227 228 struct thread_struct { 229 unsigned long ksp; /* Kernel stack pointer */ 230 231 #ifdef CONFIG_PPC64 232 unsigned long ksp_vsid; 233 #endif 234 struct pt_regs *regs; /* Pointer to saved register state */ 235 mm_segment_t fs; /* for get_fs() validation */ 236 #ifdef CONFIG_BOOKE 237 /* BookE base exception scratch space; align on cacheline */ 238 unsigned long normsave[8] ____cacheline_aligned; 239 #endif 240 #ifdef CONFIG_PPC32 241 void *pgdir; /* root of page-table tree */ 242 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */ 243 #endif 244 /* Debug Registers */ 245 struct debug_reg debug; 246 struct thread_fp_state fp_state; 247 struct thread_fp_state *fp_save_area; 248 int fpexc_mode; /* floating-point exception mode */ 249 unsigned int align_ctl; /* alignment handling control */ 250 #ifdef CONFIG_PPC64 251 unsigned long start_tb; /* Start purr when proc switched in */ 252 unsigned long accum_tb; /* Total accumulated purr for process */ 253 #endif 254 #ifdef CONFIG_HAVE_HW_BREAKPOINT 255 struct perf_event *ptrace_bps[HBP_NUM]; 256 /* 257 * Helps identify source of single-step exception and subsequent 258 * hw-breakpoint enablement 259 */ 260 struct perf_event *last_hit_ubp; 261 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 262 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */ 263 unsigned long trap_nr; /* last trap # on this thread */ 264 u8 load_fp; 265 #ifdef CONFIG_ALTIVEC 266 u8 load_vec; 267 struct thread_vr_state vr_state; 268 struct thread_vr_state *vr_save_area; 269 unsigned long vrsave; 270 int used_vr; /* set if process has used altivec */ 271 #endif /* CONFIG_ALTIVEC */ 272 #ifdef CONFIG_VSX 273 /* VSR status */ 274 int used_vsr; /* set if process has used VSX */ 275 #endif /* CONFIG_VSX */ 276 #ifdef CONFIG_SPE 277 unsigned long evr[32]; /* upper 32-bits of SPE regs */ 278 u64 acc; /* Accumulator */ 279 unsigned long spefscr; /* SPE & eFP status */ 280 unsigned long spefscr_last; /* SPEFSCR value on last prctl 281 call or trap return */ 282 int used_spe; /* set if process has used spe */ 283 #endif /* CONFIG_SPE */ 284 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 285 u8 load_tm; 286 u64 tm_tfhar; /* Transaction fail handler addr */ 287 u64 tm_texasr; /* Transaction exception & summary */ 288 u64 tm_tfiar; /* Transaction fail instr address reg */ 289 struct pt_regs ckpt_regs; /* Checkpointed registers */ 290 291 unsigned long tm_tar; 292 unsigned long tm_ppr; 293 unsigned long tm_dscr; 294 295 /* 296 * Checkpointed FP and VSX 0-31 register set. 297 * 298 * When a transaction is active/signalled/scheduled etc., *regs is the 299 * most recent set of/speculated GPRs with ckpt_regs being the older 300 * checkpointed regs to which we roll back if transaction aborts. 301 * 302 * These are analogous to how ckpt_regs and pt_regs work 303 */ 304 struct thread_fp_state ckfp_state; /* Checkpointed FP state */ 305 struct thread_vr_state ckvr_state; /* Checkpointed VR state */ 306 unsigned long ckvrsave; /* Checkpointed VRSAVE */ 307 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 308 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 309 void* kvm_shadow_vcpu; /* KVM internal data */ 310 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */ 311 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 312 struct kvm_vcpu *kvm_vcpu; 313 #endif 314 #ifdef CONFIG_PPC64 315 unsigned long dscr; 316 unsigned long fscr; 317 /* 318 * This member element dscr_inherit indicates that the process 319 * has explicitly attempted and changed the DSCR register value 320 * for itself. Hence kernel wont use the default CPU DSCR value 321 * contained in the PACA structure anymore during process context 322 * switch. Once this variable is set, this behaviour will also be 323 * inherited to all the children of this process from that point 324 * onwards. 325 */ 326 int dscr_inherit; 327 unsigned long ppr; /* used to save/restore SMT priority */ 328 #endif 329 #ifdef CONFIG_PPC_BOOK3S_64 330 unsigned long tar; 331 unsigned long ebbrr; 332 unsigned long ebbhr; 333 unsigned long bescr; 334 unsigned long siar; 335 unsigned long sdar; 336 unsigned long sier; 337 unsigned long mmcr2; 338 unsigned mmcr0; 339 unsigned used_ebb; 340 #endif 341 }; 342 343 #define ARCH_MIN_TASKALIGN 16 344 345 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) 346 #define INIT_SP_LIMIT \ 347 (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack) 348 349 #ifdef CONFIG_SPE 350 #define SPEFSCR_INIT \ 351 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \ 352 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, 353 #else 354 #define SPEFSCR_INIT 355 #endif 356 357 #ifdef CONFIG_PPC32 358 #define INIT_THREAD { \ 359 .ksp = INIT_SP, \ 360 .ksp_limit = INIT_SP_LIMIT, \ 361 .fs = KERNEL_DS, \ 362 .pgdir = swapper_pg_dir, \ 363 .fpexc_mode = MSR_FE0 | MSR_FE1, \ 364 SPEFSCR_INIT \ 365 } 366 #else 367 #define INIT_THREAD { \ 368 .ksp = INIT_SP, \ 369 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ 370 .fs = KERNEL_DS, \ 371 .fpexc_mode = 0, \ 372 .ppr = INIT_PPR, \ 373 .fscr = FSCR_TAR | FSCR_EBB \ 374 } 375 #endif 376 377 /* 378 * Return saved PC of a blocked thread. For now, this is the "user" PC 379 */ 380 #define thread_saved_pc(tsk) \ 381 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 382 383 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs) 384 385 unsigned long get_wchan(struct task_struct *p); 386 387 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) 388 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) 389 390 /* Get/set floating-point exception mode */ 391 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) 392 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) 393 394 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); 395 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); 396 397 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr)) 398 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val)) 399 400 extern int get_endian(struct task_struct *tsk, unsigned long adr); 401 extern int set_endian(struct task_struct *tsk, unsigned int val); 402 403 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr)) 404 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 405 406 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr); 407 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); 408 409 extern void load_fp_state(struct thread_fp_state *fp); 410 extern void store_fp_state(struct thread_fp_state *fp); 411 extern void load_vr_state(struct thread_vr_state *vr); 412 extern void store_vr_state(struct thread_vr_state *vr); 413 414 static inline unsigned int __unpack_fe01(unsigned long msr_bits) 415 { 416 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); 417 } 418 419 static inline unsigned long __pack_fe01(unsigned int fpmode) 420 { 421 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); 422 } 423 424 #ifdef CONFIG_PPC64 425 #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) 426 #else 427 #define cpu_relax() barrier() 428 #endif 429 430 /* Check that a certain kernel stack pointer is valid in task_struct p */ 431 int validate_sp(unsigned long sp, struct task_struct *p, 432 unsigned long nbytes); 433 434 /* 435 * Prefetch macros. 436 */ 437 #define ARCH_HAS_PREFETCH 438 #define ARCH_HAS_PREFETCHW 439 #define ARCH_HAS_SPINLOCK_PREFETCH 440 441 static inline void prefetch(const void *x) 442 { 443 if (unlikely(!x)) 444 return; 445 446 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); 447 } 448 449 static inline void prefetchw(const void *x) 450 { 451 if (unlikely(!x)) 452 return; 453 454 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); 455 } 456 457 #define spin_lock_prefetch(x) prefetchw(x) 458 459 #define HAVE_ARCH_PICK_MMAP_LAYOUT 460 461 #ifdef CONFIG_PPC64 462 static inline unsigned long get_clean_sp(unsigned long sp, int is_32) 463 { 464 if (is_32) 465 return sp & 0x0ffffffffUL; 466 return sp; 467 } 468 #else 469 static inline unsigned long get_clean_sp(unsigned long sp, int is_32) 470 { 471 return sp; 472 } 473 #endif 474 475 extern unsigned long cpuidle_disable; 476 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF}; 477 478 extern int powersave_nap; /* set if nap mode can be used in idle loop */ 479 extern unsigned long power7_nap(int check_irq); 480 extern unsigned long power7_sleep(void); 481 extern unsigned long power7_winkle(void); 482 extern unsigned long power9_idle_stop(unsigned long stop_psscr_val, 483 unsigned long stop_psscr_mask); 484 485 extern void flush_instruction_cache(void); 486 extern void hard_reset_now(void); 487 extern void poweroff_now(void); 488 extern int fix_alignment(struct pt_regs *); 489 extern void cvt_fd(float *from, double *to); 490 extern void cvt_df(double *from, float *to); 491 extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); 492 493 #ifdef CONFIG_PPC64 494 /* 495 * We handle most unaligned accesses in hardware. On the other hand 496 * unaligned DMA can be very expensive on some ppc64 IO chips (it does 497 * powers of 2 writes until it reaches sufficient alignment). 498 * 499 * Based on this we disable the IP header alignment in network drivers. 500 */ 501 #define NET_IP_ALIGN 0 502 #endif 503 504 #endif /* __KERNEL__ */ 505 #endif /* __ASSEMBLY__ */ 506 #endif /* _ASM_POWERPC_PROCESSOR_H */ 507