1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/init.h> 8 #include <linux/stringify.h> 9 #include <asm/asm-compat.h> 10 #include <asm/processor.h> 11 #include <asm/ppc-opcode.h> 12 #include <asm/firmware.h> 13 14 #ifndef __ASSEMBLY__ 15 #error __FILE__ should only be used in assembler files 16 #else 17 18 #define SZL (BITS_PER_LONG/8) 19 20 /* 21 * Stuff for accurate CPU time accounting. 22 * These macros handle transitions between user and system state 23 * in exception entry and exit and accumulate time to the 24 * user_time and system_time fields in the paca. 25 */ 26 27 #ifndef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 28 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 29 #define ACCOUNT_CPU_USER_EXIT(ra, rb) 30 #define ACCOUNT_STOLEN_TIME 31 #else 32 #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 33 MFTB(ra); /* get timebase */ \ 34 ld rb,PACA_STARTTIME_USER(r13); \ 35 std ra,PACA_STARTTIME(r13); \ 36 subf rb,rb,ra; /* subtract start value */ \ 37 ld ra,PACA_USER_TIME(r13); \ 38 add ra,ra,rb; /* add on to user time */ \ 39 std ra,PACA_USER_TIME(r13); \ 40 41 #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 42 MFTB(ra); /* get timebase */ \ 43 ld rb,PACA_STARTTIME(r13); \ 44 std ra,PACA_STARTTIME_USER(r13); \ 45 subf rb,rb,ra; /* subtract start value */ \ 46 ld ra,PACA_SYSTEM_TIME(r13); \ 47 add ra,ra,rb; /* add on to system time */ \ 48 std ra,PACA_SYSTEM_TIME(r13) 49 50 #ifdef CONFIG_PPC_SPLPAR 51 #define ACCOUNT_STOLEN_TIME \ 52 BEGIN_FW_FTR_SECTION; \ 53 beq 33f; \ 54 /* from user - see if there are any DTL entries to process */ \ 55 ld r10,PACALPPACAPTR(r13); /* get ptr to VPA */ \ 56 ld r11,PACA_DTL_RIDX(r13); /* get log read index */ \ 57 addi r10,r10,LPPACA_DTLIDX; \ 58 LDX_BE r10,0,r10; /* get log write index */ \ 59 cmpd cr1,r11,r10; \ 60 beq+ cr1,33f; \ 61 bl .accumulate_stolen_time; \ 62 ld r12,_MSR(r1); \ 63 andi. r10,r12,MSR_PR; /* Restore cr0 (coming from user) */ \ 64 33: \ 65 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) 66 67 #else /* CONFIG_PPC_SPLPAR */ 68 #define ACCOUNT_STOLEN_TIME 69 70 #endif /* CONFIG_PPC_SPLPAR */ 71 72 #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */ 73 74 /* 75 * Macros for storing registers into and loading registers from 76 * exception frames. 77 */ 78 #ifdef __powerpc64__ 79 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 80 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 81 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 82 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 83 #else 84 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 85 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 86 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 87 SAVE_10GPRS(22, base) 88 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 89 REST_10GPRS(22, base) 90 #endif 91 92 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 93 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 94 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 95 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 96 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 97 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 98 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 99 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 100 101 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 102 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 103 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 104 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 105 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 106 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 107 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 108 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 109 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 110 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 111 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 112 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 113 114 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 115 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 116 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 117 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 118 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 119 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 120 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 121 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 122 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 123 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 124 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 125 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 126 127 #ifdef __BIG_ENDIAN__ 128 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 129 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 130 #else 131 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 132 STXVD2X(n,b,base); \ 133 XXSWAPD(n,n) 134 135 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 136 XXSWAPD(n,n) 137 #endif 138 /* Save the lower 32 VSRs in the thread VSR region */ 139 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 140 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 141 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 142 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 143 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 144 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 145 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 146 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 147 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 148 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 149 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 150 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 151 152 /* 153 * b = base register for addressing, o = base offset from register of 1st EVR 154 * n = first EVR, s = scratch 155 */ 156 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 157 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 158 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 159 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 160 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 161 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 162 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 163 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 164 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 165 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 166 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 167 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 168 169 /* Macros to adjust thread priority for hardware multithreading */ 170 #define HMT_VERY_LOW or 31,31,31 # very low priority 171 #define HMT_LOW or 1,1,1 172 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 173 #define HMT_MEDIUM or 2,2,2 174 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 175 #define HMT_HIGH or 3,3,3 176 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 177 178 #ifdef CONFIG_PPC64 179 #define ULONG_SIZE 8 180 #else 181 #define ULONG_SIZE 4 182 #endif 183 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 184 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 185 186 #ifdef __KERNEL__ 187 #ifdef CONFIG_PPC64 188 189 #define STACKFRAMESIZE 256 190 #define __STK_REG(i) (112 + ((i)-14)*8) 191 #define STK_REG(i) __STK_REG(__REG_##i) 192 193 #define __STK_PARAM(i) (48 + ((i)-3)*8) 194 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 195 196 #define XGLUE(a,b) a##b 197 #define GLUE(a,b) XGLUE(a,b) 198 199 #define _GLOBAL(name) \ 200 .section ".text"; \ 201 .align 2 ; \ 202 .globl name; \ 203 .globl GLUE(.,name); \ 204 .section ".opd","aw"; \ 205 name: \ 206 .quad GLUE(.,name); \ 207 .quad .TOC.@tocbase; \ 208 .quad 0; \ 209 .previous; \ 210 .type GLUE(.,name),@function; \ 211 GLUE(.,name): 212 213 #define _INIT_GLOBAL(name) \ 214 __REF; \ 215 .align 2 ; \ 216 .globl name; \ 217 .globl GLUE(.,name); \ 218 .section ".opd","aw"; \ 219 name: \ 220 .quad GLUE(.,name); \ 221 .quad .TOC.@tocbase; \ 222 .quad 0; \ 223 .previous; \ 224 .type GLUE(.,name),@function; \ 225 GLUE(.,name): 226 227 #define _KPROBE(name) \ 228 .section ".kprobes.text","a"; \ 229 .align 2 ; \ 230 .globl name; \ 231 .globl GLUE(.,name); \ 232 .section ".opd","aw"; \ 233 name: \ 234 .quad GLUE(.,name); \ 235 .quad .TOC.@tocbase; \ 236 .quad 0; \ 237 .previous; \ 238 .type GLUE(.,name),@function; \ 239 GLUE(.,name): 240 241 #define _STATIC(name) \ 242 .section ".text"; \ 243 .align 2 ; \ 244 .section ".opd","aw"; \ 245 name: \ 246 .quad GLUE(.,name); \ 247 .quad .TOC.@tocbase; \ 248 .quad 0; \ 249 .previous; \ 250 .type GLUE(.,name),@function; \ 251 GLUE(.,name): 252 253 #define _INIT_STATIC(name) \ 254 __REF; \ 255 .align 2 ; \ 256 .section ".opd","aw"; \ 257 name: \ 258 .quad GLUE(.,name); \ 259 .quad .TOC.@tocbase; \ 260 .quad 0; \ 261 .previous; \ 262 .type GLUE(.,name),@function; \ 263 GLUE(.,name): 264 265 #else /* 32-bit */ 266 267 #define _ENTRY(n) \ 268 .globl n; \ 269 n: 270 271 #define _GLOBAL(n) \ 272 .text; \ 273 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 274 .globl n; \ 275 n: 276 277 #define _KPROBE(n) \ 278 .section ".kprobes.text","a"; \ 279 .globl n; \ 280 n: 281 282 #endif 283 284 /* 285 * LOAD_REG_IMMEDIATE(rn, expr) 286 * Loads the value of the constant expression 'expr' into register 'rn' 287 * using immediate instructions only. Use this when it's important not 288 * to reference other data (i.e. on ppc64 when the TOC pointer is not 289 * valid) and when 'expr' is a constant or absolute address. 290 * 291 * LOAD_REG_ADDR(rn, name) 292 * Loads the address of label 'name' into register 'rn'. Use this when 293 * you don't particularly need immediate instructions only, but you need 294 * the whole address in one register (e.g. it's a structure address and 295 * you want to access various offsets within it). On ppc32 this is 296 * identical to LOAD_REG_IMMEDIATE. 297 * 298 * LOAD_REG_ADDRBASE(rn, name) 299 * ADDROFF(name) 300 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 301 * register 'rn'. ADDROFF(name) returns the remainder of the address as 302 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 303 * in size, so is suitable for use directly as an offset in load and store 304 * instructions. Use this when loading/storing a single word or less as: 305 * LOAD_REG_ADDRBASE(rX, name) 306 * ld rY,ADDROFF(name)(rX) 307 */ 308 #ifdef __powerpc64__ 309 #define LOAD_REG_IMMEDIATE(reg,expr) \ 310 lis reg,(expr)@highest; \ 311 ori reg,reg,(expr)@higher; \ 312 rldicr reg,reg,32,31; \ 313 oris reg,reg,(expr)@h; \ 314 ori reg,reg,(expr)@l; 315 316 #define LOAD_REG_ADDR(reg,name) \ 317 ld reg,name@got(r2) 318 319 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 320 #define ADDROFF(name) 0 321 322 /* offsets for stack frame layout */ 323 #define LRSAVE 16 324 325 #else /* 32-bit */ 326 327 #define LOAD_REG_IMMEDIATE(reg,expr) \ 328 lis reg,(expr)@ha; \ 329 addi reg,reg,(expr)@l; 330 331 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 332 333 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 334 #define ADDROFF(name) name@l 335 336 /* offsets for stack frame layout */ 337 #define LRSAVE 4 338 339 #endif 340 341 /* various errata or part fixups */ 342 #ifdef CONFIG_PPC601_SYNC_FIX 343 #define SYNC \ 344 BEGIN_FTR_SECTION \ 345 sync; \ 346 isync; \ 347 END_FTR_SECTION_IFSET(CPU_FTR_601) 348 #define SYNC_601 \ 349 BEGIN_FTR_SECTION \ 350 sync; \ 351 END_FTR_SECTION_IFSET(CPU_FTR_601) 352 #define ISYNC_601 \ 353 BEGIN_FTR_SECTION \ 354 isync; \ 355 END_FTR_SECTION_IFSET(CPU_FTR_601) 356 #else 357 #define SYNC 358 #define SYNC_601 359 #define ISYNC_601 360 #endif 361 362 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 363 #define MFTB(dest) \ 364 90: mfspr dest, SPRN_TBRL; \ 365 BEGIN_FTR_SECTION_NESTED(96); \ 366 cmpwi dest,0; \ 367 beq- 90b; \ 368 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 369 #else 370 #define MFTB(dest) mfspr dest, SPRN_TBRL 371 #endif 372 373 #ifndef CONFIG_SMP 374 #define TLBSYNC 375 #else /* CONFIG_SMP */ 376 /* tlbsync is not implemented on 601 */ 377 #define TLBSYNC \ 378 BEGIN_FTR_SECTION \ 379 tlbsync; \ 380 sync; \ 381 END_FTR_SECTION_IFCLR(CPU_FTR_601) 382 #endif 383 384 #ifdef CONFIG_PPC64 385 #define MTOCRF(FXM, RS) \ 386 BEGIN_FTR_SECTION_NESTED(848); \ 387 mtcrf (FXM), RS; \ 388 FTR_SECTION_ELSE_NESTED(848); \ 389 mtocrf (FXM), RS; \ 390 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 391 392 /* 393 * PPR restore macros used in entry_64.S 394 * Used for P7 or later processors 395 */ 396 #define HMT_MEDIUM_LOW_HAS_PPR \ 397 BEGIN_FTR_SECTION_NESTED(944) \ 398 HMT_MEDIUM_LOW; \ 399 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,944) 400 401 #define SET_DEFAULT_THREAD_PPR(ra, rb) \ 402 BEGIN_FTR_SECTION_NESTED(945) \ 403 lis ra,INIT_PPR@highest; /* default ppr=3 */ \ 404 ld rb,PACACURRENT(r13); \ 405 sldi ra,ra,32; /* 11- 13 bits are used for ppr */ \ 406 std ra,TASKTHREADPPR(rb); \ 407 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945) 408 409 #endif 410 411 /* 412 * This instruction is not implemented on the PPC 603 or 601; however, on 413 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 414 * All of these instructions exist in the 8xx, they have magical powers, 415 * and they must be used. 416 */ 417 418 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 419 #define tlbia \ 420 li r4,1024; \ 421 mtctr r4; \ 422 lis r4,KERNELBASE@h; \ 423 0: tlbie r4; \ 424 addi r4,r4,0x1000; \ 425 bdnz 0b 426 #endif 427 428 429 #ifdef CONFIG_IBM440EP_ERR42 430 #define PPC440EP_ERR42 isync 431 #else 432 #define PPC440EP_ERR42 433 #endif 434 435 /* The following stops all load and store data streams associated with stream 436 * ID (ie. streams created explicitly). The embedded and server mnemonics for 437 * dcbt are different so we use machine "power4" here explicitly. 438 */ 439 #define DCBT_STOP_ALL_STREAM_IDS(scratch) \ 440 .machine push ; \ 441 .machine "power4" ; \ 442 lis scratch,0x60000000@h; \ 443 dcbt r0,scratch,0b01010; \ 444 .machine pop 445 446 /* 447 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 448 * keep the address intact to be compatible with code shared with 449 * 32-bit classic. 450 * 451 * On the other hand, I find it useful to have them behave as expected 452 * by their name (ie always do the addition) on 64-bit BookE 453 */ 454 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 455 #define toreal(rd) 456 #define fromreal(rd) 457 458 /* 459 * We use addis to ensure compatibility with the "classic" ppc versions of 460 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 461 * converting the address in r0, and so this version has to do that too 462 * (i.e. set register rd to 0 when rs == 0). 463 */ 464 #define tophys(rd,rs) \ 465 addis rd,rs,0 466 467 #define tovirt(rd,rs) \ 468 addis rd,rs,0 469 470 #elif defined(CONFIG_PPC64) 471 #define toreal(rd) /* we can access c000... in real mode */ 472 #define fromreal(rd) 473 474 #define tophys(rd,rs) \ 475 clrldi rd,rs,2 476 477 #define tovirt(rd,rs) \ 478 rotldi rd,rs,16; \ 479 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 480 rotldi rd,rd,48 481 #else 482 /* 483 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 484 * physical base address of RAM at compile time. 485 */ 486 #define toreal(rd) tophys(rd,rd) 487 #define fromreal(rd) tovirt(rd,rd) 488 489 #define tophys(rd,rs) \ 490 0: addis rd,rs,-PAGE_OFFSET@h; \ 491 .section ".vtop_fixup","aw"; \ 492 .align 1; \ 493 .long 0b; \ 494 .previous 495 496 #define tovirt(rd,rs) \ 497 0: addis rd,rs,PAGE_OFFSET@h; \ 498 .section ".ptov_fixup","aw"; \ 499 .align 1; \ 500 .long 0b; \ 501 .previous 502 #endif 503 504 #ifdef CONFIG_PPC_BOOK3S_64 505 #define RFI rfid 506 #define MTMSRD(r) mtmsrd r 507 #define MTMSR_EERI(reg) mtmsrd reg,1 508 #else 509 #define FIX_SRR1(ra, rb) 510 #ifndef CONFIG_40x 511 #define RFI rfi 512 #else 513 #define RFI rfi; b . /* Prevent prefetch past rfi */ 514 #endif 515 #define MTMSRD(r) mtmsr r 516 #define MTMSR_EERI(reg) mtmsr reg 517 #define CLR_TOP32(r) 518 #endif 519 520 #endif /* __KERNEL__ */ 521 522 /* The boring bits... */ 523 524 /* Condition Register Bit Fields */ 525 526 #define cr0 0 527 #define cr1 1 528 #define cr2 2 529 #define cr3 3 530 #define cr4 4 531 #define cr5 5 532 #define cr6 6 533 #define cr7 7 534 535 536 /* 537 * General Purpose Registers (GPRs) 538 * 539 * The lower case r0-r31 should be used in preference to the upper 540 * case R0-R31 as they provide more error checking in the assembler. 541 * Use R0-31 only when really nessesary. 542 */ 543 544 #define r0 %r0 545 #define r1 %r1 546 #define r2 %r2 547 #define r3 %r3 548 #define r4 %r4 549 #define r5 %r5 550 #define r6 %r6 551 #define r7 %r7 552 #define r8 %r8 553 #define r9 %r9 554 #define r10 %r10 555 #define r11 %r11 556 #define r12 %r12 557 #define r13 %r13 558 #define r14 %r14 559 #define r15 %r15 560 #define r16 %r16 561 #define r17 %r17 562 #define r18 %r18 563 #define r19 %r19 564 #define r20 %r20 565 #define r21 %r21 566 #define r22 %r22 567 #define r23 %r23 568 #define r24 %r24 569 #define r25 %r25 570 #define r26 %r26 571 #define r27 %r27 572 #define r28 %r28 573 #define r29 %r29 574 #define r30 %r30 575 #define r31 %r31 576 577 578 /* Floating Point Registers (FPRs) */ 579 580 #define fr0 0 581 #define fr1 1 582 #define fr2 2 583 #define fr3 3 584 #define fr4 4 585 #define fr5 5 586 #define fr6 6 587 #define fr7 7 588 #define fr8 8 589 #define fr9 9 590 #define fr10 10 591 #define fr11 11 592 #define fr12 12 593 #define fr13 13 594 #define fr14 14 595 #define fr15 15 596 #define fr16 16 597 #define fr17 17 598 #define fr18 18 599 #define fr19 19 600 #define fr20 20 601 #define fr21 21 602 #define fr22 22 603 #define fr23 23 604 #define fr24 24 605 #define fr25 25 606 #define fr26 26 607 #define fr27 27 608 #define fr28 28 609 #define fr29 29 610 #define fr30 30 611 #define fr31 31 612 613 /* AltiVec Registers (VPRs) */ 614 615 #define vr0 0 616 #define vr1 1 617 #define vr2 2 618 #define vr3 3 619 #define vr4 4 620 #define vr5 5 621 #define vr6 6 622 #define vr7 7 623 #define vr8 8 624 #define vr9 9 625 #define vr10 10 626 #define vr11 11 627 #define vr12 12 628 #define vr13 13 629 #define vr14 14 630 #define vr15 15 631 #define vr16 16 632 #define vr17 17 633 #define vr18 18 634 #define vr19 19 635 #define vr20 20 636 #define vr21 21 637 #define vr22 22 638 #define vr23 23 639 #define vr24 24 640 #define vr25 25 641 #define vr26 26 642 #define vr27 27 643 #define vr28 28 644 #define vr29 29 645 #define vr30 30 646 #define vr31 31 647 648 /* VSX Registers (VSRs) */ 649 650 #define vsr0 0 651 #define vsr1 1 652 #define vsr2 2 653 #define vsr3 3 654 #define vsr4 4 655 #define vsr5 5 656 #define vsr6 6 657 #define vsr7 7 658 #define vsr8 8 659 #define vsr9 9 660 #define vsr10 10 661 #define vsr11 11 662 #define vsr12 12 663 #define vsr13 13 664 #define vsr14 14 665 #define vsr15 15 666 #define vsr16 16 667 #define vsr17 17 668 #define vsr18 18 669 #define vsr19 19 670 #define vsr20 20 671 #define vsr21 21 672 #define vsr22 22 673 #define vsr23 23 674 #define vsr24 24 675 #define vsr25 25 676 #define vsr26 26 677 #define vsr27 27 678 #define vsr28 28 679 #define vsr29 29 680 #define vsr30 30 681 #define vsr31 31 682 #define vsr32 32 683 #define vsr33 33 684 #define vsr34 34 685 #define vsr35 35 686 #define vsr36 36 687 #define vsr37 37 688 #define vsr38 38 689 #define vsr39 39 690 #define vsr40 40 691 #define vsr41 41 692 #define vsr42 42 693 #define vsr43 43 694 #define vsr44 44 695 #define vsr45 45 696 #define vsr46 46 697 #define vsr47 47 698 #define vsr48 48 699 #define vsr49 49 700 #define vsr50 50 701 #define vsr51 51 702 #define vsr52 52 703 #define vsr53 53 704 #define vsr54 54 705 #define vsr55 55 706 #define vsr56 56 707 #define vsr57 57 708 #define vsr58 58 709 #define vsr59 59 710 #define vsr60 60 711 #define vsr61 61 712 #define vsr62 62 713 #define vsr63 63 714 715 /* SPE Registers (EVPRs) */ 716 717 #define evr0 0 718 #define evr1 1 719 #define evr2 2 720 #define evr3 3 721 #define evr4 4 722 #define evr5 5 723 #define evr6 6 724 #define evr7 7 725 #define evr8 8 726 #define evr9 9 727 #define evr10 10 728 #define evr11 11 729 #define evr12 12 730 #define evr13 13 731 #define evr14 14 732 #define evr15 15 733 #define evr16 16 734 #define evr17 17 735 #define evr18 18 736 #define evr19 19 737 #define evr20 20 738 #define evr21 21 739 #define evr22 22 740 #define evr23 23 741 #define evr24 24 742 #define evr25 25 743 #define evr26 26 744 #define evr27 27 745 #define evr28 28 746 #define evr29 29 747 #define evr30 30 748 #define evr31 31 749 750 /* some stab codes */ 751 #define N_FUN 36 752 #define N_RSYM 64 753 #define N_SLINE 68 754 #define N_SO 100 755 756 /* 757 * Create an endian fixup trampoline 758 * 759 * This starts with a "tdi 0,0,0x48" instruction which is 760 * essentially a "trap never", and thus akin to a nop. 761 * 762 * The opcode for this instruction read with the wrong endian 763 * however results in a b . + 8 764 * 765 * So essentially we use that trick to execute the following 766 * trampoline in "reverse endian" if we are running with the 767 * MSR_LE bit set the "wrong" way for whatever endianness the 768 * kernel is built for. 769 */ 770 771 #ifdef CONFIG_PPC_BOOK3E 772 #define FIXUP_ENDIAN 773 #else 774 #define FIXUP_ENDIAN \ 775 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 776 b $+36; /* Skip trampoline if endian is good */ \ 777 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 778 .long 0xa602487d; /* mflr r10 */ \ 779 .long 0x1c004a39; /* addi r10,r10,28 */ \ 780 .long 0xa600607d; /* mfmsr r11 */ \ 781 .long 0x01006b69; /* xori r11,r11,1 */ \ 782 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 783 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 784 .long 0x2400004c /* rfid */ 785 #endif /* !CONFIG_PPC_BOOK3E */ 786 #endif /* __ASSEMBLY__ */ 787 #endif /* _ASM_POWERPC_PPC_ASM_H */ 788