1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Performance event support - PowerPC classic/server specific definitions. 4 * 5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 6 */ 7 8 #include <linux/types.h> 9 #include <asm/hw_irq.h> 10 #include <linux/device.h> 11 #include <uapi/asm/perf_event.h> 12 13 /* Update perf_event_print_debug() if this changes */ 14 #define MAX_HWEVENTS 8 15 #define MAX_EVENT_ALTERNATIVES 8 16 #define MAX_LIMITED_HWCOUNTERS 2 17 18 struct perf_event; 19 20 struct mmcr_regs { 21 unsigned long mmcr0; 22 unsigned long mmcr1; 23 unsigned long mmcr2; 24 unsigned long mmcra; 25 unsigned long mmcr3; 26 }; 27 /* 28 * This struct provides the constants and functions needed to 29 * describe the PMU on a particular POWER-family CPU. 30 */ 31 struct power_pmu { 32 const char *name; 33 int n_counter; 34 int max_alternatives; 35 unsigned long add_fields; 36 unsigned long test_adder; 37 int (*compute_mmcr)(u64 events[], int n_ev, 38 unsigned int hwc[], struct mmcr_regs *mmcr, 39 struct perf_event *pevents[], u32 flags); 40 int (*get_constraint)(u64 event_id, unsigned long *mskp, 41 unsigned long *valp, u64 event_config1); 42 int (*get_alternatives)(u64 event_id, unsigned int flags, 43 u64 alt[]); 44 void (*get_mem_data_src)(union perf_mem_data_src *dsrc, 45 u32 flags, struct pt_regs *regs); 46 void (*get_mem_weight)(u64 *weight); 47 unsigned long group_constraint_mask; 48 unsigned long group_constraint_val; 49 u64 (*bhrb_filter_map)(u64 branch_sample_type); 50 void (*config_bhrb)(u64 pmu_bhrb_filter); 51 void (*disable_pmc)(unsigned int pmc, struct mmcr_regs *mmcr); 52 int (*limited_pmc_event)(u64 event_id); 53 u32 flags; 54 const struct attribute_group **attr_groups; 55 int n_generic; 56 int *generic_events; 57 u64 (*cache_events)[PERF_COUNT_HW_CACHE_MAX] 58 [PERF_COUNT_HW_CACHE_OP_MAX] 59 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 60 61 int n_blacklist_ev; 62 int *blacklist_ev; 63 /* BHRB entries in the PMU */ 64 int bhrb_nr; 65 /* 66 * set this flag with `PERF_PMU_CAP_EXTENDED_REGS` if 67 * the pmu supports extended perf regs capability 68 */ 69 int capabilities; 70 }; 71 72 /* 73 * Values for power_pmu.flags 74 */ 75 #define PPMU_LIMITED_PMC5_6 0x00000001 /* PMC5/6 have limited function */ 76 #define PPMU_ALT_SIPR 0x00000002 /* uses alternate posn for SIPR/HV */ 77 #define PPMU_NO_SIPR 0x00000004 /* no SIPR/HV in MMCRA at all */ 78 #define PPMU_NO_CONT_SAMPLING 0x00000008 /* no continuous sampling */ 79 #define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */ 80 #define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */ 81 #define PPMU_HAS_SIER 0x00000040 /* Has SIER */ 82 #define PPMU_ARCH_207S 0x00000080 /* PMC is architecture v2.07S */ 83 #define PPMU_NO_SIAR 0x00000100 /* Do not use SIAR */ 84 #define PPMU_ARCH_31 0x00000200 /* Has MMCR3, SIER2 and SIER3 */ 85 #define PPMU_P10_DD1 0x00000400 /* Is power10 DD1 processor version */ 86 #define PPMU_HAS_ATTR_CONFIG1 0x00000800 /* Using config1 attribute */ 87 88 /* 89 * Values for flags to get_alternatives() 90 */ 91 #define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */ 92 #define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */ 93 #define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */ 94 95 extern int register_power_pmu(struct power_pmu *); 96 97 struct pt_regs; 98 extern unsigned long perf_misc_flags(struct pt_regs *regs); 99 extern unsigned long perf_instruction_pointer(struct pt_regs *regs); 100 extern unsigned long int read_bhrb(int n); 101 102 /* 103 * Only override the default definitions in include/linux/perf_event.h 104 * if we have hardware PMU support. 105 */ 106 #ifdef CONFIG_PPC_PERF_CTRS 107 #define perf_misc_flags(regs) perf_misc_flags(regs) 108 #endif 109 110 /* 111 * The power_pmu.get_constraint function returns a 32/64-bit value and 112 * a 32/64-bit mask that express the constraints between this event_id and 113 * other events. 114 * 115 * The value and mask are divided up into (non-overlapping) bitfields 116 * of three different types: 117 * 118 * Select field: this expresses the constraint that some set of bits 119 * in MMCR* needs to be set to a specific value for this event_id. For a 120 * select field, the mask contains 1s in every bit of the field, and 121 * the value contains a unique value for each possible setting of the 122 * MMCR* bits. The constraint checking code will ensure that two events 123 * that set the same field in their masks have the same value in their 124 * value dwords. 125 * 126 * Add field: this expresses the constraint that there can be at most 127 * N events in a particular class. A field of k bits can be used for 128 * N <= 2^(k-1) - 1. The mask has the most significant bit of the field 129 * set (and the other bits 0), and the value has only the least significant 130 * bit of the field set. In addition, the 'add_fields' and 'test_adder' 131 * in the struct power_pmu for this processor come into play. The 132 * add_fields value contains 1 in the LSB of the field, and the 133 * test_adder contains 2^(k-1) - 1 - N in the field. 134 * 135 * NAND field: this expresses the constraint that you may not have events 136 * in all of a set of classes. (For example, on PPC970, you can't select 137 * events from the FPU, ISU and IDU simultaneously, although any two are 138 * possible.) For N classes, the field is N+1 bits wide, and each class 139 * is assigned one bit from the least-significant N bits. The mask has 140 * only the most-significant bit set, and the value has only the bit 141 * for the event_id's class set. The test_adder has the least significant 142 * bit set in the field. 143 * 144 * If an event_id is not subject to the constraint expressed by a particular 145 * field, then it will have 0 in both the mask and value for that field. 146 */ 147 148 extern ssize_t power_events_sysfs_show(struct device *dev, 149 struct device_attribute *attr, char *page); 150 151 /* 152 * EVENT_VAR() is same as PMU_EVENT_VAR with a suffix. 153 * 154 * Having a suffix allows us to have aliases in sysfs - eg: the generic 155 * event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and 156 * 'PM_CYC' where the latter is the name by which the event is known in 157 * POWER CPU specification. 158 * 159 * Similarly, some hardware and cache events use the same event code. Eg. 160 * on POWER8, both "cache-references" and "L1-dcache-loads" events refer 161 * to the same event, PM_LD_REF_L1. The suffix, allows us to have two 162 * sysfs objects for the same event and thus two entries/aliases in sysfs. 163 */ 164 #define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix 165 #define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr 166 167 #define EVENT_ATTR(_name, _id, _suffix) \ 168 PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), _id, \ 169 power_events_sysfs_show) 170 171 #define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g) 172 #define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g) 173 174 #define CACHE_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _c) 175 #define CACHE_EVENT_PTR(_id) EVENT_PTR(_id, _c) 176 177 #define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p) 178 #define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p) 179