1 #ifndef __ASM_POWERPC_PCI_H 2 #define __ASM_POWERPC_PCI_H 3 #ifdef __KERNEL__ 4 5 /* 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/types.h> 13 #include <linux/slab.h> 14 #include <linux/string.h> 15 #include <linux/dma-mapping.h> 16 17 #include <asm/machdep.h> 18 #include <asm/scatterlist.h> 19 #include <asm/io.h> 20 #include <asm/prom.h> 21 #include <asm/pci-bridge.h> 22 23 #include <asm-generic/pci-dma-compat.h> 24 25 #define PCIBIOS_MIN_IO 0x1000 26 #define PCIBIOS_MIN_MEM 0x10000000 27 28 struct pci_dev; 29 30 /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ 31 #define IOBASE_BRIDGE_NUMBER 0 32 #define IOBASE_MEMORY 1 33 #define IOBASE_IO 2 34 #define IOBASE_ISA_IO 3 35 #define IOBASE_ISA_MEM 4 36 37 /* 38 * Set this to 1 if you want the kernel to re-assign all PCI 39 * bus numbers (don't do that on ppc64 yet !) 40 */ 41 #define pcibios_assign_all_busses() (ppc_pci_flags & \ 42 PPC_PCI_REASSIGN_ALL_BUS) 43 #define pcibios_scan_all_fns(a, b) 0 44 45 static inline void pcibios_set_master(struct pci_dev *dev) 46 { 47 /* No special bus mastering setup handling */ 48 } 49 50 static inline void pcibios_penalize_isa_irq(int irq, int active) 51 { 52 /* We don't do dynamic PCI IRQ allocation */ 53 } 54 55 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ 56 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 57 { 58 if (ppc_md.pci_get_legacy_ide_irq) 59 return ppc_md.pci_get_legacy_ide_irq(dev, channel); 60 return channel ? 15 : 14; 61 } 62 63 #ifdef CONFIG_PCI 64 extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops); 65 extern struct dma_mapping_ops *get_pci_dma_ops(void); 66 #else /* CONFIG_PCI */ 67 #define set_pci_dma_ops(d) 68 #define get_pci_dma_ops() NULL 69 #endif 70 71 #ifdef CONFIG_PPC64 72 73 /* 74 * We want to avoid touching the cacheline size or MWI bit. 75 * pSeries firmware sets the cacheline size (which is not the cpu cacheline 76 * size in all cases) and hardware treats MWI the same as memory write. 77 */ 78 #define PCI_DISABLE_MWI 79 80 #ifdef CONFIG_PCI 81 static inline void pci_dma_burst_advice(struct pci_dev *pdev, 82 enum pci_dma_burst_strategy *strat, 83 unsigned long *strategy_parameter) 84 { 85 unsigned long cacheline_size; 86 u8 byte; 87 88 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 89 if (byte == 0) 90 cacheline_size = 1024; 91 else 92 cacheline_size = (int) byte * 4; 93 94 *strat = PCI_DMA_BURST_MULTIPLE; 95 *strategy_parameter = cacheline_size; 96 } 97 #endif 98 99 #else /* 32-bit */ 100 101 #ifdef CONFIG_PCI 102 static inline void pci_dma_burst_advice(struct pci_dev *pdev, 103 enum pci_dma_burst_strategy *strat, 104 unsigned long *strategy_parameter) 105 { 106 *strat = PCI_DMA_BURST_INFINITY; 107 *strategy_parameter = ~0UL; 108 } 109 #endif 110 #endif /* CONFIG_PPC64 */ 111 112 extern int pci_domain_nr(struct pci_bus *bus); 113 114 /* Decide whether to display the domain number in /proc */ 115 extern int pci_proc_domain(struct pci_bus *bus); 116 117 118 struct vm_area_struct; 119 /* Map a range of PCI memory or I/O space for a device into user space */ 120 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, 121 enum pci_mmap_state mmap_state, int write_combine); 122 123 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ 124 #define HAVE_PCI_MMAP 1 125 126 extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, 127 size_t count); 128 extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, 129 size_t count); 130 extern int pci_mmap_legacy_page_range(struct pci_bus *bus, 131 struct vm_area_struct *vma, 132 enum pci_mmap_state mmap_state); 133 134 #define HAVE_PCI_LEGACY 1 135 136 #if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE) 137 /* 138 * For 64-bit kernels, pci_unmap_{single,page} is not a nop. 139 * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and 140 * so on are not nops. 141 * and thus... 142 */ 143 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 144 dma_addr_t ADDR_NAME; 145 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 146 __u32 LEN_NAME; 147 #define pci_unmap_addr(PTR, ADDR_NAME) \ 148 ((PTR)->ADDR_NAME) 149 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 150 (((PTR)->ADDR_NAME) = (VAL)) 151 #define pci_unmap_len(PTR, LEN_NAME) \ 152 ((PTR)->LEN_NAME) 153 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 154 (((PTR)->LEN_NAME) = (VAL)) 155 156 #else /* 32-bit && coherent */ 157 158 /* pci_unmap_{page,single} is a nop so... */ 159 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) 160 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) 161 #define pci_unmap_addr(PTR, ADDR_NAME) (0) 162 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) 163 #define pci_unmap_len(PTR, LEN_NAME) (0) 164 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) 165 166 #endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */ 167 168 #ifdef CONFIG_PPC64 169 170 /* The PCI address space does not equal the physical memory address 171 * space (we have an IOMMU). The IDE and SCSI device layers use 172 * this boolean for bounce buffer decisions. 173 */ 174 #define PCI_DMA_BUS_IS_PHYS (0) 175 176 #else /* 32-bit */ 177 178 /* The PCI address space does equal the physical memory 179 * address space (no IOMMU). The IDE and SCSI device layers use 180 * this boolean for bounce buffer decisions. 181 */ 182 #define PCI_DMA_BUS_IS_PHYS (1) 183 184 #endif /* CONFIG_PPC64 */ 185 186 extern void pcibios_resource_to_bus(struct pci_dev *dev, 187 struct pci_bus_region *region, 188 struct resource *res); 189 190 extern void pcibios_bus_to_resource(struct pci_dev *dev, 191 struct resource *res, 192 struct pci_bus_region *region); 193 194 static inline struct resource *pcibios_select_root(struct pci_dev *pdev, 195 struct resource *res) 196 { 197 struct resource *root = NULL; 198 199 if (res->flags & IORESOURCE_IO) 200 root = &ioport_resource; 201 if (res->flags & IORESOURCE_MEM) 202 root = &iomem_resource; 203 204 return root; 205 } 206 207 extern void pcibios_setup_new_device(struct pci_dev *dev); 208 209 extern void pcibios_claim_one_bus(struct pci_bus *b); 210 211 extern void pcibios_allocate_bus_resources(struct pci_bus *bus); 212 213 extern void pcibios_resource_survey(void); 214 215 extern struct pci_controller *init_phb_dynamic(struct device_node *dn); 216 217 extern struct pci_dev *of_create_pci_dev(struct device_node *node, 218 struct pci_bus *bus, int devfn); 219 220 extern void of_scan_pci_bridge(struct device_node *node, 221 struct pci_dev *dev); 222 223 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); 224 225 extern int pci_read_irq_line(struct pci_dev *dev); 226 227 struct file; 228 extern pgprot_t pci_phys_mem_access_prot(struct file *file, 229 unsigned long pfn, 230 unsigned long size, 231 pgprot_t prot); 232 233 #define HAVE_ARCH_PCI_RESOURCE_TO_USER 234 extern void pci_resource_to_user(const struct pci_dev *dev, int bar, 235 const struct resource *rsrc, 236 resource_size_t *start, resource_size_t *end); 237 238 extern void pcibios_do_bus_setup(struct pci_bus *bus); 239 extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus); 240 241 242 #endif /* __KERNEL__ */ 243 #endif /* __ASM_POWERPC_PCI_H */ 244