1 /* 2 * PowerNV OPAL definitions. 3 * 4 * Copyright 2011 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef __OPAL_H 13 #define __OPAL_H 14 15 /****** Takeover interface ********/ 16 17 /* PAPR H-Call used to querty the HAL existence and/or instanciate 18 * it from within pHyp (tech preview only). 19 * 20 * This is exclusively used in prom_init.c 21 */ 22 23 #ifndef __ASSEMBLY__ 24 25 struct opal_takeover_args { 26 u64 k_image; /* r4 */ 27 u64 k_size; /* r5 */ 28 u64 k_entry; /* r6 */ 29 u64 k_entry2; /* r7 */ 30 u64 hal_addr; /* r8 */ 31 u64 rd_image; /* r9 */ 32 u64 rd_size; /* r10 */ 33 u64 rd_loc; /* r11 */ 34 }; 35 36 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align); 37 38 extern long opal_do_takeover(struct opal_takeover_args *args); 39 40 struct rtas_args; 41 extern int opal_enter_rtas(struct rtas_args *args, 42 unsigned long data, 43 unsigned long entry); 44 45 #endif /* __ASSEMBLY__ */ 46 47 /****** OPAL APIs ******/ 48 49 /* Return codes */ 50 #define OPAL_SUCCESS 0 51 #define OPAL_PARAMETER -1 52 #define OPAL_BUSY -2 53 #define OPAL_PARTIAL -3 54 #define OPAL_CONSTRAINED -4 55 #define OPAL_CLOSED -5 56 #define OPAL_HARDWARE -6 57 #define OPAL_UNSUPPORTED -7 58 #define OPAL_PERMISSION -8 59 #define OPAL_NO_MEM -9 60 #define OPAL_RESOURCE -10 61 #define OPAL_INTERNAL_ERROR -11 62 #define OPAL_BUSY_EVENT -12 63 #define OPAL_HARDWARE_FROZEN -13 64 65 /* API Tokens (in r0) */ 66 #define OPAL_CONSOLE_WRITE 1 67 #define OPAL_CONSOLE_READ 2 68 #define OPAL_RTC_READ 3 69 #define OPAL_RTC_WRITE 4 70 #define OPAL_CEC_POWER_DOWN 5 71 #define OPAL_CEC_REBOOT 6 72 #define OPAL_READ_NVRAM 7 73 #define OPAL_WRITE_NVRAM 8 74 #define OPAL_HANDLE_INTERRUPT 9 75 #define OPAL_POLL_EVENTS 10 76 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 77 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 78 #define OPAL_PCI_CONFIG_READ_BYTE 13 79 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 80 #define OPAL_PCI_CONFIG_READ_WORD 15 81 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 82 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 83 #define OPAL_PCI_CONFIG_WRITE_WORD 18 84 #define OPAL_SET_XIVE 19 85 #define OPAL_GET_XIVE 20 86 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 87 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 88 #define OPAL_PCI_EEH_FREEZE_STATUS 23 89 #define OPAL_PCI_SHPC 24 90 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 91 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 92 #define OPAL_PCI_PHB_MMIO_ENABLE 27 93 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 94 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 95 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 96 #define OPAL_PCI_SET_PE 31 97 #define OPAL_PCI_SET_PELTV 32 98 #define OPAL_PCI_SET_MVE 33 99 #define OPAL_PCI_SET_MVE_ENABLE 34 100 #define OPAL_PCI_GET_XIVE_REISSUE 35 101 #define OPAL_PCI_SET_XIVE_REISSUE 36 102 #define OPAL_PCI_SET_XIVE_PE 37 103 #define OPAL_GET_XIVE_SOURCE 38 104 #define OPAL_GET_MSI_32 39 105 #define OPAL_GET_MSI_64 40 106 #define OPAL_START_CPU 41 107 #define OPAL_QUERY_CPU_STATUS 42 108 #define OPAL_WRITE_OPPANEL 43 109 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 110 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 111 #define OPAL_PCI_RESET 49 112 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 113 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 114 #define OPAL_PCI_FENCE_PHB 52 115 #define OPAL_PCI_REINIT 53 116 #define OPAL_PCI_MASK_PE_ERROR 54 117 #define OPAL_SET_SLOT_LED_STATUS 55 118 #define OPAL_GET_EPOW_STATUS 56 119 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 120 #define OPAL_RESERVED1 58 121 #define OPAL_RESERVED2 59 122 #define OPAL_PCI_NEXT_ERROR 60 123 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 124 #define OPAL_PCI_POLL 62 125 #define OPAL_PCI_MSI_EOI 63 126 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 127 128 #ifndef __ASSEMBLY__ 129 130 /* Other enums */ 131 enum OpalVendorApiTokens { 132 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999 133 }; 134 135 enum OpalFreezeState { 136 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 137 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 138 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 139 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 140 OPAL_EEH_STOPPED_RESET = 4, 141 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 142 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 143 }; 144 145 enum OpalEehFreezeActionToken { 146 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 147 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 148 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3 149 }; 150 151 enum OpalPciStatusToken { 152 OPAL_EEH_NO_ERROR = 0, 153 OPAL_EEH_IOC_ERROR = 1, 154 OPAL_EEH_PHB_ERROR = 2, 155 OPAL_EEH_PE_ERROR = 3, 156 OPAL_EEH_PE_MMIO_ERROR = 4, 157 OPAL_EEH_PE_DMA_ERROR = 5 158 }; 159 160 enum OpalPciErrorSeverity { 161 OPAL_EEH_SEV_NO_ERROR = 0, 162 OPAL_EEH_SEV_IOC_DEAD = 1, 163 OPAL_EEH_SEV_PHB_DEAD = 2, 164 OPAL_EEH_SEV_PHB_FENCED = 3, 165 OPAL_EEH_SEV_PE_ER = 4, 166 OPAL_EEH_SEV_INF = 5 167 }; 168 169 enum OpalShpcAction { 170 OPAL_SHPC_GET_LINK_STATE = 0, 171 OPAL_SHPC_GET_SLOT_STATE = 1 172 }; 173 174 enum OpalShpcLinkState { 175 OPAL_SHPC_LINK_DOWN = 0, 176 OPAL_SHPC_LINK_UP = 1 177 }; 178 179 enum OpalMmioWindowType { 180 OPAL_M32_WINDOW_TYPE = 1, 181 OPAL_M64_WINDOW_TYPE = 2, 182 OPAL_IO_WINDOW_TYPE = 3 183 }; 184 185 enum OpalShpcSlotState { 186 OPAL_SHPC_DEV_NOT_PRESENT = 0, 187 OPAL_SHPC_DEV_PRESENT = 1 188 }; 189 190 enum OpalExceptionHandler { 191 OPAL_MACHINE_CHECK_HANDLER = 1, 192 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 193 OPAL_SOFTPATCH_HANDLER = 3 194 }; 195 196 enum OpalPendingState { 197 OPAL_EVENT_OPAL_INTERNAL = 0x1, 198 OPAL_EVENT_NVRAM = 0x2, 199 OPAL_EVENT_RTC = 0x4, 200 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 201 OPAL_EVENT_CONSOLE_INPUT = 0x10, 202 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 203 OPAL_EVENT_ERROR_LOG = 0x40, 204 OPAL_EVENT_EPOW = 0x80, 205 OPAL_EVENT_LED_STATUS = 0x100, 206 OPAL_EVENT_PCI_ERROR = 0x200 207 }; 208 209 /* Machine check related definitions */ 210 enum OpalMCE_Version { 211 OpalMCE_V1 = 1, 212 }; 213 214 enum OpalMCE_Severity { 215 OpalMCE_SEV_NO_ERROR = 0, 216 OpalMCE_SEV_WARNING = 1, 217 OpalMCE_SEV_ERROR_SYNC = 2, 218 OpalMCE_SEV_FATAL = 3, 219 }; 220 221 enum OpalMCE_Disposition { 222 OpalMCE_DISPOSITION_RECOVERED = 0, 223 OpalMCE_DISPOSITION_NOT_RECOVERED = 1, 224 }; 225 226 enum OpalMCE_Initiator { 227 OpalMCE_INITIATOR_UNKNOWN = 0, 228 OpalMCE_INITIATOR_CPU = 1, 229 }; 230 231 enum OpalMCE_ErrorType { 232 OpalMCE_ERROR_TYPE_UNKNOWN = 0, 233 OpalMCE_ERROR_TYPE_UE = 1, 234 OpalMCE_ERROR_TYPE_SLB = 2, 235 OpalMCE_ERROR_TYPE_ERAT = 3, 236 OpalMCE_ERROR_TYPE_TLB = 4, 237 }; 238 239 enum OpalMCE_UeErrorType { 240 OpalMCE_UE_ERROR_INDETERMINATE = 0, 241 OpalMCE_UE_ERROR_IFETCH = 1, 242 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2, 243 OpalMCE_UE_ERROR_LOAD_STORE = 3, 244 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4, 245 }; 246 247 enum OpalMCE_SlbErrorType { 248 OpalMCE_SLB_ERROR_INDETERMINATE = 0, 249 OpalMCE_SLB_ERROR_PARITY = 1, 250 OpalMCE_SLB_ERROR_MULTIHIT = 2, 251 }; 252 253 enum OpalMCE_EratErrorType { 254 OpalMCE_ERAT_ERROR_INDETERMINATE = 0, 255 OpalMCE_ERAT_ERROR_PARITY = 1, 256 OpalMCE_ERAT_ERROR_MULTIHIT = 2, 257 }; 258 259 enum OpalMCE_TlbErrorType { 260 OpalMCE_TLB_ERROR_INDETERMINATE = 0, 261 OpalMCE_TLB_ERROR_PARITY = 1, 262 OpalMCE_TLB_ERROR_MULTIHIT = 2, 263 }; 264 265 enum OpalThreadStatus { 266 OPAL_THREAD_INACTIVE = 0x0, 267 OPAL_THREAD_STARTED = 0x1, 268 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 269 }; 270 271 enum OpalPciBusCompare { 272 OpalPciBusAny = 0, /* Any bus number match */ 273 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 274 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 275 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 276 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 277 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 278 OpalPciBusAll = 7, /* Match bus number exactly */ 279 }; 280 281 enum OpalDeviceCompare { 282 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 283 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 284 }; 285 286 enum OpalFuncCompare { 287 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 288 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 289 }; 290 291 enum OpalPeAction { 292 OPAL_UNMAP_PE = 0, 293 OPAL_MAP_PE = 1 294 }; 295 296 enum OpalPeltvAction { 297 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 298 OPAL_ADD_PE_TO_DOMAIN = 1 299 }; 300 301 enum OpalMveEnableAction { 302 OPAL_DISABLE_MVE = 0, 303 OPAL_ENABLE_MVE = 1 304 }; 305 306 enum OpalPciResetAndReinitScope { 307 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, 308 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, 309 OPAL_PCI_IODA_TABLE_RESET = 6, 310 }; 311 312 enum OpalPciResetState { 313 OPAL_DEASSERT_RESET = 0, 314 OPAL_ASSERT_RESET = 1 315 }; 316 317 enum OpalPciMaskAction { 318 OPAL_UNMASK_ERROR_TYPE = 0, 319 OPAL_MASK_ERROR_TYPE = 1 320 }; 321 322 enum OpalSlotLedType { 323 OPAL_SLOT_LED_ID_TYPE = 0, 324 OPAL_SLOT_LED_FAULT_TYPE = 1 325 }; 326 327 enum OpalLedAction { 328 OPAL_TURN_OFF_LED = 0, 329 OPAL_TURN_ON_LED = 1, 330 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2 331 }; 332 333 enum OpalEpowStatus { 334 OPAL_EPOW_NONE = 0, 335 OPAL_EPOW_UPS = 1, 336 OPAL_EPOW_OVER_AMBIENT_TEMP = 2, 337 OPAL_EPOW_OVER_INTERNAL_TEMP = 3 338 }; 339 340 struct opal_machine_check_event { 341 enum OpalMCE_Version version:8; /* 0x00 */ 342 uint8_t in_use; /* 0x01 */ 343 enum OpalMCE_Severity severity:8; /* 0x02 */ 344 enum OpalMCE_Initiator initiator:8; /* 0x03 */ 345 enum OpalMCE_ErrorType error_type:8; /* 0x04 */ 346 enum OpalMCE_Disposition disposition:8; /* 0x05 */ 347 uint8_t reserved_1[2]; /* 0x06 */ 348 uint64_t gpr3; /* 0x08 */ 349 uint64_t srr0; /* 0x10 */ 350 uint64_t srr1; /* 0x18 */ 351 union { /* 0x20 */ 352 struct { 353 enum OpalMCE_UeErrorType ue_error_type:8; 354 uint8_t effective_address_provided; 355 uint8_t physical_address_provided; 356 uint8_t reserved_1[5]; 357 uint64_t effective_address; 358 uint64_t physical_address; 359 uint8_t reserved_2[8]; 360 } ue_error; 361 362 struct { 363 enum OpalMCE_SlbErrorType slb_error_type:8; 364 uint8_t effective_address_provided; 365 uint8_t reserved_1[6]; 366 uint64_t effective_address; 367 uint8_t reserved_2[16]; 368 } slb_error; 369 370 struct { 371 enum OpalMCE_EratErrorType erat_error_type:8; 372 uint8_t effective_address_provided; 373 uint8_t reserved_1[6]; 374 uint64_t effective_address; 375 uint8_t reserved_2[16]; 376 } erat_error; 377 378 struct { 379 enum OpalMCE_TlbErrorType tlb_error_type:8; 380 uint8_t effective_address_provided; 381 uint8_t reserved_1[6]; 382 uint64_t effective_address; 383 uint8_t reserved_2[16]; 384 } tlb_error; 385 } u; 386 }; 387 388 enum { 389 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 390 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 391 OPAL_P7IOC_DIAG_TYPE_BI = 2, 392 OPAL_P7IOC_DIAG_TYPE_CI = 3, 393 OPAL_P7IOC_DIAG_TYPE_MISC = 4, 394 OPAL_P7IOC_DIAG_TYPE_I2C = 5, 395 OPAL_P7IOC_DIAG_TYPE_LAST = 6 396 }; 397 398 struct OpalIoP7IOCErrorData { 399 uint16_t type; 400 401 /* GEM */ 402 uint64_t gemXfir; 403 uint64_t gemRfir; 404 uint64_t gemRirqfir; 405 uint64_t gemMask; 406 uint64_t gemRwof; 407 408 /* LEM */ 409 uint64_t lemFir; 410 uint64_t lemErrMask; 411 uint64_t lemAction0; 412 uint64_t lemAction1; 413 uint64_t lemWof; 414 415 union { 416 struct OpalIoP7IOCRgcErrorData { 417 uint64_t rgcStatus; /* 3E1C10 */ 418 uint64_t rgcLdcp; /* 3E1C18 */ 419 }rgc; 420 struct OpalIoP7IOCBiErrorData { 421 uint64_t biLdcp0; /* 3C0100, 3C0118 */ 422 uint64_t biLdcp1; /* 3C0108, 3C0120 */ 423 uint64_t biLdcp2; /* 3C0110, 3C0128 */ 424 uint64_t biFenceStatus; /* 3C0130, 3C0130 */ 425 426 uint8_t biDownbound; /* BI Downbound or Upbound */ 427 }bi; 428 struct OpalIoP7IOCCiErrorData { 429 uint64_t ciPortStatus; /* 3Dn008 */ 430 uint64_t ciPortLdcp; /* 3Dn010 */ 431 432 uint8_t ciPort; /* Index of CI port: 0/1 */ 433 }ci; 434 }; 435 }; 436 437 /** 438 * This structure defines the overlay which will be used to store PHB error 439 * data upon request. 440 */ 441 enum { 442 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 443 }; 444 445 enum { 446 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, 447 }; 448 449 enum { 450 OPAL_P7IOC_NUM_PEST_REGS = 128, 451 }; 452 453 struct OpalIoPhbErrorCommon { 454 uint32_t version; 455 uint32_t ioType; 456 uint32_t len; 457 }; 458 459 struct OpalIoP7IOCPhbErrorData { 460 struct OpalIoPhbErrorCommon common; 461 462 uint32_t brdgCtl; 463 464 // P7IOC utl regs 465 uint32_t portStatusReg; 466 uint32_t rootCmplxStatus; 467 uint32_t busAgentStatus; 468 469 // P7IOC cfg regs 470 uint32_t deviceStatus; 471 uint32_t slotStatus; 472 uint32_t linkStatus; 473 uint32_t devCmdStatus; 474 uint32_t devSecStatus; 475 476 // cfg AER regs 477 uint32_t rootErrorStatus; 478 uint32_t uncorrErrorStatus; 479 uint32_t corrErrorStatus; 480 uint32_t tlpHdr1; 481 uint32_t tlpHdr2; 482 uint32_t tlpHdr3; 483 uint32_t tlpHdr4; 484 uint32_t sourceId; 485 486 uint32_t rsv3; 487 488 // Record data about the call to allocate a buffer. 489 uint64_t errorClass; 490 uint64_t correlator; 491 492 //P7IOC MMIO Error Regs 493 uint64_t p7iocPlssr; // n120 494 uint64_t p7iocCsr; // n110 495 uint64_t lemFir; // nC00 496 uint64_t lemErrorMask; // nC18 497 uint64_t lemWOF; // nC40 498 uint64_t phbErrorStatus; // nC80 499 uint64_t phbFirstErrorStatus; // nC88 500 uint64_t phbErrorLog0; // nCC0 501 uint64_t phbErrorLog1; // nCC8 502 uint64_t mmioErrorStatus; // nD00 503 uint64_t mmioFirstErrorStatus; // nD08 504 uint64_t mmioErrorLog0; // nD40 505 uint64_t mmioErrorLog1; // nD48 506 uint64_t dma0ErrorStatus; // nD80 507 uint64_t dma0FirstErrorStatus; // nD88 508 uint64_t dma0ErrorLog0; // nDC0 509 uint64_t dma0ErrorLog1; // nDC8 510 uint64_t dma1ErrorStatus; // nE00 511 uint64_t dma1FirstErrorStatus; // nE08 512 uint64_t dma1ErrorLog0; // nE40 513 uint64_t dma1ErrorLog1; // nE48 514 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS]; 515 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS]; 516 }; 517 518 typedef struct oppanel_line { 519 const char * line; 520 uint64_t line_len; 521 } oppanel_line_t; 522 523 /* API functions */ 524 int64_t opal_console_write(int64_t term_number, int64_t *length, 525 const uint8_t *buffer); 526 int64_t opal_console_read(int64_t term_number, int64_t *length, 527 uint8_t *buffer); 528 int64_t opal_console_write_buffer_space(int64_t term_number, 529 int64_t *length); 530 int64_t opal_rtc_read(uint32_t *year_month_day, 531 uint64_t *hour_minute_second_millisecond); 532 int64_t opal_rtc_write(uint32_t year_month_day, 533 uint64_t hour_minute_second_millisecond); 534 int64_t opal_cec_power_down(uint64_t request); 535 int64_t opal_cec_reboot(void); 536 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 537 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 538 int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask); 539 int64_t opal_poll_events(uint64_t *outstanding_event_mask); 540 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr, 541 uint64_t tce_mem_size); 542 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr, 543 uint64_t tce_mem_size); 544 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func, 545 uint64_t offset, uint8_t *data); 546 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func, 547 uint64_t offset, uint16_t *data); 548 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func, 549 uint64_t offset, uint32_t *data); 550 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func, 551 uint64_t offset, uint8_t data); 552 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func, 553 uint64_t offset, uint16_t data); 554 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func, 555 uint64_t offset, uint32_t data); 556 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); 557 int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority); 558 int64_t opal_register_exception_handler(uint64_t opal_exception, 559 uint64_t handler_address, 560 uint64_t glue_cache_line); 561 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, 562 uint8_t *freeze_state, 563 uint16_t *pci_error_type, 564 uint64_t *phb_status); 565 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, 566 uint64_t eeh_action_token); 567 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state); 568 569 570 571 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, 572 uint16_t window_num, uint16_t enable); 573 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, 574 uint16_t window_num, 575 uint64_t starting_real_address, 576 uint64_t starting_pci_address, 577 uint16_t segment_size); 578 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, 579 uint16_t window_type, uint16_t window_num, 580 uint16_t segment_num); 581 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr, 582 uint64_t ivt_addr, uint64_t ivt_len, 583 uint64_t reject_array_addr, 584 uint64_t peltv_addr); 585 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func, 586 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare, 587 uint8_t pe_action); 588 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, 589 uint8_t state); 590 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); 591 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, 592 uint32_t state); 593 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, 594 uint8_t *p_bit, uint8_t *q_bit); 595 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, 596 uint8_t p_bit, uint8_t q_bit); 597 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); 598 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, 599 uint32_t xive_num); 600 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, 601 int32_t *interrupt_source_number); 602 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, 603 uint8_t msi_range, uint32_t *msi_address, 604 uint32_t *message_data); 605 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, 606 uint32_t xive_num, uint8_t msi_range, 607 uint64_t *msi_address, uint32_t *message_data); 608 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address); 609 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status); 610 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines); 611 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id, 612 uint16_t tce_levels, uint64_t tce_table_addr, 613 uint64_t tce_table_size, uint64_t tce_page_size); 614 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number, 615 uint16_t dma_window_number, uint64_t pci_start_addr, 616 uint64_t pci_mem_size); 617 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state); 618 619 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, 620 uint64_t diag_buffer_len); 621 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, 622 uint64_t diag_buffer_len); 623 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, 624 uint64_t diag_buffer_len); 625 int64_t opal_pci_fence_phb(uint64_t phb_id); 626 int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope); 627 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); 628 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); 629 int64_t opal_get_epow_status(uint64_t *status); 630 int64_t opal_set_system_attention_led(uint8_t led_action); 631 int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe, 632 uint16_t *pci_error_type, uint16_t *severity); 633 int64_t opal_pci_poll(uint64_t phb_id); 634 635 /* Internal functions */ 636 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data); 637 638 extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 639 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 640 641 extern void hvc_opal_init_early(void); 642 643 /* Internal functions */ 644 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, 645 int depth, void *data); 646 647 extern int opal_notifier_register(struct notifier_block *nb); 648 extern void opal_notifier_enable(void); 649 extern void opal_notifier_disable(void); 650 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 651 652 extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 653 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 654 655 extern void hvc_opal_init_early(void); 656 657 struct rtc_time; 658 extern int opal_set_rtc_time(struct rtc_time *tm); 659 extern void opal_get_rtc_time(struct rtc_time *tm); 660 extern unsigned long opal_get_boot_time(void); 661 extern void opal_nvram_init(void); 662 663 extern int opal_machine_check(struct pt_regs *regs); 664 665 extern void opal_shutdown(void); 666 667 #endif /* __ASSEMBLY__ */ 668 669 #endif /* __OPAL_H */ 670