1 /* 2 * PowerNV OPAL definitions. 3 * 4 * Copyright 2011 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef __OPAL_H 13 #define __OPAL_H 14 15 #ifndef __ASSEMBLY__ 16 /* 17 * SG entry 18 * 19 * WARNING: The current implementation requires each entry 20 * to represent a block that is 4k aligned *and* each block 21 * size except the last one in the list to be as well. 22 */ 23 struct opal_sg_entry { 24 __be64 data; 25 __be64 length; 26 }; 27 28 /* SG list */ 29 struct opal_sg_list { 30 __be64 length; 31 __be64 next; 32 struct opal_sg_entry entry[]; 33 }; 34 35 /* We calculate number of sg entries based on PAGE_SIZE */ 36 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry)) 37 38 #endif /* __ASSEMBLY__ */ 39 40 /****** OPAL APIs ******/ 41 42 /* Return codes */ 43 #define OPAL_SUCCESS 0 44 #define OPAL_PARAMETER -1 45 #define OPAL_BUSY -2 46 #define OPAL_PARTIAL -3 47 #define OPAL_CONSTRAINED -4 48 #define OPAL_CLOSED -5 49 #define OPAL_HARDWARE -6 50 #define OPAL_UNSUPPORTED -7 51 #define OPAL_PERMISSION -8 52 #define OPAL_NO_MEM -9 53 #define OPAL_RESOURCE -10 54 #define OPAL_INTERNAL_ERROR -11 55 #define OPAL_BUSY_EVENT -12 56 #define OPAL_HARDWARE_FROZEN -13 57 #define OPAL_WRONG_STATE -14 58 #define OPAL_ASYNC_COMPLETION -15 59 60 /* API Tokens (in r0) */ 61 #define OPAL_INVALID_CALL -1 62 #define OPAL_CONSOLE_WRITE 1 63 #define OPAL_CONSOLE_READ 2 64 #define OPAL_RTC_READ 3 65 #define OPAL_RTC_WRITE 4 66 #define OPAL_CEC_POWER_DOWN 5 67 #define OPAL_CEC_REBOOT 6 68 #define OPAL_READ_NVRAM 7 69 #define OPAL_WRITE_NVRAM 8 70 #define OPAL_HANDLE_INTERRUPT 9 71 #define OPAL_POLL_EVENTS 10 72 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 73 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 74 #define OPAL_PCI_CONFIG_READ_BYTE 13 75 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 76 #define OPAL_PCI_CONFIG_READ_WORD 15 77 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 78 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 79 #define OPAL_PCI_CONFIG_WRITE_WORD 18 80 #define OPAL_SET_XIVE 19 81 #define OPAL_GET_XIVE 20 82 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 83 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 84 #define OPAL_PCI_EEH_FREEZE_STATUS 23 85 #define OPAL_PCI_SHPC 24 86 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 87 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 88 #define OPAL_PCI_PHB_MMIO_ENABLE 27 89 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 90 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 91 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 92 #define OPAL_PCI_SET_PE 31 93 #define OPAL_PCI_SET_PELTV 32 94 #define OPAL_PCI_SET_MVE 33 95 #define OPAL_PCI_SET_MVE_ENABLE 34 96 #define OPAL_PCI_GET_XIVE_REISSUE 35 97 #define OPAL_PCI_SET_XIVE_REISSUE 36 98 #define OPAL_PCI_SET_XIVE_PE 37 99 #define OPAL_GET_XIVE_SOURCE 38 100 #define OPAL_GET_MSI_32 39 101 #define OPAL_GET_MSI_64 40 102 #define OPAL_START_CPU 41 103 #define OPAL_QUERY_CPU_STATUS 42 104 #define OPAL_WRITE_OPPANEL 43 105 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 106 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 107 #define OPAL_PCI_RESET 49 108 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 109 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 110 #define OPAL_PCI_FENCE_PHB 52 111 #define OPAL_PCI_REINIT 53 112 #define OPAL_PCI_MASK_PE_ERROR 54 113 #define OPAL_SET_SLOT_LED_STATUS 55 114 #define OPAL_GET_EPOW_STATUS 56 115 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 116 #define OPAL_RESERVED1 58 117 #define OPAL_RESERVED2 59 118 #define OPAL_PCI_NEXT_ERROR 60 119 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 120 #define OPAL_PCI_POLL 62 121 #define OPAL_PCI_MSI_EOI 63 122 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 123 #define OPAL_XSCOM_READ 65 124 #define OPAL_XSCOM_WRITE 66 125 #define OPAL_LPC_READ 67 126 #define OPAL_LPC_WRITE 68 127 #define OPAL_RETURN_CPU 69 128 #define OPAL_REINIT_CPUS 70 129 #define OPAL_ELOG_READ 71 130 #define OPAL_ELOG_WRITE 72 131 #define OPAL_ELOG_ACK 73 132 #define OPAL_ELOG_RESEND 74 133 #define OPAL_ELOG_SIZE 75 134 #define OPAL_FLASH_VALIDATE 76 135 #define OPAL_FLASH_MANAGE 77 136 #define OPAL_FLASH_UPDATE 78 137 #define OPAL_RESYNC_TIMEBASE 79 138 #define OPAL_CHECK_TOKEN 80 139 #define OPAL_DUMP_INIT 81 140 #define OPAL_DUMP_INFO 82 141 #define OPAL_DUMP_READ 83 142 #define OPAL_DUMP_ACK 84 143 #define OPAL_GET_MSG 85 144 #define OPAL_CHECK_ASYNC_COMPLETION 86 145 #define OPAL_SYNC_HOST_REBOOT 87 146 #define OPAL_SENSOR_READ 88 147 #define OPAL_GET_PARAM 89 148 #define OPAL_SET_PARAM 90 149 #define OPAL_DUMP_RESEND 91 150 #define OPAL_DUMP_INFO2 94 151 #define OPAL_PCI_EEH_FREEZE_SET 97 152 #define OPAL_HANDLE_HMI 98 153 #define OPAL_REGISTER_DUMP_REGION 101 154 #define OPAL_UNREGISTER_DUMP_REGION 102 155 156 #ifndef __ASSEMBLY__ 157 158 #include <linux/notifier.h> 159 160 /* Other enums */ 161 enum OpalVendorApiTokens { 162 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999 163 }; 164 165 enum OpalFreezeState { 166 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 167 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 168 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 169 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 170 OPAL_EEH_STOPPED_RESET = 4, 171 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 172 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 173 }; 174 175 enum OpalEehFreezeActionToken { 176 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 177 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 178 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, 179 180 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, 181 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, 182 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 183 }; 184 185 enum OpalPciStatusToken { 186 OPAL_EEH_NO_ERROR = 0, 187 OPAL_EEH_IOC_ERROR = 1, 188 OPAL_EEH_PHB_ERROR = 2, 189 OPAL_EEH_PE_ERROR = 3, 190 OPAL_EEH_PE_MMIO_ERROR = 4, 191 OPAL_EEH_PE_DMA_ERROR = 5 192 }; 193 194 enum OpalPciErrorSeverity { 195 OPAL_EEH_SEV_NO_ERROR = 0, 196 OPAL_EEH_SEV_IOC_DEAD = 1, 197 OPAL_EEH_SEV_PHB_DEAD = 2, 198 OPAL_EEH_SEV_PHB_FENCED = 3, 199 OPAL_EEH_SEV_PE_ER = 4, 200 OPAL_EEH_SEV_INF = 5 201 }; 202 203 enum OpalShpcAction { 204 OPAL_SHPC_GET_LINK_STATE = 0, 205 OPAL_SHPC_GET_SLOT_STATE = 1 206 }; 207 208 enum OpalShpcLinkState { 209 OPAL_SHPC_LINK_DOWN = 0, 210 OPAL_SHPC_LINK_UP = 1 211 }; 212 213 enum OpalMmioWindowType { 214 OPAL_M32_WINDOW_TYPE = 1, 215 OPAL_M64_WINDOW_TYPE = 2, 216 OPAL_IO_WINDOW_TYPE = 3 217 }; 218 219 enum OpalShpcSlotState { 220 OPAL_SHPC_DEV_NOT_PRESENT = 0, 221 OPAL_SHPC_DEV_PRESENT = 1 222 }; 223 224 enum OpalExceptionHandler { 225 OPAL_MACHINE_CHECK_HANDLER = 1, 226 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 227 OPAL_SOFTPATCH_HANDLER = 3 228 }; 229 230 enum OpalPendingState { 231 OPAL_EVENT_OPAL_INTERNAL = 0x1, 232 OPAL_EVENT_NVRAM = 0x2, 233 OPAL_EVENT_RTC = 0x4, 234 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 235 OPAL_EVENT_CONSOLE_INPUT = 0x10, 236 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 237 OPAL_EVENT_ERROR_LOG = 0x40, 238 OPAL_EVENT_EPOW = 0x80, 239 OPAL_EVENT_LED_STATUS = 0x100, 240 OPAL_EVENT_PCI_ERROR = 0x200, 241 OPAL_EVENT_DUMP_AVAIL = 0x400, 242 OPAL_EVENT_MSG_PENDING = 0x800, 243 }; 244 245 enum OpalMessageType { 246 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, 247 * additional params function-specific 248 */ 249 OPAL_MSG_MEM_ERR, 250 OPAL_MSG_EPOW, 251 OPAL_MSG_SHUTDOWN, 252 OPAL_MSG_HMI_EVT, 253 OPAL_MSG_TYPE_MAX, 254 }; 255 256 /* Machine check related definitions */ 257 enum OpalMCE_Version { 258 OpalMCE_V1 = 1, 259 }; 260 261 enum OpalMCE_Severity { 262 OpalMCE_SEV_NO_ERROR = 0, 263 OpalMCE_SEV_WARNING = 1, 264 OpalMCE_SEV_ERROR_SYNC = 2, 265 OpalMCE_SEV_FATAL = 3, 266 }; 267 268 enum OpalMCE_Disposition { 269 OpalMCE_DISPOSITION_RECOVERED = 0, 270 OpalMCE_DISPOSITION_NOT_RECOVERED = 1, 271 }; 272 273 enum OpalMCE_Initiator { 274 OpalMCE_INITIATOR_UNKNOWN = 0, 275 OpalMCE_INITIATOR_CPU = 1, 276 }; 277 278 enum OpalMCE_ErrorType { 279 OpalMCE_ERROR_TYPE_UNKNOWN = 0, 280 OpalMCE_ERROR_TYPE_UE = 1, 281 OpalMCE_ERROR_TYPE_SLB = 2, 282 OpalMCE_ERROR_TYPE_ERAT = 3, 283 OpalMCE_ERROR_TYPE_TLB = 4, 284 }; 285 286 enum OpalMCE_UeErrorType { 287 OpalMCE_UE_ERROR_INDETERMINATE = 0, 288 OpalMCE_UE_ERROR_IFETCH = 1, 289 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2, 290 OpalMCE_UE_ERROR_LOAD_STORE = 3, 291 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4, 292 }; 293 294 enum OpalMCE_SlbErrorType { 295 OpalMCE_SLB_ERROR_INDETERMINATE = 0, 296 OpalMCE_SLB_ERROR_PARITY = 1, 297 OpalMCE_SLB_ERROR_MULTIHIT = 2, 298 }; 299 300 enum OpalMCE_EratErrorType { 301 OpalMCE_ERAT_ERROR_INDETERMINATE = 0, 302 OpalMCE_ERAT_ERROR_PARITY = 1, 303 OpalMCE_ERAT_ERROR_MULTIHIT = 2, 304 }; 305 306 enum OpalMCE_TlbErrorType { 307 OpalMCE_TLB_ERROR_INDETERMINATE = 0, 308 OpalMCE_TLB_ERROR_PARITY = 1, 309 OpalMCE_TLB_ERROR_MULTIHIT = 2, 310 }; 311 312 enum OpalThreadStatus { 313 OPAL_THREAD_INACTIVE = 0x0, 314 OPAL_THREAD_STARTED = 0x1, 315 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 316 }; 317 318 enum OpalPciBusCompare { 319 OpalPciBusAny = 0, /* Any bus number match */ 320 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 321 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 322 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 323 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 324 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 325 OpalPciBusAll = 7, /* Match bus number exactly */ 326 }; 327 328 enum OpalDeviceCompare { 329 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 330 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 331 }; 332 333 enum OpalFuncCompare { 334 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 335 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 336 }; 337 338 enum OpalPeAction { 339 OPAL_UNMAP_PE = 0, 340 OPAL_MAP_PE = 1 341 }; 342 343 enum OpalPeltvAction { 344 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 345 OPAL_ADD_PE_TO_DOMAIN = 1 346 }; 347 348 enum OpalMveEnableAction { 349 OPAL_DISABLE_MVE = 0, 350 OPAL_ENABLE_MVE = 1 351 }; 352 353 enum OpalM64EnableAction { 354 OPAL_DISABLE_M64 = 0, 355 OPAL_ENABLE_M64_SPLIT = 1, 356 OPAL_ENABLE_M64_NON_SPLIT = 2 357 }; 358 359 enum OpalPciResetScope { 360 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, 361 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, 362 OPAL_PCI_IODA_TABLE_RESET = 6, 363 }; 364 365 enum OpalPciReinitScope { 366 OPAL_REINIT_PCI_DEV = 1000 367 }; 368 369 enum OpalPciResetState { 370 OPAL_DEASSERT_RESET = 0, 371 OPAL_ASSERT_RESET = 1 372 }; 373 374 enum OpalPciMaskAction { 375 OPAL_UNMASK_ERROR_TYPE = 0, 376 OPAL_MASK_ERROR_TYPE = 1 377 }; 378 379 enum OpalSlotLedType { 380 OPAL_SLOT_LED_ID_TYPE = 0, 381 OPAL_SLOT_LED_FAULT_TYPE = 1 382 }; 383 384 enum OpalLedAction { 385 OPAL_TURN_OFF_LED = 0, 386 OPAL_TURN_ON_LED = 1, 387 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2 388 }; 389 390 enum OpalEpowStatus { 391 OPAL_EPOW_NONE = 0, 392 OPAL_EPOW_UPS = 1, 393 OPAL_EPOW_OVER_AMBIENT_TEMP = 2, 394 OPAL_EPOW_OVER_INTERNAL_TEMP = 3 395 }; 396 397 /* 398 * Address cycle types for LPC accesses. These also correspond 399 * to the content of the first cell of the "reg" property for 400 * device nodes on the LPC bus 401 */ 402 enum OpalLPCAddressType { 403 OPAL_LPC_MEM = 0, 404 OPAL_LPC_IO = 1, 405 OPAL_LPC_FW = 2, 406 }; 407 408 /* System parameter permission */ 409 enum OpalSysparamPerm { 410 OPAL_SYSPARAM_READ = 0x1, 411 OPAL_SYSPARAM_WRITE = 0x2, 412 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), 413 }; 414 415 struct opal_msg { 416 __be32 msg_type; 417 __be32 reserved; 418 __be64 params[8]; 419 }; 420 421 struct opal_machine_check_event { 422 enum OpalMCE_Version version:8; /* 0x00 */ 423 uint8_t in_use; /* 0x01 */ 424 enum OpalMCE_Severity severity:8; /* 0x02 */ 425 enum OpalMCE_Initiator initiator:8; /* 0x03 */ 426 enum OpalMCE_ErrorType error_type:8; /* 0x04 */ 427 enum OpalMCE_Disposition disposition:8; /* 0x05 */ 428 uint8_t reserved_1[2]; /* 0x06 */ 429 uint64_t gpr3; /* 0x08 */ 430 uint64_t srr0; /* 0x10 */ 431 uint64_t srr1; /* 0x18 */ 432 union { /* 0x20 */ 433 struct { 434 enum OpalMCE_UeErrorType ue_error_type:8; 435 uint8_t effective_address_provided; 436 uint8_t physical_address_provided; 437 uint8_t reserved_1[5]; 438 uint64_t effective_address; 439 uint64_t physical_address; 440 uint8_t reserved_2[8]; 441 } ue_error; 442 443 struct { 444 enum OpalMCE_SlbErrorType slb_error_type:8; 445 uint8_t effective_address_provided; 446 uint8_t reserved_1[6]; 447 uint64_t effective_address; 448 uint8_t reserved_2[16]; 449 } slb_error; 450 451 struct { 452 enum OpalMCE_EratErrorType erat_error_type:8; 453 uint8_t effective_address_provided; 454 uint8_t reserved_1[6]; 455 uint64_t effective_address; 456 uint8_t reserved_2[16]; 457 } erat_error; 458 459 struct { 460 enum OpalMCE_TlbErrorType tlb_error_type:8; 461 uint8_t effective_address_provided; 462 uint8_t reserved_1[6]; 463 uint64_t effective_address; 464 uint8_t reserved_2[16]; 465 } tlb_error; 466 } u; 467 }; 468 469 /* FSP memory errors handling */ 470 enum OpalMemErr_Version { 471 OpalMemErr_V1 = 1, 472 }; 473 474 enum OpalMemErrType { 475 OPAL_MEM_ERR_TYPE_RESILIENCE = 0, 476 OPAL_MEM_ERR_TYPE_DYN_DALLOC, 477 OPAL_MEM_ERR_TYPE_SCRUB, 478 }; 479 480 /* Memory Reilience error type */ 481 enum OpalMemErr_ResilErrType { 482 OPAL_MEM_RESILIENCE_CE = 0, 483 OPAL_MEM_RESILIENCE_UE, 484 OPAL_MEM_RESILIENCE_UE_SCRUB, 485 }; 486 487 /* Dynamic Memory Deallocation type */ 488 enum OpalMemErr_DynErrType { 489 OPAL_MEM_DYNAMIC_DEALLOC = 0, 490 }; 491 492 /* OpalMemoryErrorData->flags */ 493 #define OPAL_MEM_CORRECTED_ERROR 0x0001 494 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002 495 #define OPAL_MEM_ACK_REQUIRED 0x8000 496 497 struct OpalMemoryErrorData { 498 enum OpalMemErr_Version version:8; /* 0x00 */ 499 enum OpalMemErrType type:8; /* 0x01 */ 500 __be16 flags; /* 0x02 */ 501 uint8_t reserved_1[4]; /* 0x04 */ 502 503 union { 504 /* Memory Resilience corrected/uncorrected error info */ 505 struct { 506 enum OpalMemErr_ResilErrType resil_err_type:8; 507 uint8_t reserved_1[7]; 508 __be64 physical_address_start; 509 __be64 physical_address_end; 510 } resilience; 511 /* Dynamic memory deallocation error info */ 512 struct { 513 enum OpalMemErr_DynErrType dyn_err_type:8; 514 uint8_t reserved_1[7]; 515 __be64 physical_address_start; 516 __be64 physical_address_end; 517 } dyn_dealloc; 518 } u; 519 }; 520 521 /* HMI interrupt event */ 522 enum OpalHMI_Version { 523 OpalHMIEvt_V1 = 1, 524 }; 525 526 enum OpalHMI_Severity { 527 OpalHMI_SEV_NO_ERROR = 0, 528 OpalHMI_SEV_WARNING = 1, 529 OpalHMI_SEV_ERROR_SYNC = 2, 530 OpalHMI_SEV_FATAL = 3, 531 }; 532 533 enum OpalHMI_Disposition { 534 OpalHMI_DISPOSITION_RECOVERED = 0, 535 OpalHMI_DISPOSITION_NOT_RECOVERED = 1, 536 }; 537 538 enum OpalHMI_ErrType { 539 OpalHMI_ERROR_MALFUNC_ALERT = 0, 540 OpalHMI_ERROR_PROC_RECOV_DONE, 541 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, 542 OpalHMI_ERROR_PROC_RECOV_MASKED, 543 OpalHMI_ERROR_TFAC, 544 OpalHMI_ERROR_TFMR_PARITY, 545 OpalHMI_ERROR_HA_OVERFLOW_WARN, 546 OpalHMI_ERROR_XSCOM_FAIL, 547 OpalHMI_ERROR_XSCOM_DONE, 548 OpalHMI_ERROR_SCOM_FIR, 549 OpalHMI_ERROR_DEBUG_TRIG_FIR, 550 OpalHMI_ERROR_HYP_RESOURCE, 551 }; 552 553 struct OpalHMIEvent { 554 uint8_t version; /* 0x00 */ 555 uint8_t severity; /* 0x01 */ 556 uint8_t type; /* 0x02 */ 557 uint8_t disposition; /* 0x03 */ 558 uint8_t reserved_1[4]; /* 0x04 */ 559 560 __be64 hmer; 561 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ 562 __be64 tfmr; 563 }; 564 565 enum { 566 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 567 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 568 OPAL_P7IOC_DIAG_TYPE_BI = 2, 569 OPAL_P7IOC_DIAG_TYPE_CI = 3, 570 OPAL_P7IOC_DIAG_TYPE_MISC = 4, 571 OPAL_P7IOC_DIAG_TYPE_I2C = 5, 572 OPAL_P7IOC_DIAG_TYPE_LAST = 6 573 }; 574 575 struct OpalIoP7IOCErrorData { 576 __be16 type; 577 578 /* GEM */ 579 __be64 gemXfir; 580 __be64 gemRfir; 581 __be64 gemRirqfir; 582 __be64 gemMask; 583 __be64 gemRwof; 584 585 /* LEM */ 586 __be64 lemFir; 587 __be64 lemErrMask; 588 __be64 lemAction0; 589 __be64 lemAction1; 590 __be64 lemWof; 591 592 union { 593 struct OpalIoP7IOCRgcErrorData { 594 __be64 rgcStatus; /* 3E1C10 */ 595 __be64 rgcLdcp; /* 3E1C18 */ 596 }rgc; 597 struct OpalIoP7IOCBiErrorData { 598 __be64 biLdcp0; /* 3C0100, 3C0118 */ 599 __be64 biLdcp1; /* 3C0108, 3C0120 */ 600 __be64 biLdcp2; /* 3C0110, 3C0128 */ 601 __be64 biFenceStatus; /* 3C0130, 3C0130 */ 602 603 u8 biDownbound; /* BI Downbound or Upbound */ 604 }bi; 605 struct OpalIoP7IOCCiErrorData { 606 __be64 ciPortStatus; /* 3Dn008 */ 607 __be64 ciPortLdcp; /* 3Dn010 */ 608 609 u8 ciPort; /* Index of CI port: 0/1 */ 610 }ci; 611 }; 612 }; 613 614 /** 615 * This structure defines the overlay which will be used to store PHB error 616 * data upon request. 617 */ 618 enum { 619 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 620 }; 621 622 enum { 623 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, 624 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2 625 }; 626 627 enum { 628 OPAL_P7IOC_NUM_PEST_REGS = 128, 629 OPAL_PHB3_NUM_PEST_REGS = 256 630 }; 631 632 struct OpalIoPhbErrorCommon { 633 __be32 version; 634 __be32 ioType; 635 __be32 len; 636 }; 637 638 struct OpalIoP7IOCPhbErrorData { 639 struct OpalIoPhbErrorCommon common; 640 641 __be32 brdgCtl; 642 643 // P7IOC utl regs 644 __be32 portStatusReg; 645 __be32 rootCmplxStatus; 646 __be32 busAgentStatus; 647 648 // P7IOC cfg regs 649 __be32 deviceStatus; 650 __be32 slotStatus; 651 __be32 linkStatus; 652 __be32 devCmdStatus; 653 __be32 devSecStatus; 654 655 // cfg AER regs 656 __be32 rootErrorStatus; 657 __be32 uncorrErrorStatus; 658 __be32 corrErrorStatus; 659 __be32 tlpHdr1; 660 __be32 tlpHdr2; 661 __be32 tlpHdr3; 662 __be32 tlpHdr4; 663 __be32 sourceId; 664 665 __be32 rsv3; 666 667 // Record data about the call to allocate a buffer. 668 __be64 errorClass; 669 __be64 correlator; 670 671 //P7IOC MMIO Error Regs 672 __be64 p7iocPlssr; // n120 673 __be64 p7iocCsr; // n110 674 __be64 lemFir; // nC00 675 __be64 lemErrorMask; // nC18 676 __be64 lemWOF; // nC40 677 __be64 phbErrorStatus; // nC80 678 __be64 phbFirstErrorStatus; // nC88 679 __be64 phbErrorLog0; // nCC0 680 __be64 phbErrorLog1; // nCC8 681 __be64 mmioErrorStatus; // nD00 682 __be64 mmioFirstErrorStatus; // nD08 683 __be64 mmioErrorLog0; // nD40 684 __be64 mmioErrorLog1; // nD48 685 __be64 dma0ErrorStatus; // nD80 686 __be64 dma0FirstErrorStatus; // nD88 687 __be64 dma0ErrorLog0; // nDC0 688 __be64 dma0ErrorLog1; // nDC8 689 __be64 dma1ErrorStatus; // nE00 690 __be64 dma1FirstErrorStatus; // nE08 691 __be64 dma1ErrorLog0; // nE40 692 __be64 dma1ErrorLog1; // nE48 693 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS]; 694 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS]; 695 }; 696 697 struct OpalIoPhb3ErrorData { 698 struct OpalIoPhbErrorCommon common; 699 700 __be32 brdgCtl; 701 702 /* PHB3 UTL regs */ 703 __be32 portStatusReg; 704 __be32 rootCmplxStatus; 705 __be32 busAgentStatus; 706 707 /* PHB3 cfg regs */ 708 __be32 deviceStatus; 709 __be32 slotStatus; 710 __be32 linkStatus; 711 __be32 devCmdStatus; 712 __be32 devSecStatus; 713 714 /* cfg AER regs */ 715 __be32 rootErrorStatus; 716 __be32 uncorrErrorStatus; 717 __be32 corrErrorStatus; 718 __be32 tlpHdr1; 719 __be32 tlpHdr2; 720 __be32 tlpHdr3; 721 __be32 tlpHdr4; 722 __be32 sourceId; 723 724 __be32 rsv3; 725 726 /* Record data about the call to allocate a buffer */ 727 __be64 errorClass; 728 __be64 correlator; 729 730 __be64 nFir; /* 000 */ 731 __be64 nFirMask; /* 003 */ 732 __be64 nFirWOF; /* 008 */ 733 734 /* PHB3 MMIO Error Regs */ 735 __be64 phbPlssr; /* 120 */ 736 __be64 phbCsr; /* 110 */ 737 __be64 lemFir; /* C00 */ 738 __be64 lemErrorMask; /* C18 */ 739 __be64 lemWOF; /* C40 */ 740 __be64 phbErrorStatus; /* C80 */ 741 __be64 phbFirstErrorStatus; /* C88 */ 742 __be64 phbErrorLog0; /* CC0 */ 743 __be64 phbErrorLog1; /* CC8 */ 744 __be64 mmioErrorStatus; /* D00 */ 745 __be64 mmioFirstErrorStatus; /* D08 */ 746 __be64 mmioErrorLog0; /* D40 */ 747 __be64 mmioErrorLog1; /* D48 */ 748 __be64 dma0ErrorStatus; /* D80 */ 749 __be64 dma0FirstErrorStatus; /* D88 */ 750 __be64 dma0ErrorLog0; /* DC0 */ 751 __be64 dma0ErrorLog1; /* DC8 */ 752 __be64 dma1ErrorStatus; /* E00 */ 753 __be64 dma1FirstErrorStatus; /* E08 */ 754 __be64 dma1ErrorLog0; /* E40 */ 755 __be64 dma1ErrorLog1; /* E48 */ 756 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; 757 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; 758 }; 759 760 enum { 761 OPAL_REINIT_CPUS_HILE_BE = (1 << 0), 762 OPAL_REINIT_CPUS_HILE_LE = (1 << 1), 763 }; 764 765 typedef struct oppanel_line { 766 const char * line; 767 uint64_t line_len; 768 } oppanel_line_t; 769 770 /* /sys/firmware/opal */ 771 extern struct kobject *opal_kobj; 772 773 /* /ibm,opal */ 774 extern struct device_node *opal_node; 775 776 /* API functions */ 777 int64_t opal_invalid_call(void); 778 int64_t opal_console_write(int64_t term_number, __be64 *length, 779 const uint8_t *buffer); 780 int64_t opal_console_read(int64_t term_number, __be64 *length, 781 uint8_t *buffer); 782 int64_t opal_console_write_buffer_space(int64_t term_number, 783 __be64 *length); 784 int64_t opal_rtc_read(__be32 *year_month_day, 785 __be64 *hour_minute_second_millisecond); 786 int64_t opal_rtc_write(uint32_t year_month_day, 787 uint64_t hour_minute_second_millisecond); 788 int64_t opal_cec_power_down(uint64_t request); 789 int64_t opal_cec_reboot(void); 790 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 791 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 792 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask); 793 int64_t opal_poll_events(__be64 *outstanding_event_mask); 794 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr, 795 uint64_t tce_mem_size); 796 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr, 797 uint64_t tce_mem_size); 798 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func, 799 uint64_t offset, uint8_t *data); 800 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func, 801 uint64_t offset, __be16 *data); 802 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func, 803 uint64_t offset, __be32 *data); 804 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func, 805 uint64_t offset, uint8_t data); 806 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func, 807 uint64_t offset, uint16_t data); 808 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func, 809 uint64_t offset, uint32_t data); 810 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); 811 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority); 812 int64_t opal_register_exception_handler(uint64_t opal_exception, 813 uint64_t handler_address, 814 uint64_t glue_cache_line); 815 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, 816 uint8_t *freeze_state, 817 __be16 *pci_error_type, 818 __be64 *phb_status); 819 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, 820 uint64_t eeh_action_token); 821 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number, 822 uint64_t eeh_action_token); 823 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state); 824 825 826 827 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, 828 uint16_t window_num, uint16_t enable); 829 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, 830 uint16_t window_num, 831 uint64_t starting_real_address, 832 uint64_t starting_pci_address, 833 uint64_t size); 834 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, 835 uint16_t window_type, uint16_t window_num, 836 uint16_t segment_num); 837 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr, 838 uint64_t ivt_addr, uint64_t ivt_len, 839 uint64_t reject_array_addr, 840 uint64_t peltv_addr); 841 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func, 842 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare, 843 uint8_t pe_action); 844 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, 845 uint8_t state); 846 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); 847 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, 848 uint32_t state); 849 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, 850 uint8_t *p_bit, uint8_t *q_bit); 851 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, 852 uint8_t p_bit, uint8_t q_bit); 853 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); 854 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, 855 uint32_t xive_num); 856 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, 857 __be32 *interrupt_source_number); 858 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, 859 uint8_t msi_range, __be32 *msi_address, 860 __be32 *message_data); 861 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, 862 uint32_t xive_num, uint8_t msi_range, 863 __be64 *msi_address, __be32 *message_data); 864 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address); 865 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status); 866 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines); 867 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id, 868 uint16_t tce_levels, uint64_t tce_table_addr, 869 uint64_t tce_table_size, uint64_t tce_page_size); 870 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number, 871 uint16_t dma_window_number, uint64_t pci_start_addr, 872 uint64_t pci_mem_size); 873 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state); 874 875 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, 876 uint64_t diag_buffer_len); 877 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, 878 uint64_t diag_buffer_len); 879 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, 880 uint64_t diag_buffer_len); 881 int64_t opal_pci_fence_phb(uint64_t phb_id); 882 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data); 883 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); 884 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); 885 int64_t opal_get_epow_status(__be64 *status); 886 int64_t opal_set_system_attention_led(uint8_t led_action); 887 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe, 888 __be16 *pci_error_type, __be16 *severity); 889 int64_t opal_pci_poll(uint64_t phb_id); 890 int64_t opal_return_cpu(void); 891 int64_t opal_check_token(uint64_t token); 892 int64_t opal_reinit_cpus(uint64_t flags); 893 894 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val); 895 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val); 896 897 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, 898 uint32_t addr, uint32_t data, uint32_t sz); 899 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, 900 uint32_t addr, __be32 *data, uint32_t sz); 901 902 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id); 903 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type); 904 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset); 905 int64_t opal_send_ack_elog(uint64_t log_id); 906 void opal_resend_pending_logs(void); 907 908 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); 909 int64_t opal_manage_flash(uint8_t op); 910 int64_t opal_update_flash(uint64_t blk_list); 911 int64_t opal_dump_init(uint8_t dump_type); 912 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size); 913 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type); 914 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer); 915 int64_t opal_dump_ack(uint32_t dump_id); 916 int64_t opal_dump_resend_notification(void); 917 918 int64_t opal_get_msg(uint64_t buffer, uint64_t size); 919 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token); 920 int64_t opal_sync_host_reboot(void); 921 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer, 922 uint64_t length); 923 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer, 924 uint64_t length); 925 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data); 926 int64_t opal_handle_hmi(void); 927 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end); 928 int64_t opal_unregister_dump_region(uint32_t id); 929 930 /* Internal functions */ 931 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, 932 int depth, void *data); 933 extern int early_init_dt_scan_recoverable_ranges(unsigned long node, 934 const char *uname, int depth, void *data); 935 936 extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 937 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 938 939 extern void hvc_opal_init_early(void); 940 941 extern int opal_notifier_register(struct notifier_block *nb); 942 extern int opal_notifier_unregister(struct notifier_block *nb); 943 944 extern int opal_message_notifier_register(enum OpalMessageType msg_type, 945 struct notifier_block *nb); 946 extern void opal_notifier_enable(void); 947 extern void opal_notifier_disable(void); 948 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 949 950 extern int __opal_async_get_token(void); 951 extern int opal_async_get_token_interruptible(void); 952 extern int __opal_async_release_token(int token); 953 extern int opal_async_release_token(int token); 954 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg); 955 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data); 956 957 struct rtc_time; 958 extern int opal_set_rtc_time(struct rtc_time *tm); 959 extern void opal_get_rtc_time(struct rtc_time *tm); 960 extern unsigned long opal_get_boot_time(void); 961 extern void opal_nvram_init(void); 962 extern void opal_flash_init(void); 963 extern void opal_flash_term_callback(void); 964 extern int opal_elog_init(void); 965 extern void opal_platform_dump_init(void); 966 extern void opal_sys_param_init(void); 967 extern void opal_msglog_init(void); 968 969 extern int opal_machine_check(struct pt_regs *regs); 970 extern bool opal_mce_check_early_recovery(struct pt_regs *regs); 971 extern int opal_hmi_exception_early(struct pt_regs *regs); 972 extern int opal_handle_hmi_exception(struct pt_regs *regs); 973 974 extern void opal_shutdown(void); 975 extern int opal_resync_timebase(void); 976 977 extern void opal_lpc_init(void); 978 979 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr, 980 unsigned long vmalloc_size); 981 void opal_free_sg_list(struct opal_sg_list *sg); 982 983 /* 984 * Dump region ID range usable by the OS 985 */ 986 #define OPAL_DUMP_REGION_HOST_START 0x80 987 #define OPAL_DUMP_REGION_LOG_BUF 0x80 988 #define OPAL_DUMP_REGION_HOST_END 0xFF 989 990 #endif /* __ASSEMBLY__ */ 991 992 #endif /* __OPAL_H */ 993