1 /* 2 * PowerNV OPAL definitions. 3 * 4 * Copyright 2011 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef __OPAL_H 13 #define __OPAL_H 14 15 #ifndef __ASSEMBLY__ 16 /* 17 * SG entry 18 * 19 * WARNING: The current implementation requires each entry 20 * to represent a block that is 4k aligned *and* each block 21 * size except the last one in the list to be as well. 22 */ 23 struct opal_sg_entry { 24 __be64 data; 25 __be64 length; 26 }; 27 28 /* SG list */ 29 struct opal_sg_list { 30 __be64 length; 31 __be64 next; 32 struct opal_sg_entry entry[]; 33 }; 34 35 /* We calculate number of sg entries based on PAGE_SIZE */ 36 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry)) 37 38 #endif /* __ASSEMBLY__ */ 39 40 /****** OPAL APIs ******/ 41 42 /* Return codes */ 43 #define OPAL_SUCCESS 0 44 #define OPAL_PARAMETER -1 45 #define OPAL_BUSY -2 46 #define OPAL_PARTIAL -3 47 #define OPAL_CONSTRAINED -4 48 #define OPAL_CLOSED -5 49 #define OPAL_HARDWARE -6 50 #define OPAL_UNSUPPORTED -7 51 #define OPAL_PERMISSION -8 52 #define OPAL_NO_MEM -9 53 #define OPAL_RESOURCE -10 54 #define OPAL_INTERNAL_ERROR -11 55 #define OPAL_BUSY_EVENT -12 56 #define OPAL_HARDWARE_FROZEN -13 57 #define OPAL_WRONG_STATE -14 58 #define OPAL_ASYNC_COMPLETION -15 59 60 /* API Tokens (in r0) */ 61 #define OPAL_INVALID_CALL -1 62 #define OPAL_CONSOLE_WRITE 1 63 #define OPAL_CONSOLE_READ 2 64 #define OPAL_RTC_READ 3 65 #define OPAL_RTC_WRITE 4 66 #define OPAL_CEC_POWER_DOWN 5 67 #define OPAL_CEC_REBOOT 6 68 #define OPAL_READ_NVRAM 7 69 #define OPAL_WRITE_NVRAM 8 70 #define OPAL_HANDLE_INTERRUPT 9 71 #define OPAL_POLL_EVENTS 10 72 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 73 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 74 #define OPAL_PCI_CONFIG_READ_BYTE 13 75 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 76 #define OPAL_PCI_CONFIG_READ_WORD 15 77 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 78 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 79 #define OPAL_PCI_CONFIG_WRITE_WORD 18 80 #define OPAL_SET_XIVE 19 81 #define OPAL_GET_XIVE 20 82 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 83 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 84 #define OPAL_PCI_EEH_FREEZE_STATUS 23 85 #define OPAL_PCI_SHPC 24 86 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 87 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 88 #define OPAL_PCI_PHB_MMIO_ENABLE 27 89 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 90 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 91 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 92 #define OPAL_PCI_SET_PE 31 93 #define OPAL_PCI_SET_PELTV 32 94 #define OPAL_PCI_SET_MVE 33 95 #define OPAL_PCI_SET_MVE_ENABLE 34 96 #define OPAL_PCI_GET_XIVE_REISSUE 35 97 #define OPAL_PCI_SET_XIVE_REISSUE 36 98 #define OPAL_PCI_SET_XIVE_PE 37 99 #define OPAL_GET_XIVE_SOURCE 38 100 #define OPAL_GET_MSI_32 39 101 #define OPAL_GET_MSI_64 40 102 #define OPAL_START_CPU 41 103 #define OPAL_QUERY_CPU_STATUS 42 104 #define OPAL_WRITE_OPPANEL 43 105 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 106 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 107 #define OPAL_PCI_RESET 49 108 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 109 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 110 #define OPAL_PCI_FENCE_PHB 52 111 #define OPAL_PCI_REINIT 53 112 #define OPAL_PCI_MASK_PE_ERROR 54 113 #define OPAL_SET_SLOT_LED_STATUS 55 114 #define OPAL_GET_EPOW_STATUS 56 115 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 116 #define OPAL_RESERVED1 58 117 #define OPAL_RESERVED2 59 118 #define OPAL_PCI_NEXT_ERROR 60 119 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 120 #define OPAL_PCI_POLL 62 121 #define OPAL_PCI_MSI_EOI 63 122 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 123 #define OPAL_XSCOM_READ 65 124 #define OPAL_XSCOM_WRITE 66 125 #define OPAL_LPC_READ 67 126 #define OPAL_LPC_WRITE 68 127 #define OPAL_RETURN_CPU 69 128 #define OPAL_REINIT_CPUS 70 129 #define OPAL_ELOG_READ 71 130 #define OPAL_ELOG_WRITE 72 131 #define OPAL_ELOG_ACK 73 132 #define OPAL_ELOG_RESEND 74 133 #define OPAL_ELOG_SIZE 75 134 #define OPAL_FLASH_VALIDATE 76 135 #define OPAL_FLASH_MANAGE 77 136 #define OPAL_FLASH_UPDATE 78 137 #define OPAL_RESYNC_TIMEBASE 79 138 #define OPAL_DUMP_INIT 81 139 #define OPAL_DUMP_INFO 82 140 #define OPAL_DUMP_READ 83 141 #define OPAL_DUMP_ACK 84 142 #define OPAL_GET_MSG 85 143 #define OPAL_CHECK_ASYNC_COMPLETION 86 144 #define OPAL_SYNC_HOST_REBOOT 87 145 #define OPAL_SENSOR_READ 88 146 #define OPAL_GET_PARAM 89 147 #define OPAL_SET_PARAM 90 148 #define OPAL_DUMP_RESEND 91 149 #define OPAL_DUMP_INFO2 94 150 #define OPAL_PCI_EEH_FREEZE_SET 97 151 #define OPAL_HANDLE_HMI 98 152 153 #ifndef __ASSEMBLY__ 154 155 #include <linux/notifier.h> 156 157 /* Other enums */ 158 enum OpalVendorApiTokens { 159 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999 160 }; 161 162 enum OpalFreezeState { 163 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 164 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 165 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 166 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 167 OPAL_EEH_STOPPED_RESET = 4, 168 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 169 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 170 }; 171 172 enum OpalEehFreezeActionToken { 173 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 174 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 175 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, 176 177 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, 178 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, 179 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 180 }; 181 182 enum OpalPciStatusToken { 183 OPAL_EEH_NO_ERROR = 0, 184 OPAL_EEH_IOC_ERROR = 1, 185 OPAL_EEH_PHB_ERROR = 2, 186 OPAL_EEH_PE_ERROR = 3, 187 OPAL_EEH_PE_MMIO_ERROR = 4, 188 OPAL_EEH_PE_DMA_ERROR = 5 189 }; 190 191 enum OpalPciErrorSeverity { 192 OPAL_EEH_SEV_NO_ERROR = 0, 193 OPAL_EEH_SEV_IOC_DEAD = 1, 194 OPAL_EEH_SEV_PHB_DEAD = 2, 195 OPAL_EEH_SEV_PHB_FENCED = 3, 196 OPAL_EEH_SEV_PE_ER = 4, 197 OPAL_EEH_SEV_INF = 5 198 }; 199 200 enum OpalShpcAction { 201 OPAL_SHPC_GET_LINK_STATE = 0, 202 OPAL_SHPC_GET_SLOT_STATE = 1 203 }; 204 205 enum OpalShpcLinkState { 206 OPAL_SHPC_LINK_DOWN = 0, 207 OPAL_SHPC_LINK_UP = 1 208 }; 209 210 enum OpalMmioWindowType { 211 OPAL_M32_WINDOW_TYPE = 1, 212 OPAL_M64_WINDOW_TYPE = 2, 213 OPAL_IO_WINDOW_TYPE = 3 214 }; 215 216 enum OpalShpcSlotState { 217 OPAL_SHPC_DEV_NOT_PRESENT = 0, 218 OPAL_SHPC_DEV_PRESENT = 1 219 }; 220 221 enum OpalExceptionHandler { 222 OPAL_MACHINE_CHECK_HANDLER = 1, 223 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 224 OPAL_SOFTPATCH_HANDLER = 3 225 }; 226 227 enum OpalPendingState { 228 OPAL_EVENT_OPAL_INTERNAL = 0x1, 229 OPAL_EVENT_NVRAM = 0x2, 230 OPAL_EVENT_RTC = 0x4, 231 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 232 OPAL_EVENT_CONSOLE_INPUT = 0x10, 233 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 234 OPAL_EVENT_ERROR_LOG = 0x40, 235 OPAL_EVENT_EPOW = 0x80, 236 OPAL_EVENT_LED_STATUS = 0x100, 237 OPAL_EVENT_PCI_ERROR = 0x200, 238 OPAL_EVENT_DUMP_AVAIL = 0x400, 239 OPAL_EVENT_MSG_PENDING = 0x800, 240 }; 241 242 enum OpalMessageType { 243 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, 244 * additional params function-specific 245 */ 246 OPAL_MSG_MEM_ERR, 247 OPAL_MSG_EPOW, 248 OPAL_MSG_SHUTDOWN, 249 OPAL_MSG_HMI_EVT, 250 OPAL_MSG_TYPE_MAX, 251 }; 252 253 /* Machine check related definitions */ 254 enum OpalMCE_Version { 255 OpalMCE_V1 = 1, 256 }; 257 258 enum OpalMCE_Severity { 259 OpalMCE_SEV_NO_ERROR = 0, 260 OpalMCE_SEV_WARNING = 1, 261 OpalMCE_SEV_ERROR_SYNC = 2, 262 OpalMCE_SEV_FATAL = 3, 263 }; 264 265 enum OpalMCE_Disposition { 266 OpalMCE_DISPOSITION_RECOVERED = 0, 267 OpalMCE_DISPOSITION_NOT_RECOVERED = 1, 268 }; 269 270 enum OpalMCE_Initiator { 271 OpalMCE_INITIATOR_UNKNOWN = 0, 272 OpalMCE_INITIATOR_CPU = 1, 273 }; 274 275 enum OpalMCE_ErrorType { 276 OpalMCE_ERROR_TYPE_UNKNOWN = 0, 277 OpalMCE_ERROR_TYPE_UE = 1, 278 OpalMCE_ERROR_TYPE_SLB = 2, 279 OpalMCE_ERROR_TYPE_ERAT = 3, 280 OpalMCE_ERROR_TYPE_TLB = 4, 281 }; 282 283 enum OpalMCE_UeErrorType { 284 OpalMCE_UE_ERROR_INDETERMINATE = 0, 285 OpalMCE_UE_ERROR_IFETCH = 1, 286 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2, 287 OpalMCE_UE_ERROR_LOAD_STORE = 3, 288 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4, 289 }; 290 291 enum OpalMCE_SlbErrorType { 292 OpalMCE_SLB_ERROR_INDETERMINATE = 0, 293 OpalMCE_SLB_ERROR_PARITY = 1, 294 OpalMCE_SLB_ERROR_MULTIHIT = 2, 295 }; 296 297 enum OpalMCE_EratErrorType { 298 OpalMCE_ERAT_ERROR_INDETERMINATE = 0, 299 OpalMCE_ERAT_ERROR_PARITY = 1, 300 OpalMCE_ERAT_ERROR_MULTIHIT = 2, 301 }; 302 303 enum OpalMCE_TlbErrorType { 304 OpalMCE_TLB_ERROR_INDETERMINATE = 0, 305 OpalMCE_TLB_ERROR_PARITY = 1, 306 OpalMCE_TLB_ERROR_MULTIHIT = 2, 307 }; 308 309 enum OpalThreadStatus { 310 OPAL_THREAD_INACTIVE = 0x0, 311 OPAL_THREAD_STARTED = 0x1, 312 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 313 }; 314 315 enum OpalPciBusCompare { 316 OpalPciBusAny = 0, /* Any bus number match */ 317 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 318 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 319 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 320 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 321 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 322 OpalPciBusAll = 7, /* Match bus number exactly */ 323 }; 324 325 enum OpalDeviceCompare { 326 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 327 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 328 }; 329 330 enum OpalFuncCompare { 331 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 332 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 333 }; 334 335 enum OpalPeAction { 336 OPAL_UNMAP_PE = 0, 337 OPAL_MAP_PE = 1 338 }; 339 340 enum OpalPeltvAction { 341 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 342 OPAL_ADD_PE_TO_DOMAIN = 1 343 }; 344 345 enum OpalMveEnableAction { 346 OPAL_DISABLE_MVE = 0, 347 OPAL_ENABLE_MVE = 1 348 }; 349 350 enum OpalM64EnableAction { 351 OPAL_DISABLE_M64 = 0, 352 OPAL_ENABLE_M64_SPLIT = 1, 353 OPAL_ENABLE_M64_NON_SPLIT = 2 354 }; 355 356 enum OpalPciResetScope { 357 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, 358 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, 359 OPAL_PCI_IODA_TABLE_RESET = 6, 360 }; 361 362 enum OpalPciReinitScope { 363 OPAL_REINIT_PCI_DEV = 1000 364 }; 365 366 enum OpalPciResetState { 367 OPAL_DEASSERT_RESET = 0, 368 OPAL_ASSERT_RESET = 1 369 }; 370 371 enum OpalPciMaskAction { 372 OPAL_UNMASK_ERROR_TYPE = 0, 373 OPAL_MASK_ERROR_TYPE = 1 374 }; 375 376 enum OpalSlotLedType { 377 OPAL_SLOT_LED_ID_TYPE = 0, 378 OPAL_SLOT_LED_FAULT_TYPE = 1 379 }; 380 381 enum OpalLedAction { 382 OPAL_TURN_OFF_LED = 0, 383 OPAL_TURN_ON_LED = 1, 384 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2 385 }; 386 387 enum OpalEpowStatus { 388 OPAL_EPOW_NONE = 0, 389 OPAL_EPOW_UPS = 1, 390 OPAL_EPOW_OVER_AMBIENT_TEMP = 2, 391 OPAL_EPOW_OVER_INTERNAL_TEMP = 3 392 }; 393 394 /* 395 * Address cycle types for LPC accesses. These also correspond 396 * to the content of the first cell of the "reg" property for 397 * device nodes on the LPC bus 398 */ 399 enum OpalLPCAddressType { 400 OPAL_LPC_MEM = 0, 401 OPAL_LPC_IO = 1, 402 OPAL_LPC_FW = 2, 403 }; 404 405 /* System parameter permission */ 406 enum OpalSysparamPerm { 407 OPAL_SYSPARAM_READ = 0x1, 408 OPAL_SYSPARAM_WRITE = 0x2, 409 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), 410 }; 411 412 struct opal_msg { 413 __be32 msg_type; 414 __be32 reserved; 415 __be64 params[8]; 416 }; 417 418 struct opal_machine_check_event { 419 enum OpalMCE_Version version:8; /* 0x00 */ 420 uint8_t in_use; /* 0x01 */ 421 enum OpalMCE_Severity severity:8; /* 0x02 */ 422 enum OpalMCE_Initiator initiator:8; /* 0x03 */ 423 enum OpalMCE_ErrorType error_type:8; /* 0x04 */ 424 enum OpalMCE_Disposition disposition:8; /* 0x05 */ 425 uint8_t reserved_1[2]; /* 0x06 */ 426 uint64_t gpr3; /* 0x08 */ 427 uint64_t srr0; /* 0x10 */ 428 uint64_t srr1; /* 0x18 */ 429 union { /* 0x20 */ 430 struct { 431 enum OpalMCE_UeErrorType ue_error_type:8; 432 uint8_t effective_address_provided; 433 uint8_t physical_address_provided; 434 uint8_t reserved_1[5]; 435 uint64_t effective_address; 436 uint64_t physical_address; 437 uint8_t reserved_2[8]; 438 } ue_error; 439 440 struct { 441 enum OpalMCE_SlbErrorType slb_error_type:8; 442 uint8_t effective_address_provided; 443 uint8_t reserved_1[6]; 444 uint64_t effective_address; 445 uint8_t reserved_2[16]; 446 } slb_error; 447 448 struct { 449 enum OpalMCE_EratErrorType erat_error_type:8; 450 uint8_t effective_address_provided; 451 uint8_t reserved_1[6]; 452 uint64_t effective_address; 453 uint8_t reserved_2[16]; 454 } erat_error; 455 456 struct { 457 enum OpalMCE_TlbErrorType tlb_error_type:8; 458 uint8_t effective_address_provided; 459 uint8_t reserved_1[6]; 460 uint64_t effective_address; 461 uint8_t reserved_2[16]; 462 } tlb_error; 463 } u; 464 }; 465 466 /* FSP memory errors handling */ 467 enum OpalMemErr_Version { 468 OpalMemErr_V1 = 1, 469 }; 470 471 enum OpalMemErrType { 472 OPAL_MEM_ERR_TYPE_RESILIENCE = 0, 473 OPAL_MEM_ERR_TYPE_DYN_DALLOC, 474 OPAL_MEM_ERR_TYPE_SCRUB, 475 }; 476 477 /* Memory Reilience error type */ 478 enum OpalMemErr_ResilErrType { 479 OPAL_MEM_RESILIENCE_CE = 0, 480 OPAL_MEM_RESILIENCE_UE, 481 OPAL_MEM_RESILIENCE_UE_SCRUB, 482 }; 483 484 /* Dynamic Memory Deallocation type */ 485 enum OpalMemErr_DynErrType { 486 OPAL_MEM_DYNAMIC_DEALLOC = 0, 487 }; 488 489 /* OpalMemoryErrorData->flags */ 490 #define OPAL_MEM_CORRECTED_ERROR 0x0001 491 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002 492 #define OPAL_MEM_ACK_REQUIRED 0x8000 493 494 struct OpalMemoryErrorData { 495 enum OpalMemErr_Version version:8; /* 0x00 */ 496 enum OpalMemErrType type:8; /* 0x01 */ 497 __be16 flags; /* 0x02 */ 498 uint8_t reserved_1[4]; /* 0x04 */ 499 500 union { 501 /* Memory Resilience corrected/uncorrected error info */ 502 struct { 503 enum OpalMemErr_ResilErrType resil_err_type:8; 504 uint8_t reserved_1[7]; 505 __be64 physical_address_start; 506 __be64 physical_address_end; 507 } resilience; 508 /* Dynamic memory deallocation error info */ 509 struct { 510 enum OpalMemErr_DynErrType dyn_err_type:8; 511 uint8_t reserved_1[7]; 512 __be64 physical_address_start; 513 __be64 physical_address_end; 514 } dyn_dealloc; 515 } u; 516 }; 517 518 /* HMI interrupt event */ 519 enum OpalHMI_Version { 520 OpalHMIEvt_V1 = 1, 521 }; 522 523 enum OpalHMI_Severity { 524 OpalHMI_SEV_NO_ERROR = 0, 525 OpalHMI_SEV_WARNING = 1, 526 OpalHMI_SEV_ERROR_SYNC = 2, 527 OpalHMI_SEV_FATAL = 3, 528 }; 529 530 enum OpalHMI_Disposition { 531 OpalHMI_DISPOSITION_RECOVERED = 0, 532 OpalHMI_DISPOSITION_NOT_RECOVERED = 1, 533 }; 534 535 enum OpalHMI_ErrType { 536 OpalHMI_ERROR_MALFUNC_ALERT = 0, 537 OpalHMI_ERROR_PROC_RECOV_DONE, 538 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, 539 OpalHMI_ERROR_PROC_RECOV_MASKED, 540 OpalHMI_ERROR_TFAC, 541 OpalHMI_ERROR_TFMR_PARITY, 542 OpalHMI_ERROR_HA_OVERFLOW_WARN, 543 OpalHMI_ERROR_XSCOM_FAIL, 544 OpalHMI_ERROR_XSCOM_DONE, 545 OpalHMI_ERROR_SCOM_FIR, 546 OpalHMI_ERROR_DEBUG_TRIG_FIR, 547 OpalHMI_ERROR_HYP_RESOURCE, 548 }; 549 550 struct OpalHMIEvent { 551 uint8_t version; /* 0x00 */ 552 uint8_t severity; /* 0x01 */ 553 uint8_t type; /* 0x02 */ 554 uint8_t disposition; /* 0x03 */ 555 uint8_t reserved_1[4]; /* 0x04 */ 556 557 __be64 hmer; 558 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ 559 __be64 tfmr; 560 }; 561 562 enum { 563 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 564 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 565 OPAL_P7IOC_DIAG_TYPE_BI = 2, 566 OPAL_P7IOC_DIAG_TYPE_CI = 3, 567 OPAL_P7IOC_DIAG_TYPE_MISC = 4, 568 OPAL_P7IOC_DIAG_TYPE_I2C = 5, 569 OPAL_P7IOC_DIAG_TYPE_LAST = 6 570 }; 571 572 struct OpalIoP7IOCErrorData { 573 __be16 type; 574 575 /* GEM */ 576 __be64 gemXfir; 577 __be64 gemRfir; 578 __be64 gemRirqfir; 579 __be64 gemMask; 580 __be64 gemRwof; 581 582 /* LEM */ 583 __be64 lemFir; 584 __be64 lemErrMask; 585 __be64 lemAction0; 586 __be64 lemAction1; 587 __be64 lemWof; 588 589 union { 590 struct OpalIoP7IOCRgcErrorData { 591 __be64 rgcStatus; /* 3E1C10 */ 592 __be64 rgcLdcp; /* 3E1C18 */ 593 }rgc; 594 struct OpalIoP7IOCBiErrorData { 595 __be64 biLdcp0; /* 3C0100, 3C0118 */ 596 __be64 biLdcp1; /* 3C0108, 3C0120 */ 597 __be64 biLdcp2; /* 3C0110, 3C0128 */ 598 __be64 biFenceStatus; /* 3C0130, 3C0130 */ 599 600 u8 biDownbound; /* BI Downbound or Upbound */ 601 }bi; 602 struct OpalIoP7IOCCiErrorData { 603 __be64 ciPortStatus; /* 3Dn008 */ 604 __be64 ciPortLdcp; /* 3Dn010 */ 605 606 u8 ciPort; /* Index of CI port: 0/1 */ 607 }ci; 608 }; 609 }; 610 611 /** 612 * This structure defines the overlay which will be used to store PHB error 613 * data upon request. 614 */ 615 enum { 616 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 617 }; 618 619 enum { 620 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, 621 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2 622 }; 623 624 enum { 625 OPAL_P7IOC_NUM_PEST_REGS = 128, 626 OPAL_PHB3_NUM_PEST_REGS = 256 627 }; 628 629 struct OpalIoPhbErrorCommon { 630 __be32 version; 631 __be32 ioType; 632 __be32 len; 633 }; 634 635 struct OpalIoP7IOCPhbErrorData { 636 struct OpalIoPhbErrorCommon common; 637 638 __be32 brdgCtl; 639 640 // P7IOC utl regs 641 __be32 portStatusReg; 642 __be32 rootCmplxStatus; 643 __be32 busAgentStatus; 644 645 // P7IOC cfg regs 646 __be32 deviceStatus; 647 __be32 slotStatus; 648 __be32 linkStatus; 649 __be32 devCmdStatus; 650 __be32 devSecStatus; 651 652 // cfg AER regs 653 __be32 rootErrorStatus; 654 __be32 uncorrErrorStatus; 655 __be32 corrErrorStatus; 656 __be32 tlpHdr1; 657 __be32 tlpHdr2; 658 __be32 tlpHdr3; 659 __be32 tlpHdr4; 660 __be32 sourceId; 661 662 __be32 rsv3; 663 664 // Record data about the call to allocate a buffer. 665 __be64 errorClass; 666 __be64 correlator; 667 668 //P7IOC MMIO Error Regs 669 __be64 p7iocPlssr; // n120 670 __be64 p7iocCsr; // n110 671 __be64 lemFir; // nC00 672 __be64 lemErrorMask; // nC18 673 __be64 lemWOF; // nC40 674 __be64 phbErrorStatus; // nC80 675 __be64 phbFirstErrorStatus; // nC88 676 __be64 phbErrorLog0; // nCC0 677 __be64 phbErrorLog1; // nCC8 678 __be64 mmioErrorStatus; // nD00 679 __be64 mmioFirstErrorStatus; // nD08 680 __be64 mmioErrorLog0; // nD40 681 __be64 mmioErrorLog1; // nD48 682 __be64 dma0ErrorStatus; // nD80 683 __be64 dma0FirstErrorStatus; // nD88 684 __be64 dma0ErrorLog0; // nDC0 685 __be64 dma0ErrorLog1; // nDC8 686 __be64 dma1ErrorStatus; // nE00 687 __be64 dma1FirstErrorStatus; // nE08 688 __be64 dma1ErrorLog0; // nE40 689 __be64 dma1ErrorLog1; // nE48 690 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS]; 691 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS]; 692 }; 693 694 struct OpalIoPhb3ErrorData { 695 struct OpalIoPhbErrorCommon common; 696 697 __be32 brdgCtl; 698 699 /* PHB3 UTL regs */ 700 __be32 portStatusReg; 701 __be32 rootCmplxStatus; 702 __be32 busAgentStatus; 703 704 /* PHB3 cfg regs */ 705 __be32 deviceStatus; 706 __be32 slotStatus; 707 __be32 linkStatus; 708 __be32 devCmdStatus; 709 __be32 devSecStatus; 710 711 /* cfg AER regs */ 712 __be32 rootErrorStatus; 713 __be32 uncorrErrorStatus; 714 __be32 corrErrorStatus; 715 __be32 tlpHdr1; 716 __be32 tlpHdr2; 717 __be32 tlpHdr3; 718 __be32 tlpHdr4; 719 __be32 sourceId; 720 721 __be32 rsv3; 722 723 /* Record data about the call to allocate a buffer */ 724 __be64 errorClass; 725 __be64 correlator; 726 727 __be64 nFir; /* 000 */ 728 __be64 nFirMask; /* 003 */ 729 __be64 nFirWOF; /* 008 */ 730 731 /* PHB3 MMIO Error Regs */ 732 __be64 phbPlssr; /* 120 */ 733 __be64 phbCsr; /* 110 */ 734 __be64 lemFir; /* C00 */ 735 __be64 lemErrorMask; /* C18 */ 736 __be64 lemWOF; /* C40 */ 737 __be64 phbErrorStatus; /* C80 */ 738 __be64 phbFirstErrorStatus; /* C88 */ 739 __be64 phbErrorLog0; /* CC0 */ 740 __be64 phbErrorLog1; /* CC8 */ 741 __be64 mmioErrorStatus; /* D00 */ 742 __be64 mmioFirstErrorStatus; /* D08 */ 743 __be64 mmioErrorLog0; /* D40 */ 744 __be64 mmioErrorLog1; /* D48 */ 745 __be64 dma0ErrorStatus; /* D80 */ 746 __be64 dma0FirstErrorStatus; /* D88 */ 747 __be64 dma0ErrorLog0; /* DC0 */ 748 __be64 dma0ErrorLog1; /* DC8 */ 749 __be64 dma1ErrorStatus; /* E00 */ 750 __be64 dma1FirstErrorStatus; /* E08 */ 751 __be64 dma1ErrorLog0; /* E40 */ 752 __be64 dma1ErrorLog1; /* E48 */ 753 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; 754 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; 755 }; 756 757 enum { 758 OPAL_REINIT_CPUS_HILE_BE = (1 << 0), 759 OPAL_REINIT_CPUS_HILE_LE = (1 << 1), 760 }; 761 762 typedef struct oppanel_line { 763 const char * line; 764 uint64_t line_len; 765 } oppanel_line_t; 766 767 /* /sys/firmware/opal */ 768 extern struct kobject *opal_kobj; 769 770 /* /ibm,opal */ 771 extern struct device_node *opal_node; 772 773 /* API functions */ 774 int64_t opal_invalid_call(void); 775 int64_t opal_console_write(int64_t term_number, __be64 *length, 776 const uint8_t *buffer); 777 int64_t opal_console_read(int64_t term_number, __be64 *length, 778 uint8_t *buffer); 779 int64_t opal_console_write_buffer_space(int64_t term_number, 780 __be64 *length); 781 int64_t opal_rtc_read(__be32 *year_month_day, 782 __be64 *hour_minute_second_millisecond); 783 int64_t opal_rtc_write(uint32_t year_month_day, 784 uint64_t hour_minute_second_millisecond); 785 int64_t opal_cec_power_down(uint64_t request); 786 int64_t opal_cec_reboot(void); 787 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 788 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 789 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask); 790 int64_t opal_poll_events(__be64 *outstanding_event_mask); 791 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr, 792 uint64_t tce_mem_size); 793 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr, 794 uint64_t tce_mem_size); 795 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func, 796 uint64_t offset, uint8_t *data); 797 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func, 798 uint64_t offset, __be16 *data); 799 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func, 800 uint64_t offset, __be32 *data); 801 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func, 802 uint64_t offset, uint8_t data); 803 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func, 804 uint64_t offset, uint16_t data); 805 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func, 806 uint64_t offset, uint32_t data); 807 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); 808 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority); 809 int64_t opal_register_exception_handler(uint64_t opal_exception, 810 uint64_t handler_address, 811 uint64_t glue_cache_line); 812 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, 813 uint8_t *freeze_state, 814 __be16 *pci_error_type, 815 __be64 *phb_status); 816 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, 817 uint64_t eeh_action_token); 818 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number, 819 uint64_t eeh_action_token); 820 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state); 821 822 823 824 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, 825 uint16_t window_num, uint16_t enable); 826 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, 827 uint16_t window_num, 828 uint64_t starting_real_address, 829 uint64_t starting_pci_address, 830 uint64_t size); 831 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, 832 uint16_t window_type, uint16_t window_num, 833 uint16_t segment_num); 834 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr, 835 uint64_t ivt_addr, uint64_t ivt_len, 836 uint64_t reject_array_addr, 837 uint64_t peltv_addr); 838 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func, 839 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare, 840 uint8_t pe_action); 841 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, 842 uint8_t state); 843 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); 844 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, 845 uint32_t state); 846 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, 847 uint8_t *p_bit, uint8_t *q_bit); 848 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, 849 uint8_t p_bit, uint8_t q_bit); 850 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); 851 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, 852 uint32_t xive_num); 853 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, 854 __be32 *interrupt_source_number); 855 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, 856 uint8_t msi_range, __be32 *msi_address, 857 __be32 *message_data); 858 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, 859 uint32_t xive_num, uint8_t msi_range, 860 __be64 *msi_address, __be32 *message_data); 861 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address); 862 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status); 863 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines); 864 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id, 865 uint16_t tce_levels, uint64_t tce_table_addr, 866 uint64_t tce_table_size, uint64_t tce_page_size); 867 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number, 868 uint16_t dma_window_number, uint64_t pci_start_addr, 869 uint64_t pci_mem_size); 870 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state); 871 872 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, 873 uint64_t diag_buffer_len); 874 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, 875 uint64_t diag_buffer_len); 876 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, 877 uint64_t diag_buffer_len); 878 int64_t opal_pci_fence_phb(uint64_t phb_id); 879 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data); 880 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); 881 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); 882 int64_t opal_get_epow_status(__be64 *status); 883 int64_t opal_set_system_attention_led(uint8_t led_action); 884 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe, 885 __be16 *pci_error_type, __be16 *severity); 886 int64_t opal_pci_poll(uint64_t phb_id); 887 int64_t opal_return_cpu(void); 888 int64_t opal_reinit_cpus(uint64_t flags); 889 890 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val); 891 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val); 892 893 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, 894 uint32_t addr, uint32_t data, uint32_t sz); 895 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, 896 uint32_t addr, __be32 *data, uint32_t sz); 897 898 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id); 899 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type); 900 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset); 901 int64_t opal_send_ack_elog(uint64_t log_id); 902 void opal_resend_pending_logs(void); 903 904 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); 905 int64_t opal_manage_flash(uint8_t op); 906 int64_t opal_update_flash(uint64_t blk_list); 907 int64_t opal_dump_init(uint8_t dump_type); 908 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size); 909 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type); 910 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer); 911 int64_t opal_dump_ack(uint32_t dump_id); 912 int64_t opal_dump_resend_notification(void); 913 914 int64_t opal_get_msg(uint64_t buffer, uint64_t size); 915 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token); 916 int64_t opal_sync_host_reboot(void); 917 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer, 918 uint64_t length); 919 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer, 920 uint64_t length); 921 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data); 922 int64_t opal_handle_hmi(void); 923 924 /* Internal functions */ 925 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, 926 int depth, void *data); 927 extern int early_init_dt_scan_recoverable_ranges(unsigned long node, 928 const char *uname, int depth, void *data); 929 930 extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 931 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 932 933 extern void hvc_opal_init_early(void); 934 935 extern int opal_notifier_register(struct notifier_block *nb); 936 extern int opal_notifier_unregister(struct notifier_block *nb); 937 938 extern int opal_message_notifier_register(enum OpalMessageType msg_type, 939 struct notifier_block *nb); 940 extern void opal_notifier_enable(void); 941 extern void opal_notifier_disable(void); 942 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 943 944 extern int __opal_async_get_token(void); 945 extern int opal_async_get_token_interruptible(void); 946 extern int __opal_async_release_token(int token); 947 extern int opal_async_release_token(int token); 948 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg); 949 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data); 950 951 struct rtc_time; 952 extern int opal_set_rtc_time(struct rtc_time *tm); 953 extern void opal_get_rtc_time(struct rtc_time *tm); 954 extern unsigned long opal_get_boot_time(void); 955 extern void opal_nvram_init(void); 956 extern void opal_flash_init(void); 957 extern void opal_flash_term_callback(void); 958 extern int opal_elog_init(void); 959 extern void opal_platform_dump_init(void); 960 extern void opal_sys_param_init(void); 961 extern void opal_msglog_init(void); 962 963 extern int opal_machine_check(struct pt_regs *regs); 964 extern bool opal_mce_check_early_recovery(struct pt_regs *regs); 965 extern int opal_hmi_exception_early(struct pt_regs *regs); 966 extern int opal_handle_hmi_exception(struct pt_regs *regs); 967 968 extern void opal_shutdown(void); 969 extern int opal_resync_timebase(void); 970 971 extern void opal_lpc_init(void); 972 973 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr, 974 unsigned long vmalloc_size); 975 void opal_free_sg_list(struct opal_sg_list *sg); 976 977 #endif /* __ASSEMBLY__ */ 978 979 #endif /* __OPAL_H */ 980