1 /* 2 * OPAL API definitions. 3 * 4 * Copyright 2011-2015 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef __OPAL_API_H 13 #define __OPAL_API_H 14 15 /****** OPAL APIs ******/ 16 17 /* Return codes */ 18 #define OPAL_SUCCESS 0 19 #define OPAL_PARAMETER -1 20 #define OPAL_BUSY -2 21 #define OPAL_PARTIAL -3 22 #define OPAL_CONSTRAINED -4 23 #define OPAL_CLOSED -5 24 #define OPAL_HARDWARE -6 25 #define OPAL_UNSUPPORTED -7 26 #define OPAL_PERMISSION -8 27 #define OPAL_NO_MEM -9 28 #define OPAL_RESOURCE -10 29 #define OPAL_INTERNAL_ERROR -11 30 #define OPAL_BUSY_EVENT -12 31 #define OPAL_HARDWARE_FROZEN -13 32 #define OPAL_WRONG_STATE -14 33 #define OPAL_ASYNC_COMPLETION -15 34 #define OPAL_EMPTY -16 35 #define OPAL_I2C_TIMEOUT -17 36 #define OPAL_I2C_INVALID_CMD -18 37 #define OPAL_I2C_LBUS_PARITY -19 38 #define OPAL_I2C_BKEND_OVERRUN -20 39 #define OPAL_I2C_BKEND_ACCESS -21 40 #define OPAL_I2C_ARBT_LOST -22 41 #define OPAL_I2C_NACK_RCVD -23 42 #define OPAL_I2C_STOP_ERR -24 43 44 /* API Tokens (in r0) */ 45 #define OPAL_INVALID_CALL -1 46 #define OPAL_TEST 0 47 #define OPAL_CONSOLE_WRITE 1 48 #define OPAL_CONSOLE_READ 2 49 #define OPAL_RTC_READ 3 50 #define OPAL_RTC_WRITE 4 51 #define OPAL_CEC_POWER_DOWN 5 52 #define OPAL_CEC_REBOOT 6 53 #define OPAL_READ_NVRAM 7 54 #define OPAL_WRITE_NVRAM 8 55 #define OPAL_HANDLE_INTERRUPT 9 56 #define OPAL_POLL_EVENTS 10 57 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 58 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 59 #define OPAL_PCI_CONFIG_READ_BYTE 13 60 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 61 #define OPAL_PCI_CONFIG_READ_WORD 15 62 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 63 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 64 #define OPAL_PCI_CONFIG_WRITE_WORD 18 65 #define OPAL_SET_XIVE 19 66 #define OPAL_GET_XIVE 20 67 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 68 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 69 #define OPAL_PCI_EEH_FREEZE_STATUS 23 70 #define OPAL_PCI_SHPC 24 71 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 72 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 73 #define OPAL_PCI_PHB_MMIO_ENABLE 27 74 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 75 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 76 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 77 #define OPAL_PCI_SET_PE 31 78 #define OPAL_PCI_SET_PELTV 32 79 #define OPAL_PCI_SET_MVE 33 80 #define OPAL_PCI_SET_MVE_ENABLE 34 81 #define OPAL_PCI_GET_XIVE_REISSUE 35 82 #define OPAL_PCI_SET_XIVE_REISSUE 36 83 #define OPAL_PCI_SET_XIVE_PE 37 84 #define OPAL_GET_XIVE_SOURCE 38 85 #define OPAL_GET_MSI_32 39 86 #define OPAL_GET_MSI_64 40 87 #define OPAL_START_CPU 41 88 #define OPAL_QUERY_CPU_STATUS 42 89 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */ 90 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 91 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 92 #define OPAL_PCI_RESET 49 93 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 94 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 95 #define OPAL_PCI_FENCE_PHB 52 96 #define OPAL_PCI_REINIT 53 97 #define OPAL_PCI_MASK_PE_ERROR 54 98 #define OPAL_SET_SLOT_LED_STATUS 55 99 #define OPAL_GET_EPOW_STATUS 56 100 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 101 #define OPAL_RESERVED1 58 102 #define OPAL_RESERVED2 59 103 #define OPAL_PCI_NEXT_ERROR 60 104 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 105 #define OPAL_PCI_POLL 62 106 #define OPAL_PCI_MSI_EOI 63 107 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 108 #define OPAL_XSCOM_READ 65 109 #define OPAL_XSCOM_WRITE 66 110 #define OPAL_LPC_READ 67 111 #define OPAL_LPC_WRITE 68 112 #define OPAL_RETURN_CPU 69 113 #define OPAL_REINIT_CPUS 70 114 #define OPAL_ELOG_READ 71 115 #define OPAL_ELOG_WRITE 72 116 #define OPAL_ELOG_ACK 73 117 #define OPAL_ELOG_RESEND 74 118 #define OPAL_ELOG_SIZE 75 119 #define OPAL_FLASH_VALIDATE 76 120 #define OPAL_FLASH_MANAGE 77 121 #define OPAL_FLASH_UPDATE 78 122 #define OPAL_RESYNC_TIMEBASE 79 123 #define OPAL_CHECK_TOKEN 80 124 #define OPAL_DUMP_INIT 81 125 #define OPAL_DUMP_INFO 82 126 #define OPAL_DUMP_READ 83 127 #define OPAL_DUMP_ACK 84 128 #define OPAL_GET_MSG 85 129 #define OPAL_CHECK_ASYNC_COMPLETION 86 130 #define OPAL_SYNC_HOST_REBOOT 87 131 #define OPAL_SENSOR_READ 88 132 #define OPAL_GET_PARAM 89 133 #define OPAL_SET_PARAM 90 134 #define OPAL_DUMP_RESEND 91 135 #define OPAL_ELOG_SEND 92 /* Deprecated */ 136 #define OPAL_PCI_SET_PHB_CAPI_MODE 93 137 #define OPAL_DUMP_INFO2 94 138 #define OPAL_WRITE_OPPANEL_ASYNC 95 139 #define OPAL_PCI_ERR_INJECT 96 140 #define OPAL_PCI_EEH_FREEZE_SET 97 141 #define OPAL_HANDLE_HMI 98 142 #define OPAL_CONFIG_CPU_IDLE_STATE 99 143 #define OPAL_SLW_SET_REG 100 144 #define OPAL_REGISTER_DUMP_REGION 101 145 #define OPAL_UNREGISTER_DUMP_REGION 102 146 #define OPAL_WRITE_TPO 103 147 #define OPAL_READ_TPO 104 148 #define OPAL_GET_DPO_STATUS 105 149 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */ 150 #define OPAL_IPMI_SEND 107 151 #define OPAL_IPMI_RECV 108 152 #define OPAL_I2C_REQUEST 109 153 #define OPAL_LAST 109 154 155 /* Device tree flags */ 156 157 /* Flags set in power-mgmt nodes in device tree if 158 * respective idle states are supported in the platform. 159 */ 160 #define OPAL_PM_NAP_ENABLED 0x00010000 161 #define OPAL_PM_SLEEP_ENABLED 0x00020000 162 #define OPAL_PM_WINKLE_ENABLED 0x00040000 163 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */ 164 165 #ifndef __ASSEMBLY__ 166 167 /* Other enums */ 168 enum OpalFreezeState { 169 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 170 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 171 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 172 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 173 OPAL_EEH_STOPPED_RESET = 4, 174 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 175 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 176 }; 177 178 enum OpalEehFreezeActionToken { 179 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 180 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 181 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, 182 183 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, 184 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, 185 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 186 }; 187 188 enum OpalPciStatusToken { 189 OPAL_EEH_NO_ERROR = 0, 190 OPAL_EEH_IOC_ERROR = 1, 191 OPAL_EEH_PHB_ERROR = 2, 192 OPAL_EEH_PE_ERROR = 3, 193 OPAL_EEH_PE_MMIO_ERROR = 4, 194 OPAL_EEH_PE_DMA_ERROR = 5 195 }; 196 197 enum OpalPciErrorSeverity { 198 OPAL_EEH_SEV_NO_ERROR = 0, 199 OPAL_EEH_SEV_IOC_DEAD = 1, 200 OPAL_EEH_SEV_PHB_DEAD = 2, 201 OPAL_EEH_SEV_PHB_FENCED = 3, 202 OPAL_EEH_SEV_PE_ER = 4, 203 OPAL_EEH_SEV_INF = 5 204 }; 205 206 enum OpalErrinjectType { 207 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0, 208 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1, 209 }; 210 211 enum OpalErrinjectFunc { 212 /* IOA bus specific errors */ 213 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0, 214 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1, 215 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2, 216 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3, 217 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4, 218 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5, 219 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6, 220 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7, 221 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8, 222 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9, 223 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10, 224 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11, 225 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12, 226 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13, 227 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14, 228 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15, 229 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16, 230 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17, 231 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18, 232 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19, 233 }; 234 235 enum OpalMmioWindowType { 236 OPAL_M32_WINDOW_TYPE = 1, 237 OPAL_M64_WINDOW_TYPE = 2, 238 OPAL_IO_WINDOW_TYPE = 3 239 }; 240 241 enum OpalExceptionHandler { 242 OPAL_MACHINE_CHECK_HANDLER = 1, 243 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 244 OPAL_SOFTPATCH_HANDLER = 3 245 }; 246 247 enum OpalPendingState { 248 OPAL_EVENT_OPAL_INTERNAL = 0x1, 249 OPAL_EVENT_NVRAM = 0x2, 250 OPAL_EVENT_RTC = 0x4, 251 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 252 OPAL_EVENT_CONSOLE_INPUT = 0x10, 253 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 254 OPAL_EVENT_ERROR_LOG = 0x40, 255 OPAL_EVENT_EPOW = 0x80, 256 OPAL_EVENT_LED_STATUS = 0x100, 257 OPAL_EVENT_PCI_ERROR = 0x200, 258 OPAL_EVENT_DUMP_AVAIL = 0x400, 259 OPAL_EVENT_MSG_PENDING = 0x800, 260 }; 261 262 enum OpalThreadStatus { 263 OPAL_THREAD_INACTIVE = 0x0, 264 OPAL_THREAD_STARTED = 0x1, 265 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 266 }; 267 268 enum OpalPciBusCompare { 269 OpalPciBusAny = 0, /* Any bus number match */ 270 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 271 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 272 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 273 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 274 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 275 OpalPciBusAll = 7, /* Match bus number exactly */ 276 }; 277 278 enum OpalDeviceCompare { 279 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 280 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 281 }; 282 283 enum OpalFuncCompare { 284 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 285 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 286 }; 287 288 enum OpalPeAction { 289 OPAL_UNMAP_PE = 0, 290 OPAL_MAP_PE = 1 291 }; 292 293 enum OpalPeltvAction { 294 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 295 OPAL_ADD_PE_TO_DOMAIN = 1 296 }; 297 298 enum OpalMveEnableAction { 299 OPAL_DISABLE_MVE = 0, 300 OPAL_ENABLE_MVE = 1 301 }; 302 303 enum OpalM64Action { 304 OPAL_DISABLE_M64 = 0, 305 OPAL_ENABLE_M64_SPLIT = 1, 306 OPAL_ENABLE_M64_NON_SPLIT = 2 307 }; 308 309 enum OpalPciResetScope { 310 OPAL_RESET_PHB_COMPLETE = 1, 311 OPAL_RESET_PCI_LINK = 2, 312 OPAL_RESET_PHB_ERROR = 3, 313 OPAL_RESET_PCI_HOT = 4, 314 OPAL_RESET_PCI_FUNDAMENTAL = 5, 315 OPAL_RESET_PCI_IODA_TABLE = 6 316 }; 317 318 enum OpalPciReinitScope { 319 /* 320 * Note: we chose values that do not overlap 321 * OpalPciResetScope as OPAL v2 used the same 322 * enum for both 323 */ 324 OPAL_REINIT_PCI_DEV = 1000 325 }; 326 327 enum OpalPciResetState { 328 OPAL_DEASSERT_RESET = 0, 329 OPAL_ASSERT_RESET = 1 330 }; 331 332 /* 333 * Address cycle types for LPC accesses. These also correspond 334 * to the content of the first cell of the "reg" property for 335 * device nodes on the LPC bus 336 */ 337 enum OpalLPCAddressType { 338 OPAL_LPC_MEM = 0, 339 OPAL_LPC_IO = 1, 340 OPAL_LPC_FW = 2, 341 }; 342 343 enum opal_msg_type { 344 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, 345 * additional params function-specific 346 */ 347 OPAL_MSG_MEM_ERR, 348 OPAL_MSG_EPOW, 349 OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */ 350 OPAL_MSG_HMI_EVT, 351 OPAL_MSG_DPO, 352 OPAL_MSG_TYPE_MAX, 353 }; 354 355 struct opal_msg { 356 __be32 msg_type; 357 __be32 reserved; 358 __be64 params[8]; 359 }; 360 361 /* System parameter permission */ 362 enum OpalSysparamPerm { 363 OPAL_SYSPARAM_READ = 0x1, 364 OPAL_SYSPARAM_WRITE = 0x2, 365 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), 366 }; 367 368 enum { 369 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1, 370 }; 371 372 struct opal_ipmi_msg { 373 uint8_t version; 374 uint8_t netfn; 375 uint8_t cmd; 376 uint8_t data[]; 377 }; 378 379 /* FSP memory errors handling */ 380 enum OpalMemErr_Version { 381 OpalMemErr_V1 = 1, 382 }; 383 384 enum OpalMemErrType { 385 OPAL_MEM_ERR_TYPE_RESILIENCE = 0, 386 OPAL_MEM_ERR_TYPE_DYN_DALLOC, 387 }; 388 389 /* Memory Reilience error type */ 390 enum OpalMemErr_ResilErrType { 391 OPAL_MEM_RESILIENCE_CE = 0, 392 OPAL_MEM_RESILIENCE_UE, 393 OPAL_MEM_RESILIENCE_UE_SCRUB, 394 }; 395 396 /* Dynamic Memory Deallocation type */ 397 enum OpalMemErr_DynErrType { 398 OPAL_MEM_DYNAMIC_DEALLOC = 0, 399 }; 400 401 struct OpalMemoryErrorData { 402 enum OpalMemErr_Version version:8; /* 0x00 */ 403 enum OpalMemErrType type:8; /* 0x01 */ 404 __be16 flags; /* 0x02 */ 405 uint8_t reserved_1[4]; /* 0x04 */ 406 407 union { 408 /* Memory Resilience corrected/uncorrected error info */ 409 struct { 410 enum OpalMemErr_ResilErrType resil_err_type:8; 411 uint8_t reserved_1[7]; 412 __be64 physical_address_start; 413 __be64 physical_address_end; 414 } resilience; 415 /* Dynamic memory deallocation error info */ 416 struct { 417 enum OpalMemErr_DynErrType dyn_err_type:8; 418 uint8_t reserved_1[7]; 419 __be64 physical_address_start; 420 __be64 physical_address_end; 421 } dyn_dealloc; 422 } u; 423 }; 424 425 /* HMI interrupt event */ 426 enum OpalHMI_Version { 427 OpalHMIEvt_V1 = 1, 428 }; 429 430 enum OpalHMI_Severity { 431 OpalHMI_SEV_NO_ERROR = 0, 432 OpalHMI_SEV_WARNING = 1, 433 OpalHMI_SEV_ERROR_SYNC = 2, 434 OpalHMI_SEV_FATAL = 3, 435 }; 436 437 enum OpalHMI_Disposition { 438 OpalHMI_DISPOSITION_RECOVERED = 0, 439 OpalHMI_DISPOSITION_NOT_RECOVERED = 1, 440 }; 441 442 enum OpalHMI_ErrType { 443 OpalHMI_ERROR_MALFUNC_ALERT = 0, 444 OpalHMI_ERROR_PROC_RECOV_DONE, 445 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, 446 OpalHMI_ERROR_PROC_RECOV_MASKED, 447 OpalHMI_ERROR_TFAC, 448 OpalHMI_ERROR_TFMR_PARITY, 449 OpalHMI_ERROR_HA_OVERFLOW_WARN, 450 OpalHMI_ERROR_XSCOM_FAIL, 451 OpalHMI_ERROR_XSCOM_DONE, 452 OpalHMI_ERROR_SCOM_FIR, 453 OpalHMI_ERROR_DEBUG_TRIG_FIR, 454 OpalHMI_ERROR_HYP_RESOURCE, 455 OpalHMI_ERROR_CAPP_RECOVERY, 456 }; 457 458 struct OpalHMIEvent { 459 uint8_t version; /* 0x00 */ 460 uint8_t severity; /* 0x01 */ 461 uint8_t type; /* 0x02 */ 462 uint8_t disposition; /* 0x03 */ 463 uint8_t reserved_1[4]; /* 0x04 */ 464 465 __be64 hmer; 466 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ 467 __be64 tfmr; 468 }; 469 470 enum { 471 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 472 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 473 OPAL_P7IOC_DIAG_TYPE_BI = 2, 474 OPAL_P7IOC_DIAG_TYPE_CI = 3, 475 OPAL_P7IOC_DIAG_TYPE_MISC = 4, 476 OPAL_P7IOC_DIAG_TYPE_I2C = 5, 477 OPAL_P7IOC_DIAG_TYPE_LAST = 6 478 }; 479 480 struct OpalIoP7IOCErrorData { 481 __be16 type; 482 483 /* GEM */ 484 __be64 gemXfir; 485 __be64 gemRfir; 486 __be64 gemRirqfir; 487 __be64 gemMask; 488 __be64 gemRwof; 489 490 /* LEM */ 491 __be64 lemFir; 492 __be64 lemErrMask; 493 __be64 lemAction0; 494 __be64 lemAction1; 495 __be64 lemWof; 496 497 union { 498 struct OpalIoP7IOCRgcErrorData { 499 __be64 rgcStatus; /* 3E1C10 */ 500 __be64 rgcLdcp; /* 3E1C18 */ 501 }rgc; 502 struct OpalIoP7IOCBiErrorData { 503 __be64 biLdcp0; /* 3C0100, 3C0118 */ 504 __be64 biLdcp1; /* 3C0108, 3C0120 */ 505 __be64 biLdcp2; /* 3C0110, 3C0128 */ 506 __be64 biFenceStatus; /* 3C0130, 3C0130 */ 507 508 uint8_t biDownbound; /* BI Downbound or Upbound */ 509 }bi; 510 struct OpalIoP7IOCCiErrorData { 511 __be64 ciPortStatus; /* 3Dn008 */ 512 __be64 ciPortLdcp; /* 3Dn010 */ 513 514 uint8_t ciPort; /* Index of CI port: 0/1 */ 515 }ci; 516 }; 517 }; 518 519 /** 520 * This structure defines the overlay which will be used to store PHB error 521 * data upon request. 522 */ 523 enum { 524 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 525 }; 526 527 enum { 528 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, 529 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2 530 }; 531 532 enum { 533 OPAL_P7IOC_NUM_PEST_REGS = 128, 534 OPAL_PHB3_NUM_PEST_REGS = 256 535 }; 536 537 struct OpalIoPhbErrorCommon { 538 __be32 version; 539 __be32 ioType; 540 __be32 len; 541 }; 542 543 struct OpalIoP7IOCPhbErrorData { 544 struct OpalIoPhbErrorCommon common; 545 546 __be32 brdgCtl; 547 548 // P7IOC utl regs 549 __be32 portStatusReg; 550 __be32 rootCmplxStatus; 551 __be32 busAgentStatus; 552 553 // P7IOC cfg regs 554 __be32 deviceStatus; 555 __be32 slotStatus; 556 __be32 linkStatus; 557 __be32 devCmdStatus; 558 __be32 devSecStatus; 559 560 // cfg AER regs 561 __be32 rootErrorStatus; 562 __be32 uncorrErrorStatus; 563 __be32 corrErrorStatus; 564 __be32 tlpHdr1; 565 __be32 tlpHdr2; 566 __be32 tlpHdr3; 567 __be32 tlpHdr4; 568 __be32 sourceId; 569 570 __be32 rsv3; 571 572 // Record data about the call to allocate a buffer. 573 __be64 errorClass; 574 __be64 correlator; 575 576 //P7IOC MMIO Error Regs 577 __be64 p7iocPlssr; // n120 578 __be64 p7iocCsr; // n110 579 __be64 lemFir; // nC00 580 __be64 lemErrorMask; // nC18 581 __be64 lemWOF; // nC40 582 __be64 phbErrorStatus; // nC80 583 __be64 phbFirstErrorStatus; // nC88 584 __be64 phbErrorLog0; // nCC0 585 __be64 phbErrorLog1; // nCC8 586 __be64 mmioErrorStatus; // nD00 587 __be64 mmioFirstErrorStatus; // nD08 588 __be64 mmioErrorLog0; // nD40 589 __be64 mmioErrorLog1; // nD48 590 __be64 dma0ErrorStatus; // nD80 591 __be64 dma0FirstErrorStatus; // nD88 592 __be64 dma0ErrorLog0; // nDC0 593 __be64 dma0ErrorLog1; // nDC8 594 __be64 dma1ErrorStatus; // nE00 595 __be64 dma1FirstErrorStatus; // nE08 596 __be64 dma1ErrorLog0; // nE40 597 __be64 dma1ErrorLog1; // nE48 598 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS]; 599 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS]; 600 }; 601 602 struct OpalIoPhb3ErrorData { 603 struct OpalIoPhbErrorCommon common; 604 605 __be32 brdgCtl; 606 607 /* PHB3 UTL regs */ 608 __be32 portStatusReg; 609 __be32 rootCmplxStatus; 610 __be32 busAgentStatus; 611 612 /* PHB3 cfg regs */ 613 __be32 deviceStatus; 614 __be32 slotStatus; 615 __be32 linkStatus; 616 __be32 devCmdStatus; 617 __be32 devSecStatus; 618 619 /* cfg AER regs */ 620 __be32 rootErrorStatus; 621 __be32 uncorrErrorStatus; 622 __be32 corrErrorStatus; 623 __be32 tlpHdr1; 624 __be32 tlpHdr2; 625 __be32 tlpHdr3; 626 __be32 tlpHdr4; 627 __be32 sourceId; 628 629 __be32 rsv3; 630 631 /* Record data about the call to allocate a buffer */ 632 __be64 errorClass; 633 __be64 correlator; 634 635 /* PHB3 MMIO Error Regs */ 636 __be64 nFir; /* 000 */ 637 __be64 nFirMask; /* 003 */ 638 __be64 nFirWOF; /* 008 */ 639 __be64 phbPlssr; /* 120 */ 640 __be64 phbCsr; /* 110 */ 641 __be64 lemFir; /* C00 */ 642 __be64 lemErrorMask; /* C18 */ 643 __be64 lemWOF; /* C40 */ 644 __be64 phbErrorStatus; /* C80 */ 645 __be64 phbFirstErrorStatus; /* C88 */ 646 __be64 phbErrorLog0; /* CC0 */ 647 __be64 phbErrorLog1; /* CC8 */ 648 __be64 mmioErrorStatus; /* D00 */ 649 __be64 mmioFirstErrorStatus; /* D08 */ 650 __be64 mmioErrorLog0; /* D40 */ 651 __be64 mmioErrorLog1; /* D48 */ 652 __be64 dma0ErrorStatus; /* D80 */ 653 __be64 dma0FirstErrorStatus; /* D88 */ 654 __be64 dma0ErrorLog0; /* DC0 */ 655 __be64 dma0ErrorLog1; /* DC8 */ 656 __be64 dma1ErrorStatus; /* E00 */ 657 __be64 dma1FirstErrorStatus; /* E08 */ 658 __be64 dma1ErrorLog0; /* E40 */ 659 __be64 dma1ErrorLog1; /* E48 */ 660 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; 661 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; 662 }; 663 664 enum { 665 OPAL_REINIT_CPUS_HILE_BE = (1 << 0), 666 OPAL_REINIT_CPUS_HILE_LE = (1 << 1), 667 }; 668 669 typedef struct oppanel_line { 670 __be64 line; 671 __be64 line_len; 672 } oppanel_line_t; 673 674 /* 675 * SG entries 676 * 677 * WARNING: The current implementation requires each entry 678 * to represent a block that is 4k aligned *and* each block 679 * size except the last one in the list to be as well. 680 */ 681 struct opal_sg_entry { 682 __be64 data; 683 __be64 length; 684 }; 685 686 /* 687 * Candiate image SG list. 688 * 689 * length = VER | length 690 */ 691 struct opal_sg_list { 692 __be64 length; 693 __be64 next; 694 struct opal_sg_entry entry[]; 695 }; 696 697 /* 698 * Dump region ID range usable by the OS 699 */ 700 #define OPAL_DUMP_REGION_HOST_START 0x80 701 #define OPAL_DUMP_REGION_LOG_BUF 0x80 702 #define OPAL_DUMP_REGION_HOST_END 0xFF 703 704 /* CAPI modes for PHB */ 705 enum { 706 OPAL_PHB_CAPI_MODE_PCIE = 0, 707 OPAL_PHB_CAPI_MODE_CAPI = 1, 708 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2, 709 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3, 710 }; 711 712 /* OPAL I2C request */ 713 struct opal_i2c_request { 714 uint8_t type; 715 #define OPAL_I2C_RAW_READ 0 716 #define OPAL_I2C_RAW_WRITE 1 717 #define OPAL_I2C_SM_READ 2 718 #define OPAL_I2C_SM_WRITE 3 719 uint8_t flags; 720 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */ 721 uint8_t subaddr_sz; /* Max 4 */ 722 uint8_t reserved; 723 __be16 addr; /* 7 or 10 bit address */ 724 __be16 reserved2; 725 __be32 subaddr; /* Sub-address if any */ 726 __be32 size; /* Data size */ 727 __be64 buffer_ra; /* Buffer real address */ 728 }; 729 730 #endif /* __ASSEMBLY__ */ 731 732 #endif /* __OPAL_API_H */ 733