1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H 3 #define _ASM_POWERPC_NOHASH_32_PGTABLE_H 4 5 #include <asm-generic/pgtable-nopmd.h> 6 7 #ifndef __ASSEMBLER__ 8 #include <linux/sched.h> 9 #include <linux/threads.h> 10 #include <asm/mmu.h> /* For sub-arch specific PPC_PIN_SIZE */ 11 12 #endif /* __ASSEMBLER__ */ 13 14 #define PTE_INDEX_SIZE PTE_SHIFT 15 #define PMD_INDEX_SIZE 0 16 #define PUD_INDEX_SIZE 0 17 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT) 18 19 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 20 #define PUD_CACHE_INDEX PUD_INDEX_SIZE 21 22 #ifndef __ASSEMBLER__ 23 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) 24 #define PMD_TABLE_SIZE 0 25 #define PUD_TABLE_SIZE 0 26 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 27 28 #define PMD_MASKED_BITS (PTE_TABLE_SIZE - 1) 29 #endif /* __ASSEMBLER__ */ 30 31 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 32 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 33 34 /* 35 * The normal case is that PTEs are 32-bits and we have a 1-page 36 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 37 * 38 * For any >32-bit physical address platform, we can use the following 39 * two level page table layout where the pgdir is 8KB and the MS 13 bits 40 * are an index to the second level table. The combined pgdir/pmd first 41 * level has 2048 entries and the second level has 512 64-bit PTE entries. 42 * -Matt 43 */ 44 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 45 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 46 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 47 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 48 49 /* Bits to mask out from a PGD to get to the PUD page */ 50 #define PGD_MASKED_BITS 0 51 52 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 53 54 55 /* 56 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary 57 * value (for now) on others, from where we can start layout kernel 58 * virtual space that goes below PKMAP and FIXMAP 59 */ 60 61 #define FIXADDR_SIZE 0 62 #ifdef CONFIG_KASAN 63 #include <asm/kasan.h> 64 #define FIXADDR_TOP (KASAN_SHADOW_START - PAGE_SIZE) 65 #else 66 #define FIXADDR_TOP ((unsigned long)(-PAGE_SIZE)) 67 #endif 68 69 /* 70 * ioremap_bot starts at that address. Early ioremaps move down from there, 71 * until mem_init() at which point this becomes the top of the vmalloc 72 * and ioremap space 73 */ 74 #ifdef CONFIG_HIGHMEM 75 #define IOREMAP_TOP PKMAP_BASE 76 #else 77 #define IOREMAP_TOP FIXADDR_START 78 #endif 79 80 /* PPC32 shares vmalloc area with ioremap */ 81 #define IOREMAP_START VMALLOC_START 82 #define IOREMAP_END VMALLOC_END 83 84 /* 85 * Just any arbitrary offset to the start of the vmalloc VM area: the 86 * current 16MB value just means that there will be a 64MB "hole" after the 87 * physical memory until the kernel virtual memory starts. That means that 88 * any out-of-bounds memory accesses will hopefully be caught. 89 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 90 * area for the same reason. ;) 91 * 92 * We no longer map larger than phys RAM with the BATs so we don't have 93 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry 94 * about clashes between our early calls to ioremap() that start growing down 95 * from IOREMAP_TOP being run into the VM area allocations (growing upwards 96 * from VMALLOC_START). For this reason we have ioremap_bot to check when 97 * we actually run into our mappings setup in the early boot with the VM 98 * system. This really does become a problem for machines with good amounts 99 * of RAM. -- Cort 100 */ 101 #define VMALLOC_OFFSET (0x1000000) /* 16M */ 102 #ifdef PPC_PIN_SIZE 103 #define VMALLOC_START (((ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 104 #else 105 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 106 #endif 107 108 #ifdef CONFIG_KASAN_VMALLOC 109 #define VMALLOC_END ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT) 110 #else 111 #define VMALLOC_END ioremap_bot 112 #endif 113 114 /* 115 * Bits in a linux-style PTE. These match the bits in the 116 * (hardware-defined) PowerPC PTE as closely as possible. 117 */ 118 119 #if defined(CONFIG_44x) 120 #include <asm/nohash/32/pte-44x.h> 121 #elif defined(CONFIG_PPC_85xx) 122 #include <asm/nohash/pte-e500.h> 123 #elif defined(CONFIG_PPC_8xx) 124 #include <asm/nohash/32/pte-8xx.h> 125 #endif 126 127 /* 128 * Location of the PFN in the PTE. Most 32-bit platforms use the same 129 * as _PAGE_SHIFT here (ie, naturally aligned). 130 * Platform who don't just pre-define the value so we don't override it here. 131 */ 132 #ifndef PTE_RPN_SHIFT 133 #define PTE_RPN_SHIFT (PAGE_SHIFT) 134 #endif 135 136 /* 137 * The mask covered by the RPN must be a ULL on 32-bit platforms with 138 * 64-bit PTEs. 139 */ 140 #ifdef CONFIG_PTE_64BIT 141 #define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1)) 142 #define MAX_POSSIBLE_PHYSMEM_BITS 36 143 #else 144 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1)) 145 #define MAX_POSSIBLE_PHYSMEM_BITS 32 146 #endif 147 148 #ifndef __ASSEMBLER__ 149 150 #define pmd_none(pmd) (!pmd_val(pmd)) 151 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) 152 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) 153 static inline void pmd_clear(pmd_t *pmdp) 154 { 155 *pmdp = __pmd(0); 156 } 157 158 /* 159 * Note that on Book E processors, the pmd contains the kernel virtual 160 * (lowmem) address of the pte page. The physical address is less useful 161 * because everything runs with translation enabled (even the TLB miss 162 * handler). On everything else the pmd contains the physical address 163 * of the pte page. -- paulus 164 */ 165 #ifndef CONFIG_BOOKE 166 #define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT) 167 #else 168 #define pmd_page_vaddr(pmd) \ 169 ((const void *)((unsigned long)pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1))) 170 #define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT) 171 #endif 172 173 #define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd)) 174 175 /* 176 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 177 * are !pte_none() && !pte_present(). 178 * 179 * Format of swap PTEs (32bit PTEs): 180 * 181 * 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 182 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 183 * <------------------ offset -------------------> < type -> E 0 0 184 * 185 * E is the exclusive marker that is not stored in swap entries. 186 * 187 * For 64bit PTEs, the offset is extended by 32bit. 188 */ 189 #define __swp_type(entry) ((entry).val & 0x1f) 190 #define __swp_offset(entry) ((entry).val >> 5) 191 #define __swp_entry(type, offset) ((swp_entry_t) { ((type) & 0x1f) | ((offset) << 5) }) 192 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) 193 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) 194 195 /* We borrow LSB 2 to store the exclusive marker in swap PTEs. */ 196 #define _PAGE_SWP_EXCLUSIVE 0x000004 197 198 #endif /* !__ASSEMBLER__ */ 199 200 #endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */ 201