1 #ifndef _ASM_POWERPC_MMU_H_ 2 #define _ASM_POWERPC_MMU_H_ 3 #ifdef __KERNEL__ 4 5 #include <asm/asm-compat.h> 6 #include <asm/feature-fixups.h> 7 8 /* 9 * MMU features bit definitions 10 */ 11 12 /* 13 * First half is MMU families 14 */ 15 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 16 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 17 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 18 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 19 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 20 #define MMU_FTR_TYPE_3E ASM_CONST(0x00000020) 21 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000040) 22 23 /* 24 * This is individual features 25 */ 26 27 /* Enable use of high BAT registers */ 28 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 29 30 /* Enable >32-bit physical addresses on 32-bit processor, only used 31 * by CONFIG_6xx currently as BookE supports that from day 1 32 */ 33 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 34 35 /* Enable use of broadcast TLB invalidations. We don't always set it 36 * on processors that support it due to other constraints with the 37 * use of such invalidations 38 */ 39 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 40 41 /* Enable use of tlbilx invalidate instructions. 42 */ 43 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 44 45 /* This indicates that the processor cannot handle multiple outstanding 46 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 47 * around such invalidate forms. 48 */ 49 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 50 51 /* This indicates that the processor doesn't handle way selection 52 * properly and needs SW to track and update the LRU state. This 53 * is specific to an errata on e300c2/c3/c4 class parts 54 */ 55 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 56 57 /* This indicates that the processor uses the ISA 2.06 server tlbie 58 * mnemonics 59 */ 60 #define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000) 61 62 /* Enable use of TLB reservation. Processor should support tlbsrx. 63 * instruction and MAS0[WQ]. 64 */ 65 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) 66 67 /* Use paired MAS registers (MAS7||MAS3, etc.) 68 */ 69 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 70 71 #ifndef __ASSEMBLY__ 72 #include <asm/cputable.h> 73 74 static inline int mmu_has_feature(unsigned long feature) 75 { 76 return (cur_cpu_spec->mmu_features & feature); 77 } 78 79 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 80 81 /* MMU initialization (64-bit only fo now) */ 82 extern void early_init_mmu(void); 83 extern void early_init_mmu_secondary(void); 84 85 #endif /* !__ASSEMBLY__ */ 86 87 /* The kernel use the constants below to index in the page sizes array. 88 * The use of fixed constants for this purpose is better for performances 89 * of the low level hash refill handlers. 90 * 91 * A non supported page size has a "shift" field set to 0 92 * 93 * Any new page size being implemented can get a new entry in here. Whether 94 * the kernel will use it or not is a different matter though. The actual page 95 * size used by hugetlbfs is not defined here and may be made variable 96 * 97 * Note: This array ended up being a false good idea as it's growing to the 98 * point where I wonder if we should replace it with something different, 99 * to think about, feedback welcome. --BenH. 100 */ 101 102 /* There are #define as they have to be used in assembly 103 * 104 * WARNING: If you change this list, make sure to update the array of 105 * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will 106 * happen 107 */ 108 #define MMU_PAGE_4K 0 109 #define MMU_PAGE_16K 1 110 #define MMU_PAGE_64K 2 111 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 112 #define MMU_PAGE_256K 4 113 #define MMU_PAGE_1M 5 114 #define MMU_PAGE_8M 6 115 #define MMU_PAGE_16M 7 116 #define MMU_PAGE_256M 8 117 #define MMU_PAGE_1G 9 118 #define MMU_PAGE_16G 10 119 #define MMU_PAGE_64G 11 120 #define MMU_PAGE_COUNT 12 121 122 123 #if defined(CONFIG_PPC_STD_MMU_64) 124 /* 64-bit classic hash table MMU */ 125 # include <asm/mmu-hash64.h> 126 #elif defined(CONFIG_PPC_STD_MMU_32) 127 /* 32-bit classic hash table MMU */ 128 # include <asm/mmu-hash32.h> 129 #elif defined(CONFIG_40x) 130 /* 40x-style software loaded TLB */ 131 # include <asm/mmu-40x.h> 132 #elif defined(CONFIG_44x) 133 /* 44x-style software loaded TLB */ 134 # include <asm/mmu-44x.h> 135 #elif defined(CONFIG_PPC_BOOK3E_MMU) 136 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ 137 # include <asm/mmu-book3e.h> 138 #elif defined (CONFIG_PPC_8xx) 139 /* Motorola/Freescale 8xx software loaded TLB */ 140 # include <asm/mmu-8xx.h> 141 #endif 142 143 144 #endif /* __KERNEL__ */ 145 #endif /* _ASM_POWERPC_MMU_H_ */ 146