1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_MMU_H_ 3 #define _ASM_POWERPC_MMU_H_ 4 #ifdef __KERNEL__ 5 6 #include <linux/types.h> 7 8 #include <asm/asm-const.h> 9 10 /* 11 * MMU features bit definitions 12 */ 13 14 /* 15 * MMU families 16 */ 17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 19 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 20 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 21 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) 22 23 /* Radix page table supported and enabled */ 24 #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040) 25 26 /* 27 * Individual features below. 28 */ 29 30 /* 31 * Supports KUAP feature 32 * key 0 controlling userspace addresses on radix 33 * Key 3 on hash 34 */ 35 #define MMU_FTR_KUAP ASM_CONST(0x00000200) 36 37 /* 38 * Supports KUEP feature 39 * key 0 controlling userspace addresses on radix 40 * Key 3 on hash 41 */ 42 #define MMU_FTR_BOOK3S_KUEP ASM_CONST(0x00000400) 43 44 /* 45 * Support for memory protection keys. 46 */ 47 #define MMU_FTR_PKEY ASM_CONST(0x00000800) 48 49 /* Guest Translation Shootdown Enable */ 50 #define MMU_FTR_GTSE ASM_CONST(0x00001000) 51 52 /* 53 * Support for 68 bit VA space. We added that from ISA 2.05 54 */ 55 #define MMU_FTR_68_BIT_VA ASM_CONST(0x00002000) 56 /* 57 * Kernel read only support. 58 * We added the ppp value 0b110 in ISA 2.04. 59 */ 60 #define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000) 61 62 /* 63 * We need to clear top 16bits of va (from the remaining 64 bits )in 64 * tlbie* instructions 65 */ 66 #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000) 67 68 /* Enable use of high BAT registers */ 69 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 70 71 /* Enable >32-bit physical addresses on 32-bit processor, only used 72 * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1 73 */ 74 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 75 76 /* Enable use of broadcast TLB invalidations. We don't always set it 77 * on processors that support it due to other constraints with the 78 * use of such invalidations 79 */ 80 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 81 82 /* Enable use of tlbilx invalidate instructions. 83 */ 84 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 85 86 /* This indicates that the processor cannot handle multiple outstanding 87 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 88 * around such invalidate forms. 89 */ 90 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 91 92 /* This indicates that the processor doesn't handle way selection 93 * properly and needs SW to track and update the LRU state. This 94 * is specific to an errata on e300c2/c3/c4 class parts 95 */ 96 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 97 98 /* Doesn't support the B bit (1T segment) in SLBIE 99 */ 100 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000) 101 102 /* Support 16M large pages 103 */ 104 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) 105 106 /* Supports TLBIEL variant 107 */ 108 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) 109 110 /* Supports tlbies w/o locking 111 */ 112 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) 113 114 /* Large pages can be marked CI 115 */ 116 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) 117 118 /* 1T segments available 119 */ 120 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) 121 122 // NX paste RMA reject in DSI 123 #define MMU_FTR_NX_DSI ASM_CONST(0x80000000) 124 125 /* MMU feature bit sets for various CPUs */ 126 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 (MMU_FTR_HPTE_TABLE | MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) 127 #define MMU_FTRS_POWER MMU_FTRS_DEFAULT_HPTE_ARCH_V2 128 #define MMU_FTRS_PPC970 MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA 129 #define MMU_FTRS_POWER5 MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE 130 #define MMU_FTRS_POWER6 MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA 131 #define MMU_FTRS_POWER7 MMU_FTRS_POWER6 132 #define MMU_FTRS_POWER8 MMU_FTRS_POWER6 133 #define MMU_FTRS_POWER9 MMU_FTRS_POWER6 134 #define MMU_FTRS_POWER10 MMU_FTRS_POWER6 135 #define MMU_FTRS_POWER11 MMU_FTRS_POWER6 136 #define MMU_FTRS_POWER12 MMU_FTRS_POWER6 137 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 138 MMU_FTR_CI_LARGE_PAGE 139 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 140 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B 141 #ifndef __ASSEMBLER__ 142 #include <linux/bug.h> 143 #include <asm/cputable.h> 144 #include <asm/page.h> 145 146 typedef pte_t *pgtable_t; 147 148 enum { 149 MMU_FTRS_POSSIBLE = 150 #if defined(CONFIG_PPC_BOOK3S_604) 151 MMU_FTR_HPTE_TABLE | 152 #endif 153 #ifdef CONFIG_PPC_8xx 154 MMU_FTR_TYPE_8xx | 155 #endif 156 #ifdef CONFIG_PPC_47x 157 MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL | 158 #elif defined(CONFIG_44x) 159 MMU_FTR_TYPE_44x | 160 #endif 161 #ifdef CONFIG_PPC_E500 162 MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX | 163 #endif 164 #ifdef CONFIG_PPC_BOOK3S_32 165 MMU_FTR_USE_HIGH_BATS | 166 #endif 167 #ifdef CONFIG_PPC_83xx 168 MMU_FTR_NEED_DTLB_SW_LRU | 169 #endif 170 #ifdef CONFIG_PPC_BOOK3S_64 171 MMU_FTR_KERNEL_RO | 172 #ifdef CONFIG_PPC_64S_HASH_MMU 173 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL | 174 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE | 175 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA | 176 MMU_FTR_68_BIT_VA | MMU_FTR_HPTE_TABLE | 177 #endif 178 #ifdef CONFIG_PPC_RADIX_MMU 179 MMU_FTR_TYPE_RADIX | 180 MMU_FTR_GTSE | MMU_FTR_NX_DSI | 181 #endif /* CONFIG_PPC_RADIX_MMU */ 182 #endif 183 #ifdef CONFIG_PPC_KUAP 184 MMU_FTR_KUAP | 185 #endif /* CONFIG_PPC_KUAP */ 186 #ifdef CONFIG_PPC_MEM_KEYS 187 MMU_FTR_PKEY | 188 #endif 189 #ifdef CONFIG_PPC_KUEP 190 MMU_FTR_BOOK3S_KUEP | 191 #endif /* CONFIG_PPC_KUAP */ 192 193 0, 194 }; 195 196 #if defined(CONFIG_PPC_BOOK3S_604) && !defined(CONFIG_PPC_BOOK3S_603) 197 #define MMU_FTRS_ALWAYS MMU_FTR_HPTE_TABLE 198 #endif 199 #ifdef CONFIG_PPC_8xx 200 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_8xx 201 #endif 202 #ifdef CONFIG_PPC_47x 203 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_47x 204 #elif defined(CONFIG_44x) 205 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_44x 206 #endif 207 #ifdef CONFIG_PPC_E500 208 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_FSL_E 209 #endif 210 211 /* BOOK3S_64 options */ 212 #if defined(CONFIG_PPC_RADIX_MMU) && !defined(CONFIG_PPC_64S_HASH_MMU) 213 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_RADIX 214 #elif !defined(CONFIG_PPC_RADIX_MMU) && defined(CONFIG_PPC_64S_HASH_MMU) 215 #define MMU_FTRS_ALWAYS MMU_FTR_HPTE_TABLE 216 #endif 217 218 #ifndef MMU_FTRS_ALWAYS 219 #define MMU_FTRS_ALWAYS 0 220 #endif 221 222 static __always_inline bool early_mmu_has_feature(unsigned long feature) 223 { 224 if (MMU_FTRS_ALWAYS & feature) 225 return true; 226 227 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); 228 } 229 230 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 231 #include <linux/jump_label.h> 232 233 #define NUM_MMU_FTR_KEYS 32 234 235 extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS]; 236 237 extern void mmu_feature_keys_init(void); 238 239 static __always_inline bool mmu_has_feature(unsigned long feature) 240 { 241 int i; 242 243 BUILD_BUG_ON(!__builtin_constant_p(feature)); 244 BUILD_BUG_ON(__builtin_popcountl(feature) > 1); 245 246 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG 247 if (!static_key_feature_checks_initialized) { 248 printk("Warning! mmu_has_feature() used prior to jump label init!\n"); 249 dump_stack(); 250 return early_mmu_has_feature(feature); 251 } 252 #endif 253 254 if (MMU_FTRS_ALWAYS & feature) 255 return true; 256 257 if (!(MMU_FTRS_POSSIBLE & feature)) 258 return false; 259 260 i = __builtin_ctzl(feature); 261 return static_branch_likely(&mmu_feature_keys[i]); 262 } 263 264 static inline void mmu_clear_feature(unsigned long feature) 265 { 266 int i; 267 268 i = __builtin_ctzl(feature); 269 cur_cpu_spec->mmu_features &= ~feature; 270 static_branch_disable(&mmu_feature_keys[i]); 271 } 272 #else 273 274 static inline void mmu_feature_keys_init(void) 275 { 276 277 } 278 279 static __always_inline bool mmu_has_feature(unsigned long feature) 280 { 281 return early_mmu_has_feature(feature); 282 } 283 284 static inline void mmu_clear_feature(unsigned long feature) 285 { 286 cur_cpu_spec->mmu_features &= ~feature; 287 } 288 #endif /* CONFIG_JUMP_LABEL */ 289 290 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 291 292 #ifdef CONFIG_PPC64 293 /* This is our real memory area size on ppc64 server, on embedded, we 294 * make it match the size our of bolted TLB area 295 */ 296 extern u64 ppc64_rma_size; 297 298 /* Cleanup function used by kexec */ 299 extern void mmu_cleanup_all(void); 300 extern void radix__mmu_cleanup_all(void); 301 302 /* Functions for creating and updating partition table on POWER9 */ 303 extern void mmu_partition_table_init(void); 304 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, 305 unsigned long dw1, bool flush); 306 #endif /* CONFIG_PPC64 */ 307 308 struct mm_struct; 309 #ifdef CONFIG_DEBUG_VM 310 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); 311 #else /* CONFIG_DEBUG_VM */ 312 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 313 { 314 } 315 #endif /* !CONFIG_DEBUG_VM */ 316 317 static __always_inline bool radix_enabled(void) 318 { 319 return mmu_has_feature(MMU_FTR_TYPE_RADIX); 320 } 321 322 static __always_inline bool early_radix_enabled(void) 323 { 324 return early_mmu_has_feature(MMU_FTR_TYPE_RADIX); 325 } 326 327 static inline bool strict_kernel_rwx_enabled(void) 328 { 329 return IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) && rodata_enabled; 330 } 331 332 static inline bool strict_module_rwx_enabled(void) 333 { 334 return IS_ENABLED(CONFIG_STRICT_MODULE_RWX) && strict_kernel_rwx_enabled(); 335 } 336 #endif /* !__ASSEMBLER__ */ 337 338 /* The kernel use the constants below to index in the page sizes array. 339 * The use of fixed constants for this purpose is better for performances 340 * of the low level hash refill handlers. 341 * 342 * A non supported page size has a "shift" field set to 0 343 * 344 * Any new page size being implemented can get a new entry in here. Whether 345 * the kernel will use it or not is a different matter though. The actual page 346 * size used by hugetlbfs is not defined here and may be made variable 347 * 348 * Note: This array ended up being a false good idea as it's growing to the 349 * point where I wonder if we should replace it with something different, 350 * to think about, feedback welcome. --BenH. 351 */ 352 353 /* These are #defines as they have to be used in assembly */ 354 #define MMU_PAGE_4K 0 355 #define MMU_PAGE_16K 1 356 #define MMU_PAGE_64K 2 357 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 358 #define MMU_PAGE_256K 4 359 #define MMU_PAGE_512K 5 360 #define MMU_PAGE_1M 6 361 #define MMU_PAGE_2M 7 362 #define MMU_PAGE_4M 8 363 #define MMU_PAGE_8M 9 364 #define MMU_PAGE_16M 10 365 #define MMU_PAGE_64M 11 366 #define MMU_PAGE_256M 12 367 #define MMU_PAGE_1G 13 368 #define MMU_PAGE_16G 14 369 #define MMU_PAGE_64G 15 370 371 /* 372 * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 373 * Also we need to change he type of mm_context.low/high_slices_psize. 374 */ 375 #define MMU_PAGE_COUNT 16 376 377 #ifdef CONFIG_PPC_BOOK3S_64 378 #include <asm/book3s/64/mmu.h> 379 #else /* CONFIG_PPC_BOOK3S_64 */ 380 381 #ifndef __ASSEMBLER__ 382 /* MMU initialization */ 383 extern void early_init_mmu(void); 384 extern void early_init_mmu_secondary(void); 385 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, 386 phys_addr_t first_memblock_size); 387 static inline void mmu_early_init_devtree(void) { } 388 389 static inline void pkey_early_init_devtree(void) {} 390 391 extern void *abatron_pteptrs[2]; 392 #endif /* __ASSEMBLER__ */ 393 #endif 394 395 #if defined(CONFIG_PPC_BOOK3S_32) 396 /* 32-bit classic hash table MMU */ 397 #include <asm/book3s/32/mmu-hash.h> 398 #elif defined(CONFIG_PPC_MMU_NOHASH) 399 #include <asm/nohash/mmu.h> 400 #endif 401 402 #endif /* __KERNEL__ */ 403 #endif /* _ASM_POWERPC_MMU_H_ */ 404