1 #ifndef _ASM_POWERPC_MMU_H_ 2 #define _ASM_POWERPC_MMU_H_ 3 #ifdef __KERNEL__ 4 5 #include <linux/types.h> 6 7 #include <asm/asm-compat.h> 8 #include <asm/feature-fixups.h> 9 10 /* 11 * MMU features bit definitions 12 */ 13 14 /* 15 * MMU families 16 */ 17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 22 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) 23 24 /* Radix page table supported and enabled */ 25 #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040) 26 27 /* 28 * Individual features below. 29 */ 30 31 /* 32 * Kernel read only support. 33 * We added the ppp value 0b110 in ISA 2.04. 34 */ 35 #define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000) 36 37 /* 38 * We need to clear top 16bits of va (from the remaining 64 bits )in 39 * tlbie* instructions 40 */ 41 #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000) 42 43 /* Enable use of high BAT registers */ 44 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 45 46 /* Enable >32-bit physical addresses on 32-bit processor, only used 47 * by CONFIG_6xx currently as BookE supports that from day 1 48 */ 49 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 50 51 /* Enable use of broadcast TLB invalidations. We don't always set it 52 * on processors that support it due to other constraints with the 53 * use of such invalidations 54 */ 55 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 56 57 /* Enable use of tlbilx invalidate instructions. 58 */ 59 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 60 61 /* This indicates that the processor cannot handle multiple outstanding 62 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 63 * around such invalidate forms. 64 */ 65 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 66 67 /* This indicates that the processor doesn't handle way selection 68 * properly and needs SW to track and update the LRU state. This 69 * is specific to an errata on e300c2/c3/c4 class parts 70 */ 71 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 72 73 /* Enable use of TLB reservation. Processor should support tlbsrx. 74 * instruction and MAS0[WQ]. 75 */ 76 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) 77 78 /* Use paired MAS registers (MAS7||MAS3, etc.) 79 */ 80 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 81 82 /* Doesn't support the B bit (1T segment) in SLBIE 83 */ 84 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000) 85 86 /* Support 16M large pages 87 */ 88 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) 89 90 /* Supports TLBIEL variant 91 */ 92 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) 93 94 /* Supports tlbies w/o locking 95 */ 96 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) 97 98 /* Large pages can be marked CI 99 */ 100 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) 101 102 /* 1T segments available 103 */ 104 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) 105 106 /* MMU feature bit sets for various CPUs */ 107 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \ 108 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2 109 #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2 110 #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA 111 #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 112 #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO 113 #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO 114 #define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO 115 #define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO 116 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 117 MMU_FTR_CI_LARGE_PAGE 118 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 119 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B 120 #ifndef __ASSEMBLY__ 121 #include <linux/bug.h> 122 #include <asm/cputable.h> 123 124 #ifdef CONFIG_PPC_FSL_BOOK3E 125 #include <asm/percpu.h> 126 DECLARE_PER_CPU(int, next_tlbcam_idx); 127 #endif 128 129 enum { 130 MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx | 131 MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E | 132 MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS | 133 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX | 134 MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU | 135 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS | 136 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL | 137 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE | 138 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA | 139 #ifdef CONFIG_PPC_RADIX_MMU 140 MMU_FTR_TYPE_RADIX | 141 #endif 142 0, 143 }; 144 145 static inline bool early_mmu_has_feature(unsigned long feature) 146 { 147 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); 148 } 149 150 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 151 #include <linux/jump_label.h> 152 153 #define NUM_MMU_FTR_KEYS 32 154 155 extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS]; 156 157 extern void mmu_feature_keys_init(void); 158 159 static __always_inline bool mmu_has_feature(unsigned long feature) 160 { 161 int i; 162 163 BUILD_BUG_ON(!__builtin_constant_p(feature)); 164 165 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG 166 if (!static_key_initialized) { 167 printk("Warning! mmu_has_feature() used prior to jump label init!\n"); 168 dump_stack(); 169 return early_mmu_has_feature(feature); 170 } 171 #endif 172 173 if (!(MMU_FTRS_POSSIBLE & feature)) 174 return false; 175 176 i = __builtin_ctzl(feature); 177 return static_branch_likely(&mmu_feature_keys[i]); 178 } 179 180 static inline void mmu_clear_feature(unsigned long feature) 181 { 182 int i; 183 184 i = __builtin_ctzl(feature); 185 cur_cpu_spec->mmu_features &= ~feature; 186 static_branch_disable(&mmu_feature_keys[i]); 187 } 188 #else 189 190 static inline void mmu_feature_keys_init(void) 191 { 192 193 } 194 195 static inline bool mmu_has_feature(unsigned long feature) 196 { 197 return early_mmu_has_feature(feature); 198 } 199 200 static inline void mmu_clear_feature(unsigned long feature) 201 { 202 cur_cpu_spec->mmu_features &= ~feature; 203 } 204 #endif /* CONFIG_JUMP_LABEL */ 205 206 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 207 208 #ifdef CONFIG_PPC64 209 /* This is our real memory area size on ppc64 server, on embedded, we 210 * make it match the size our of bolted TLB area 211 */ 212 extern u64 ppc64_rma_size; 213 214 /* Cleanup function used by kexec */ 215 extern void mmu_cleanup_all(void); 216 extern void radix__mmu_cleanup_all(void); 217 218 /* Functions for creating and updating partition table on POWER9 */ 219 extern void mmu_partition_table_init(void); 220 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, 221 unsigned long dw1); 222 #endif /* CONFIG_PPC64 */ 223 224 struct mm_struct; 225 #ifdef CONFIG_DEBUG_VM 226 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); 227 #else /* CONFIG_DEBUG_VM */ 228 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 229 { 230 } 231 #endif /* !CONFIG_DEBUG_VM */ 232 233 #ifdef CONFIG_PPC_RADIX_MMU 234 static inline bool radix_enabled(void) 235 { 236 return mmu_has_feature(MMU_FTR_TYPE_RADIX); 237 } 238 239 static inline bool early_radix_enabled(void) 240 { 241 return early_mmu_has_feature(MMU_FTR_TYPE_RADIX); 242 } 243 #else 244 static inline bool radix_enabled(void) 245 { 246 return false; 247 } 248 249 static inline bool early_radix_enabled(void) 250 { 251 return false; 252 } 253 #endif 254 255 #endif /* !__ASSEMBLY__ */ 256 257 /* The kernel use the constants below to index in the page sizes array. 258 * The use of fixed constants for this purpose is better for performances 259 * of the low level hash refill handlers. 260 * 261 * A non supported page size has a "shift" field set to 0 262 * 263 * Any new page size being implemented can get a new entry in here. Whether 264 * the kernel will use it or not is a different matter though. The actual page 265 * size used by hugetlbfs is not defined here and may be made variable 266 * 267 * Note: This array ended up being a false good idea as it's growing to the 268 * point where I wonder if we should replace it with something different, 269 * to think about, feedback welcome. --BenH. 270 */ 271 272 /* These are #defines as they have to be used in assembly */ 273 #define MMU_PAGE_4K 0 274 #define MMU_PAGE_16K 1 275 #define MMU_PAGE_64K 2 276 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 277 #define MMU_PAGE_256K 4 278 #define MMU_PAGE_512K 5 279 #define MMU_PAGE_1M 6 280 #define MMU_PAGE_2M 7 281 #define MMU_PAGE_4M 8 282 #define MMU_PAGE_8M 9 283 #define MMU_PAGE_16M 10 284 #define MMU_PAGE_64M 11 285 #define MMU_PAGE_256M 12 286 #define MMU_PAGE_1G 13 287 #define MMU_PAGE_16G 14 288 #define MMU_PAGE_64G 15 289 290 /* N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 */ 291 #define MMU_PAGE_COUNT 16 292 293 #ifdef CONFIG_PPC_BOOK3S_64 294 #include <asm/book3s/64/mmu.h> 295 #else /* CONFIG_PPC_BOOK3S_64 */ 296 297 #ifndef __ASSEMBLY__ 298 /* MMU initialization */ 299 extern void early_init_mmu(void); 300 extern void early_init_mmu_secondary(void); 301 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, 302 phys_addr_t first_memblock_size); 303 static inline void mmu_early_init_devtree(void) { } 304 #endif /* __ASSEMBLY__ */ 305 #endif 306 307 #if defined(CONFIG_PPC_STD_MMU_32) 308 /* 32-bit classic hash table MMU */ 309 #include <asm/book3s/32/mmu-hash.h> 310 #elif defined(CONFIG_40x) 311 /* 40x-style software loaded TLB */ 312 # include <asm/mmu-40x.h> 313 #elif defined(CONFIG_44x) 314 /* 44x-style software loaded TLB */ 315 # include <asm/mmu-44x.h> 316 #elif defined(CONFIG_PPC_BOOK3E_MMU) 317 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ 318 # include <asm/mmu-book3e.h> 319 #elif defined (CONFIG_PPC_8xx) 320 /* Motorola/Freescale 8xx software loaded TLB */ 321 # include <asm/mmu-8xx.h> 322 #endif 323 324 #endif /* __KERNEL__ */ 325 #endif /* _ASM_POWERPC_MMU_H_ */ 326