1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_MMU_H_ 3 #define _ASM_POWERPC_MMU_H_ 4 #ifdef __KERNEL__ 5 6 #include <linux/types.h> 7 8 #include <asm/asm-const.h> 9 10 /* 11 * MMU features bit definitions 12 */ 13 14 /* 15 * MMU families 16 */ 17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 22 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) 23 24 /* Radix page table supported and enabled */ 25 #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040) 26 27 /* 28 * Individual features below. 29 */ 30 31 /* 32 * Support for 68 bit VA space. We added that from ISA 2.05 33 */ 34 #define MMU_FTR_68_BIT_VA ASM_CONST(0x00002000) 35 /* 36 * Kernel read only support. 37 * We added the ppp value 0b110 in ISA 2.04. 38 */ 39 #define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000) 40 41 /* 42 * We need to clear top 16bits of va (from the remaining 64 bits )in 43 * tlbie* instructions 44 */ 45 #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000) 46 47 /* Enable use of high BAT registers */ 48 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 49 50 /* Enable >32-bit physical addresses on 32-bit processor, only used 51 * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1 52 */ 53 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 54 55 /* Enable use of broadcast TLB invalidations. We don't always set it 56 * on processors that support it due to other constraints with the 57 * use of such invalidations 58 */ 59 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 60 61 /* Enable use of tlbilx invalidate instructions. 62 */ 63 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 64 65 /* This indicates that the processor cannot handle multiple outstanding 66 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 67 * around such invalidate forms. 68 */ 69 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 70 71 /* This indicates that the processor doesn't handle way selection 72 * properly and needs SW to track and update the LRU state. This 73 * is specific to an errata on e300c2/c3/c4 class parts 74 */ 75 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 76 77 /* Enable use of TLB reservation. Processor should support tlbsrx. 78 * instruction and MAS0[WQ]. 79 */ 80 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) 81 82 /* Use paired MAS registers (MAS7||MAS3, etc.) 83 */ 84 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 85 86 /* Doesn't support the B bit (1T segment) in SLBIE 87 */ 88 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000) 89 90 /* Support 16M large pages 91 */ 92 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) 93 94 /* Supports TLBIEL variant 95 */ 96 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) 97 98 /* Supports tlbies w/o locking 99 */ 100 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) 101 102 /* Large pages can be marked CI 103 */ 104 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) 105 106 /* 1T segments available 107 */ 108 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) 109 110 /* 111 * Supports KUAP (key 0 controlling userspace addresses) on radix 112 */ 113 #define MMU_FTR_RADIX_KUAP ASM_CONST(0x80000000) 114 115 /* MMU feature bit sets for various CPUs */ 116 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \ 117 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2 118 #define MMU_FTRS_POWER MMU_FTRS_DEFAULT_HPTE_ARCH_V2 119 #define MMU_FTRS_PPC970 MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA 120 #define MMU_FTRS_POWER5 MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE 121 #define MMU_FTRS_POWER6 MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA 122 #define MMU_FTRS_POWER7 MMU_FTRS_POWER6 123 #define MMU_FTRS_POWER8 MMU_FTRS_POWER6 124 #define MMU_FTRS_POWER9 MMU_FTRS_POWER6 125 #define MMU_FTRS_POWER10 MMU_FTRS_POWER6 126 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 127 MMU_FTR_CI_LARGE_PAGE 128 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 129 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B 130 #ifndef __ASSEMBLY__ 131 #include <linux/bug.h> 132 #include <asm/cputable.h> 133 #include <asm/page.h> 134 135 typedef pte_t *pgtable_t; 136 137 #ifdef CONFIG_PPC_FSL_BOOK3E 138 #include <asm/percpu.h> 139 DECLARE_PER_CPU(int, next_tlbcam_idx); 140 #endif 141 142 enum { 143 MMU_FTRS_POSSIBLE = 144 #ifdef CONFIG_PPC_BOOK3S 145 MMU_FTR_HPTE_TABLE | 146 #endif 147 #ifdef CONFIG_PPC_8xx 148 MMU_FTR_TYPE_8xx | 149 #endif 150 #ifdef CONFIG_40x 151 MMU_FTR_TYPE_40x | 152 #endif 153 #ifdef CONFIG_44x 154 MMU_FTR_TYPE_44x | 155 #endif 156 #if defined(CONFIG_E200) || defined(CONFIG_E500) 157 MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX | 158 #endif 159 #ifdef CONFIG_PPC_47x 160 MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL | 161 #endif 162 #ifdef CONFIG_PPC_BOOK3S_32 163 MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU | 164 #endif 165 #ifdef CONFIG_PPC_BOOK3E_64 166 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS | 167 #endif 168 #ifdef CONFIG_PPC_BOOK3S_64 169 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL | 170 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE | 171 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA | 172 MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA | 173 #endif 174 #ifdef CONFIG_PPC_RADIX_MMU 175 MMU_FTR_TYPE_RADIX | 176 #ifdef CONFIG_PPC_KUAP 177 MMU_FTR_RADIX_KUAP | 178 #endif /* CONFIG_PPC_KUAP */ 179 #endif /* CONFIG_PPC_RADIX_MMU */ 180 0, 181 }; 182 183 static inline bool early_mmu_has_feature(unsigned long feature) 184 { 185 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); 186 } 187 188 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 189 #include <linux/jump_label.h> 190 191 #define NUM_MMU_FTR_KEYS 32 192 193 extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS]; 194 195 extern void mmu_feature_keys_init(void); 196 197 static __always_inline bool mmu_has_feature(unsigned long feature) 198 { 199 int i; 200 201 #ifndef __clang__ /* clang can't cope with this */ 202 BUILD_BUG_ON(!__builtin_constant_p(feature)); 203 #endif 204 205 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG 206 if (!static_key_initialized) { 207 printk("Warning! mmu_has_feature() used prior to jump label init!\n"); 208 dump_stack(); 209 return early_mmu_has_feature(feature); 210 } 211 #endif 212 213 if (!(MMU_FTRS_POSSIBLE & feature)) 214 return false; 215 216 i = __builtin_ctzl(feature); 217 return static_branch_likely(&mmu_feature_keys[i]); 218 } 219 220 static inline void mmu_clear_feature(unsigned long feature) 221 { 222 int i; 223 224 i = __builtin_ctzl(feature); 225 cur_cpu_spec->mmu_features &= ~feature; 226 static_branch_disable(&mmu_feature_keys[i]); 227 } 228 #else 229 230 static inline void mmu_feature_keys_init(void) 231 { 232 233 } 234 235 static inline bool mmu_has_feature(unsigned long feature) 236 { 237 return early_mmu_has_feature(feature); 238 } 239 240 static inline void mmu_clear_feature(unsigned long feature) 241 { 242 cur_cpu_spec->mmu_features &= ~feature; 243 } 244 #endif /* CONFIG_JUMP_LABEL */ 245 246 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 247 248 #ifdef CONFIG_PPC64 249 /* This is our real memory area size on ppc64 server, on embedded, we 250 * make it match the size our of bolted TLB area 251 */ 252 extern u64 ppc64_rma_size; 253 254 /* Cleanup function used by kexec */ 255 extern void mmu_cleanup_all(void); 256 extern void radix__mmu_cleanup_all(void); 257 258 /* Functions for creating and updating partition table on POWER9 */ 259 extern void mmu_partition_table_init(void); 260 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, 261 unsigned long dw1, bool flush); 262 #endif /* CONFIG_PPC64 */ 263 264 struct mm_struct; 265 #ifdef CONFIG_DEBUG_VM 266 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); 267 #else /* CONFIG_DEBUG_VM */ 268 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 269 { 270 } 271 #endif /* !CONFIG_DEBUG_VM */ 272 273 #ifdef CONFIG_PPC_RADIX_MMU 274 static inline bool radix_enabled(void) 275 { 276 return mmu_has_feature(MMU_FTR_TYPE_RADIX); 277 } 278 279 static inline bool early_radix_enabled(void) 280 { 281 return early_mmu_has_feature(MMU_FTR_TYPE_RADIX); 282 } 283 #else 284 static inline bool radix_enabled(void) 285 { 286 return false; 287 } 288 289 static inline bool early_radix_enabled(void) 290 { 291 return false; 292 } 293 #endif 294 295 #ifdef CONFIG_STRICT_KERNEL_RWX 296 static inline bool strict_kernel_rwx_enabled(void) 297 { 298 return rodata_enabled; 299 } 300 #else 301 static inline bool strict_kernel_rwx_enabled(void) 302 { 303 return false; 304 } 305 #endif 306 #endif /* !__ASSEMBLY__ */ 307 308 /* The kernel use the constants below to index in the page sizes array. 309 * The use of fixed constants for this purpose is better for performances 310 * of the low level hash refill handlers. 311 * 312 * A non supported page size has a "shift" field set to 0 313 * 314 * Any new page size being implemented can get a new entry in here. Whether 315 * the kernel will use it or not is a different matter though. The actual page 316 * size used by hugetlbfs is not defined here and may be made variable 317 * 318 * Note: This array ended up being a false good idea as it's growing to the 319 * point where I wonder if we should replace it with something different, 320 * to think about, feedback welcome. --BenH. 321 */ 322 323 /* These are #defines as they have to be used in assembly */ 324 #define MMU_PAGE_4K 0 325 #define MMU_PAGE_16K 1 326 #define MMU_PAGE_64K 2 327 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 328 #define MMU_PAGE_256K 4 329 #define MMU_PAGE_512K 5 330 #define MMU_PAGE_1M 6 331 #define MMU_PAGE_2M 7 332 #define MMU_PAGE_4M 8 333 #define MMU_PAGE_8M 9 334 #define MMU_PAGE_16M 10 335 #define MMU_PAGE_64M 11 336 #define MMU_PAGE_256M 12 337 #define MMU_PAGE_1G 13 338 #define MMU_PAGE_16G 14 339 #define MMU_PAGE_64G 15 340 341 /* 342 * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 343 * Also we need to change he type of mm_context.low/high_slices_psize. 344 */ 345 #define MMU_PAGE_COUNT 16 346 347 #ifdef CONFIG_PPC_BOOK3S_64 348 #include <asm/book3s/64/mmu.h> 349 #else /* CONFIG_PPC_BOOK3S_64 */ 350 351 #ifndef __ASSEMBLY__ 352 /* MMU initialization */ 353 extern void early_init_mmu(void); 354 extern void early_init_mmu_secondary(void); 355 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, 356 phys_addr_t first_memblock_size); 357 static inline void mmu_early_init_devtree(void) { } 358 359 extern void *abatron_pteptrs[2]; 360 #endif /* __ASSEMBLY__ */ 361 #endif 362 363 #if defined(CONFIG_PPC_BOOK3S_32) 364 /* 32-bit classic hash table MMU */ 365 #include <asm/book3s/32/mmu-hash.h> 366 #elif defined(CONFIG_PPC_MMU_NOHASH) 367 #include <asm/nohash/mmu.h> 368 #endif 369 370 #endif /* __KERNEL__ */ 371 #endif /* _ASM_POWERPC_MMU_H_ */ 372