1e22a2274SMahesh Salgaonkar /* 2e22a2274SMahesh Salgaonkar * Machine check exception header file. 3e22a2274SMahesh Salgaonkar * 4e22a2274SMahesh Salgaonkar * This program is free software; you can redistribute it and/or modify 5e22a2274SMahesh Salgaonkar * it under the terms of the GNU General Public License as published by 6e22a2274SMahesh Salgaonkar * the Free Software Foundation; either version 2 of the License, or 7e22a2274SMahesh Salgaonkar * (at your option) any later version. 8e22a2274SMahesh Salgaonkar * 9e22a2274SMahesh Salgaonkar * This program is distributed in the hope that it will be useful, 10e22a2274SMahesh Salgaonkar * but WITHOUT ANY WARRANTY; without even the implied warranty of 11e22a2274SMahesh Salgaonkar * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12e22a2274SMahesh Salgaonkar * GNU General Public License for more details. 13e22a2274SMahesh Salgaonkar * 14e22a2274SMahesh Salgaonkar * You should have received a copy of the GNU General Public License 15e22a2274SMahesh Salgaonkar * along with this program; if not, write to the Free Software 16e22a2274SMahesh Salgaonkar * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17e22a2274SMahesh Salgaonkar * 18e22a2274SMahesh Salgaonkar * Copyright 2013 IBM Corporation 19e22a2274SMahesh Salgaonkar * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> 20e22a2274SMahesh Salgaonkar */ 21e22a2274SMahesh Salgaonkar 22e22a2274SMahesh Salgaonkar #ifndef __ASM_PPC64_MCE_H__ 23e22a2274SMahesh Salgaonkar #define __ASM_PPC64_MCE_H__ 24e22a2274SMahesh Salgaonkar 25e22a2274SMahesh Salgaonkar #include <linux/bitops.h> 26e22a2274SMahesh Salgaonkar 27e22a2274SMahesh Salgaonkar /* 28e22a2274SMahesh Salgaonkar * Machine Check bits on power7 and power8 29e22a2274SMahesh Salgaonkar */ 30e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42)) /* P8 too */ 31e22a2274SMahesh Salgaonkar 32e22a2274SMahesh Salgaonkar /* SRR1 bits for machine check (On Power7 and Power8) */ 33e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_IFETCH(srr1) ((srr1) & PPC_BITMASK(43, 45)) /* P8 too */ 34e22a2274SMahesh Salgaonkar 35e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_IFETCH_UE (0x1 << PPC_BITLSHIFT(45)) /* P8 too */ 36e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_IFETCH_SLB_PARITY (0x2 << PPC_BITLSHIFT(45)) /* P8 too */ 37e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_IFETCH_SLB_MULTIHIT (0x3 << PPC_BITLSHIFT(45)) /* P8 too */ 38e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_IFETCH_SLB_BOTH (0x4 << PPC_BITLSHIFT(45)) 39e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_IFETCH_TLB_MULTIHIT (0x5 << PPC_BITLSHIFT(45)) /* P8 too */ 40e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_IFETCH_UE_TLB_RELOAD (0x6 << PPC_BITLSHIFT(45)) /* P8 too */ 41e22a2274SMahesh Salgaonkar #define P7_SRR1_MC_IFETCH_UE_IFU_INTERNAL (0x7 << PPC_BITLSHIFT(45)) 42e22a2274SMahesh Salgaonkar 43e22a2274SMahesh Salgaonkar /* SRR1 bits for machine check (On Power8) */ 44e22a2274SMahesh Salgaonkar #define P8_SRR1_MC_IFETCH_ERAT_MULTIHIT (0x4 << PPC_BITLSHIFT(45)) 45e22a2274SMahesh Salgaonkar 46e22a2274SMahesh Salgaonkar /* DSISR bits for machine check (On Power7 and Power8) */ 47e22a2274SMahesh Salgaonkar #define P7_DSISR_MC_UE (PPC_BIT(48)) /* P8 too */ 48e22a2274SMahesh Salgaonkar #define P7_DSISR_MC_UE_TABLEWALK (PPC_BIT(49)) /* P8 too */ 49e22a2274SMahesh Salgaonkar #define P7_DSISR_MC_ERAT_MULTIHIT (PPC_BIT(52)) /* P8 too */ 50e22a2274SMahesh Salgaonkar #define P7_DSISR_MC_TLB_MULTIHIT_MFTLB (PPC_BIT(53)) /* P8 too */ 51e22a2274SMahesh Salgaonkar #define P7_DSISR_MC_SLB_PARITY_MFSLB (PPC_BIT(55)) /* P8 too */ 52e22a2274SMahesh Salgaonkar #define P7_DSISR_MC_SLB_MULTIHIT (PPC_BIT(56)) /* P8 too */ 53e22a2274SMahesh Salgaonkar #define P7_DSISR_MC_SLB_MULTIHIT_PARITY (PPC_BIT(57)) /* P8 too */ 54e22a2274SMahesh Salgaonkar 55e22a2274SMahesh Salgaonkar /* 56e22a2274SMahesh Salgaonkar * DSISR bits for machine check (Power8) in addition to above. 57e22a2274SMahesh Salgaonkar * Secondary DERAT Multihit 58e22a2274SMahesh Salgaonkar */ 59e22a2274SMahesh Salgaonkar #define P8_DSISR_MC_ERAT_MULTIHIT_SEC (PPC_BIT(54)) 60e22a2274SMahesh Salgaonkar 61e22a2274SMahesh Salgaonkar /* SLB error bits */ 62e22a2274SMahesh Salgaonkar #define P7_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_ERAT_MULTIHIT | \ 63e22a2274SMahesh Salgaonkar P7_DSISR_MC_SLB_PARITY_MFSLB | \ 64e22a2274SMahesh Salgaonkar P7_DSISR_MC_SLB_MULTIHIT | \ 65e22a2274SMahesh Salgaonkar P7_DSISR_MC_SLB_MULTIHIT_PARITY) 66e22a2274SMahesh Salgaonkar 67*ae744f34SMahesh Salgaonkar #define P8_DSISR_MC_SLB_ERRORS (P7_DSISR_MC_SLB_ERRORS | \ 68*ae744f34SMahesh Salgaonkar P8_DSISR_MC_ERAT_MULTIHIT_SEC) 69*ae744f34SMahesh Salgaonkar 70e22a2274SMahesh Salgaonkar #endif /* __ASM_PPC64_MCE_H__ */ 71