1b8b572e1SStephen Rothwell /* 2b8b572e1SStephen Rothwell * lppaca.h 3b8b572e1SStephen Rothwell * Copyright (C) 2001 Mike Corrigan IBM Corporation 4b8b572e1SStephen Rothwell * 5b8b572e1SStephen Rothwell * This program is free software; you can redistribute it and/or modify 6b8b572e1SStephen Rothwell * it under the terms of the GNU General Public License as published by 7b8b572e1SStephen Rothwell * the Free Software Foundation; either version 2 of the License, or 8b8b572e1SStephen Rothwell * (at your option) any later version. 9b8b572e1SStephen Rothwell * 10b8b572e1SStephen Rothwell * This program is distributed in the hope that it will be useful, 11b8b572e1SStephen Rothwell * but WITHOUT ANY WARRANTY; without even the implied warranty of 12b8b572e1SStephen Rothwell * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13b8b572e1SStephen Rothwell * GNU General Public License for more details. 14b8b572e1SStephen Rothwell * 15b8b572e1SStephen Rothwell * You should have received a copy of the GNU General Public License 16b8b572e1SStephen Rothwell * along with this program; if not, write to the Free Software 17b8b572e1SStephen Rothwell * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18b8b572e1SStephen Rothwell */ 19b8b572e1SStephen Rothwell #ifndef _ASM_POWERPC_LPPACA_H 20b8b572e1SStephen Rothwell #define _ASM_POWERPC_LPPACA_H 21b8b572e1SStephen Rothwell #ifdef __KERNEL__ 22b8b572e1SStephen Rothwell 23*94491685SBenjamin Herrenschmidt /* These definitions relate to hypervisors that only exist when using 24*94491685SBenjamin Herrenschmidt * a server type processor 25*94491685SBenjamin Herrenschmidt */ 26*94491685SBenjamin Herrenschmidt #ifdef CONFIG_PPC_BOOK3S 27*94491685SBenjamin Herrenschmidt 28b8b572e1SStephen Rothwell //============================================================================= 29b8b572e1SStephen Rothwell // 30b8b572e1SStephen Rothwell // This control block contains the data that is shared between the 31b8b572e1SStephen Rothwell // hypervisor (PLIC) and the OS. 32b8b572e1SStephen Rothwell // 33b8b572e1SStephen Rothwell // 34b8b572e1SStephen Rothwell //---------------------------------------------------------------------------- 35b8b572e1SStephen Rothwell #include <linux/cache.h> 36b8b572e1SStephen Rothwell #include <asm/types.h> 37b8b572e1SStephen Rothwell #include <asm/mmu.h> 38b8b572e1SStephen Rothwell 39b8b572e1SStephen Rothwell /* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k 40b8b572e1SStephen Rothwell * alignment is sufficient to prevent this */ 41b8b572e1SStephen Rothwell struct lppaca { 42b8b572e1SStephen Rothwell //============================================================================= 43b8b572e1SStephen Rothwell // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data 44b8b572e1SStephen Rothwell // NOTE: The xDynXyz fields are fields that will be dynamically changed by 45b8b572e1SStephen Rothwell // PLIC when preparing to bring a processor online or when dispatching a 46b8b572e1SStephen Rothwell // virtual processor! 47b8b572e1SStephen Rothwell //============================================================================= 48b8b572e1SStephen Rothwell u32 desc; // Eye catcher 0xD397D781 x00-x03 49b8b572e1SStephen Rothwell u16 size; // Size of this struct x04-x05 50b8b572e1SStephen Rothwell u16 reserved1; // Reserved x06-x07 51b8b572e1SStephen Rothwell u16 reserved2:14; // Reserved x08-x09 52b8b572e1SStephen Rothwell u8 shared_proc:1; // Shared processor indicator ... 53b8b572e1SStephen Rothwell u8 secondary_thread:1; // Secondary thread indicator ... 54b8b572e1SStephen Rothwell volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A 55b8b572e1SStephen Rothwell u8 secondary_thread_count; // Secondary thread count x0B-x0B 56b8b572e1SStephen Rothwell volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D 57b8b572e1SStephen Rothwell volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F 58b8b572e1SStephen Rothwell u32 decr_val; // Value for Decr programming x10-x13 59b8b572e1SStephen Rothwell u32 pmc_val; // Value for PMC regs x14-x17 60b8b572e1SStephen Rothwell volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B 61b8b572e1SStephen Rothwell volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F 62b8b572e1SStephen Rothwell volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23 63b8b572e1SStephen Rothwell u32 dsei_data; // DSEI data x24-x27 64b8b572e1SStephen Rothwell u64 sprg3; // SPRG3 value x28-x2F 65b8b572e1SStephen Rothwell u8 reserved3[80]; // Reserved x30-x7F 66b8b572e1SStephen Rothwell 67b8b572e1SStephen Rothwell //============================================================================= 68b8b572e1SStephen Rothwell // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data 69b8b572e1SStephen Rothwell //============================================================================= 70b8b572e1SStephen Rothwell // This Dword contains a byte for each type of interrupt that can occur. 71b8b572e1SStephen Rothwell // The IPI is a count while the others are just a binary 1 or 0. 72b8b572e1SStephen Rothwell union { 73b8b572e1SStephen Rothwell u64 any_int; 74b8b572e1SStephen Rothwell struct { 75b8b572e1SStephen Rothwell u16 reserved; // Reserved - cleared by #mpasmbl 76b8b572e1SStephen Rothwell u8 xirr_int; // Indicates xXirrValue is valid or Immed IO 77b8b572e1SStephen Rothwell u8 ipi_cnt; // IPI Count 78b8b572e1SStephen Rothwell u8 decr_int; // DECR interrupt occurred 79b8b572e1SStephen Rothwell u8 pdc_int; // PDC interrupt occurred 80b8b572e1SStephen Rothwell u8 quantum_int; // Interrupt quantum reached 81b8b572e1SStephen Rothwell u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending 82b8b572e1SStephen Rothwell } fields; 83b8b572e1SStephen Rothwell } int_dword; 84b8b572e1SStephen Rothwell 85b8b572e1SStephen Rothwell // Whenever any fields in this Dword are set then PLIC will defer the 86b8b572e1SStephen Rothwell // processing of external interrupts. Note that PLIC will store the 87b8b572e1SStephen Rothwell // XIRR directly into the xXirrValue field so that another XIRR will 88b8b572e1SStephen Rothwell // not be presented until this one clears. The layout of the low 89b8b572e1SStephen Rothwell // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the 90b8b572e1SStephen Rothwell // entire Dword is zero or not. A non-zero value in the low order 91b8b572e1SStephen Rothwell // 2-bytes will result in SLIC being granted the highest thread 92b8b572e1SStephen Rothwell // priority upon return. A 0 will return to SLIC as medium priority. 93b8b572e1SStephen Rothwell u64 plic_defer_ints_area; // Entire Dword 94b8b572e1SStephen Rothwell 95b8b572e1SStephen Rothwell // Used to pass the real SRR0/1 from PLIC to SLIC as well as to 96b8b572e1SStephen Rothwell // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid. 97b8b572e1SStephen Rothwell u64 saved_srr0; // Saved SRR0 x10-x17 98b8b572e1SStephen Rothwell u64 saved_srr1; // Saved SRR1 x18-x1F 99b8b572e1SStephen Rothwell 100b8b572e1SStephen Rothwell // Used to pass parms from the OS to PLIC for SetAsrAndRfid 101b8b572e1SStephen Rothwell u64 saved_gpr3; // Saved GPR3 x20-x27 102b8b572e1SStephen Rothwell u64 saved_gpr4; // Saved GPR4 x28-x2F 103b8b572e1SStephen Rothwell u64 saved_gpr5; // Saved GPR5 x30-x37 104b8b572e1SStephen Rothwell 105098e8957SJeremy Kerr u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38 106b8b572e1SStephen Rothwell u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39 107b8b572e1SStephen Rothwell u8 fpregs_in_use; // FP regs in use x3A-x3A 108b8b572e1SStephen Rothwell u8 pmcregs_in_use; // PMC regs in use x3B-x3B 109b8b572e1SStephen Rothwell volatile u32 saved_decr; // Saved Decr Value x3C-x3F 110b8b572e1SStephen Rothwell volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47 111b8b572e1SStephen Rothwell volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F 112b8b572e1SStephen Rothwell u64 tot_plic_latency; // Accumulated PLIC latency x50-x57 113b8b572e1SStephen Rothwell u64 wait_state_cycles; // Wait cycles for this proc x58-x5F 114b8b572e1SStephen Rothwell u64 end_of_quantum; // TB at end of quantum x60-x67 115b8b572e1SStephen Rothwell u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F 116b8b572e1SStephen Rothwell u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77 117b8b572e1SStephen Rothwell volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B 118b8b572e1SStephen Rothwell u16 slb_count; // # of SLBs to maintain x7C-x7D 119b8b572e1SStephen Rothwell u8 idle; // Indicate OS is idle x7E 120b8b572e1SStephen Rothwell u8 vmxregs_in_use; // VMX registers in use x7F 121b8b572e1SStephen Rothwell 122b8b572e1SStephen Rothwell 123b8b572e1SStephen Rothwell //============================================================================= 124b8b572e1SStephen Rothwell // CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors 125b8b572e1SStephen Rothwell //============================================================================= 126b8b572e1SStephen Rothwell // This is the yield_count. An "odd" value (low bit on) means that 127b8b572e1SStephen Rothwell // the processor is yielded (either because of an OS yield or a PLIC 128b8b572e1SStephen Rothwell // preempt). An even value implies that the processor is currently 129b8b572e1SStephen Rothwell // executing. 130b8b572e1SStephen Rothwell // NOTE: This value will ALWAYS be zero for dedicated processors and 131b8b572e1SStephen Rothwell // will NEVER be zero for shared processors (ie, initialized to a 1). 132b8b572e1SStephen Rothwell volatile u32 yield_count; // PLIC increments each dispatchx00-x03 1330559f0a7SAnton Blanchard volatile u32 dispersion_count; // dispatch changed phys cpu x04-x07 134b8b572e1SStephen Rothwell volatile u64 cmo_faults; // CMO page fault count x08-x0F 135b8b572e1SStephen Rothwell volatile u64 cmo_fault_time; // CMO page fault time x10-x17 136b8b572e1SStephen Rothwell u8 reserved7[104]; // Reserved x18-x7F 137b8b572e1SStephen Rothwell 138b8b572e1SStephen Rothwell //============================================================================= 139b8b572e1SStephen Rothwell // CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data 140b8b572e1SStephen Rothwell //============================================================================= 14140322783SJeremy Kerr u32 page_ins; // CMO Hint - # page ins by OS x00-x03 142098e8957SJeremy Kerr u8 reserved8[148]; // Reserved x04-x97 143098e8957SJeremy Kerr volatile u64 dtl_idx; // Dispatch Trace Log head idx x98-x9F 144098e8957SJeremy Kerr u8 reserved9[96]; // Reserved xA0-xFF 145b8b572e1SStephen Rothwell } __attribute__((__aligned__(0x400))); 146b8b572e1SStephen Rothwell 147b8b572e1SStephen Rothwell extern struct lppaca lppaca[]; 148b8b572e1SStephen Rothwell 149b8b572e1SStephen Rothwell /* 150b8b572e1SStephen Rothwell * SLB shadow buffer structure as defined in the PAPR. The save_area 151b8b572e1SStephen Rothwell * contains adjacent ESID and VSID pairs for each shadowed SLB. The 152b8b572e1SStephen Rothwell * ESID is stored in the lower 64bits, then the VSID. 153b8b572e1SStephen Rothwell */ 154b8b572e1SStephen Rothwell struct slb_shadow { 155b8b572e1SStephen Rothwell u32 persistent; // Number of persistent SLBs x00-x03 156b8b572e1SStephen Rothwell u32 buffer_length; // Total shadow buffer length x04-x07 157b8b572e1SStephen Rothwell u64 reserved; // Alignment x08-x0f 158b8b572e1SStephen Rothwell struct { 159b8b572e1SStephen Rothwell u64 esid; 160b8b572e1SStephen Rothwell u64 vsid; 161b8b572e1SStephen Rothwell } save_area[SLB_NUM_BOLTED]; // x10-x40 162b8b572e1SStephen Rothwell } ____cacheline_aligned; 163b8b572e1SStephen Rothwell 164b8b572e1SStephen Rothwell extern struct slb_shadow slb_shadow[]; 165b8b572e1SStephen Rothwell 166*94491685SBenjamin Herrenschmidt #endif /* CONFIG_PPC_BOOK3S */ 167b8b572e1SStephen Rothwell #endif /* __KERNEL__ */ 168b8b572e1SStephen Rothwell #endif /* _ASM_POWERPC_LPPACA_H */ 169