1 /* 2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 3 * Rewrite, cleanup: 4 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21 #ifndef _ASM_IOMMU_H 22 #define _ASM_IOMMU_H 23 #ifdef __KERNEL__ 24 25 #include <linux/compiler.h> 26 #include <linux/spinlock.h> 27 #include <linux/device.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/bitops.h> 30 #include <asm/machdep.h> 31 #include <asm/types.h> 32 #include <asm/pci-bridge.h> 33 34 #define IOMMU_PAGE_SHIFT_4K 12 35 #define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K) 36 #define IOMMU_PAGE_MASK_4K (~((1 << IOMMU_PAGE_SHIFT_4K) - 1)) 37 #define IOMMU_PAGE_ALIGN_4K(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE_4K) 38 39 #define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift) 40 #define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1)) 41 #define IOMMU_PAGE_ALIGN(addr, tblptr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE(tblptr)) 42 43 /* Boot time flags */ 44 extern int iommu_is_off; 45 extern int iommu_force_on; 46 47 struct iommu_table_ops { 48 /* 49 * When called with direction==DMA_NONE, it is equal to clear(). 50 * uaddr is a linear map address. 51 */ 52 int (*set)(struct iommu_table *tbl, 53 long index, long npages, 54 unsigned long uaddr, 55 enum dma_data_direction direction, 56 unsigned long attrs); 57 #ifdef CONFIG_IOMMU_API 58 /* 59 * Exchanges existing TCE with new TCE plus direction bits; 60 * returns old TCE and DMA direction mask. 61 * @tce is a physical address. 62 */ 63 int (*exchange)(struct iommu_table *tbl, 64 long index, 65 unsigned long *hpa, 66 enum dma_data_direction *direction); 67 /* Real mode */ 68 int (*exchange_rm)(struct iommu_table *tbl, 69 long index, 70 unsigned long *hpa, 71 enum dma_data_direction *direction); 72 73 __be64 *(*useraddrptr)(struct iommu_table *tbl, long index, bool alloc); 74 #endif 75 void (*clear)(struct iommu_table *tbl, 76 long index, long npages); 77 /* get() returns a physical address */ 78 unsigned long (*get)(struct iommu_table *tbl, long index); 79 void (*flush)(struct iommu_table *tbl); 80 void (*free)(struct iommu_table *tbl); 81 }; 82 83 /* These are used by VIO */ 84 extern struct iommu_table_ops iommu_table_lpar_multi_ops; 85 extern struct iommu_table_ops iommu_table_pseries_ops; 86 87 /* 88 * IOMAP_MAX_ORDER defines the largest contiguous block 89 * of dma space we can get. IOMAP_MAX_ORDER = 13 90 * allows up to 2**12 pages (4096 * 4096) = 16 MB 91 */ 92 #define IOMAP_MAX_ORDER 13 93 94 #define IOMMU_POOL_HASHBITS 2 95 #define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS) 96 97 struct iommu_pool { 98 unsigned long start; 99 unsigned long end; 100 unsigned long hint; 101 spinlock_t lock; 102 } ____cacheline_aligned_in_smp; 103 104 struct iommu_table { 105 unsigned long it_busno; /* Bus number this table belongs to */ 106 unsigned long it_size; /* Size of iommu table in entries */ 107 unsigned long it_indirect_levels; 108 unsigned long it_level_size; 109 unsigned long it_allocated_size; 110 unsigned long it_offset; /* Offset into global table */ 111 unsigned long it_base; /* mapped address of tce table */ 112 unsigned long it_index; /* which iommu table this is */ 113 unsigned long it_type; /* type: PCI or Virtual Bus */ 114 unsigned long it_blocksize; /* Entries in each block (cacheline) */ 115 unsigned long poolsize; 116 unsigned long nr_pools; 117 struct iommu_pool large_pool; 118 struct iommu_pool pools[IOMMU_NR_POOLS]; 119 unsigned long *it_map; /* A simple allocation bitmap for now */ 120 unsigned long it_page_shift;/* table iommu page size */ 121 struct list_head it_group_list;/* List of iommu_table_group_link */ 122 __be64 *it_userspace; /* userspace view of the table */ 123 struct iommu_table_ops *it_ops; 124 struct kref it_kref; 125 int it_nid; 126 }; 127 128 #define IOMMU_TABLE_USERSPACE_ENTRY_RM(tbl, entry) \ 129 ((tbl)->it_ops->useraddrptr((tbl), (entry), false)) 130 #define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \ 131 ((tbl)->it_ops->useraddrptr((tbl), (entry), true)) 132 133 /* Pure 2^n version of get_order */ 134 static inline __attribute_const__ 135 int get_iommu_order(unsigned long size, struct iommu_table *tbl) 136 { 137 return __ilog2((size - 1) >> tbl->it_page_shift) + 1; 138 } 139 140 141 struct scatterlist; 142 143 #ifdef CONFIG_PPC64 144 145 #define IOMMU_MAPPING_ERROR (~(dma_addr_t)0x0) 146 147 static inline void set_iommu_table_base(struct device *dev, 148 struct iommu_table *base) 149 { 150 dev->archdata.iommu_table_base = base; 151 } 152 153 static inline void *get_iommu_table_base(struct device *dev) 154 { 155 return dev->archdata.iommu_table_base; 156 } 157 158 extern int dma_iommu_dma_supported(struct device *dev, u64 mask); 159 160 extern struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl); 161 extern int iommu_tce_table_put(struct iommu_table *tbl); 162 163 /* Initializes an iommu_table based in values set in the passed-in 164 * structure 165 */ 166 extern struct iommu_table *iommu_init_table(struct iommu_table * tbl, 167 int nid); 168 #define IOMMU_TABLE_GROUP_MAX_TABLES 2 169 170 struct iommu_table_group; 171 172 struct iommu_table_group_ops { 173 unsigned long (*get_table_size)( 174 __u32 page_shift, 175 __u64 window_size, 176 __u32 levels); 177 long (*create_table)(struct iommu_table_group *table_group, 178 int num, 179 __u32 page_shift, 180 __u64 window_size, 181 __u32 levels, 182 struct iommu_table **ptbl); 183 long (*set_window)(struct iommu_table_group *table_group, 184 int num, 185 struct iommu_table *tblnew); 186 long (*unset_window)(struct iommu_table_group *table_group, 187 int num); 188 /* Switch ownership from platform code to external user (e.g. VFIO) */ 189 void (*take_ownership)(struct iommu_table_group *table_group); 190 /* Switch ownership from external user (e.g. VFIO) back to core */ 191 void (*release_ownership)(struct iommu_table_group *table_group); 192 }; 193 194 struct iommu_table_group_link { 195 struct list_head next; 196 struct rcu_head rcu; 197 struct iommu_table_group *table_group; 198 }; 199 200 struct iommu_table_group { 201 /* IOMMU properties */ 202 __u32 tce32_start; 203 __u32 tce32_size; 204 __u64 pgsizes; /* Bitmap of supported page sizes */ 205 __u32 max_dynamic_windows_supported; 206 __u32 max_levels; 207 208 struct iommu_group *group; 209 struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES]; 210 struct iommu_table_group_ops *ops; 211 }; 212 213 #ifdef CONFIG_IOMMU_API 214 215 extern void iommu_register_group(struct iommu_table_group *table_group, 216 int pci_domain_number, unsigned long pe_num); 217 extern int iommu_add_device(struct device *dev); 218 extern void iommu_del_device(struct device *dev); 219 extern int __init tce_iommu_bus_notifier_init(void); 220 extern long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry, 221 unsigned long *hpa, enum dma_data_direction *direction); 222 extern long iommu_tce_xchg_rm(struct iommu_table *tbl, unsigned long entry, 223 unsigned long *hpa, enum dma_data_direction *direction); 224 #else 225 static inline void iommu_register_group(struct iommu_table_group *table_group, 226 int pci_domain_number, 227 unsigned long pe_num) 228 { 229 } 230 231 static inline int iommu_add_device(struct device *dev) 232 { 233 return 0; 234 } 235 236 static inline void iommu_del_device(struct device *dev) 237 { 238 } 239 240 static inline int __init tce_iommu_bus_notifier_init(void) 241 { 242 return 0; 243 } 244 #endif /* !CONFIG_IOMMU_API */ 245 246 int dma_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr); 247 248 #else 249 250 static inline void *get_iommu_table_base(struct device *dev) 251 { 252 return NULL; 253 } 254 255 static inline int dma_iommu_dma_supported(struct device *dev, u64 mask) 256 { 257 return 0; 258 } 259 260 #endif /* CONFIG_PPC64 */ 261 262 extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl, 263 struct scatterlist *sglist, int nelems, 264 unsigned long mask, 265 enum dma_data_direction direction, 266 unsigned long attrs); 267 extern void ppc_iommu_unmap_sg(struct iommu_table *tbl, 268 struct scatterlist *sglist, 269 int nelems, 270 enum dma_data_direction direction, 271 unsigned long attrs); 272 273 extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl, 274 size_t size, dma_addr_t *dma_handle, 275 unsigned long mask, gfp_t flag, int node); 276 extern void iommu_free_coherent(struct iommu_table *tbl, size_t size, 277 void *vaddr, dma_addr_t dma_handle); 278 extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl, 279 struct page *page, unsigned long offset, 280 size_t size, unsigned long mask, 281 enum dma_data_direction direction, 282 unsigned long attrs); 283 extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle, 284 size_t size, enum dma_data_direction direction, 285 unsigned long attrs); 286 287 extern void iommu_init_early_pSeries(void); 288 extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops); 289 extern void iommu_init_early_pasemi(void); 290 291 #if defined(CONFIG_PPC64) && defined(CONFIG_PM) 292 static inline void iommu_save(void) 293 { 294 if (ppc_md.iommu_save) 295 ppc_md.iommu_save(); 296 } 297 298 static inline void iommu_restore(void) 299 { 300 if (ppc_md.iommu_restore) 301 ppc_md.iommu_restore(); 302 } 303 #endif 304 305 /* The API to support IOMMU operations for VFIO */ 306 extern int iommu_tce_check_ioba(unsigned long page_shift, 307 unsigned long offset, unsigned long size, 308 unsigned long ioba, unsigned long npages); 309 extern int iommu_tce_check_gpa(unsigned long page_shift, 310 unsigned long gpa); 311 312 #define iommu_tce_clear_param_check(tbl, ioba, tce_value, npages) \ 313 (iommu_tce_check_ioba((tbl)->it_page_shift, \ 314 (tbl)->it_offset, (tbl)->it_size, \ 315 (ioba), (npages)) || (tce_value)) 316 #define iommu_tce_put_param_check(tbl, ioba, gpa) \ 317 (iommu_tce_check_ioba((tbl)->it_page_shift, \ 318 (tbl)->it_offset, (tbl)->it_size, \ 319 (ioba), 1) || \ 320 iommu_tce_check_gpa((tbl)->it_page_shift, (gpa))) 321 322 extern void iommu_flush_tce(struct iommu_table *tbl); 323 extern int iommu_take_ownership(struct iommu_table *tbl); 324 extern void iommu_release_ownership(struct iommu_table *tbl); 325 326 extern enum dma_data_direction iommu_tce_direction(unsigned long tce); 327 extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir); 328 329 #endif /* __KERNEL__ */ 330 #endif /* _ASM_IOMMU_H */ 331