1 #ifndef _ASM_POWERPC_IO_H 2 #define _ASM_POWERPC_IO_H 3 #ifdef __KERNEL__ 4 5 #define ARCH_HAS_IOREMAP_WC 6 7 /* 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 /* Check of existence of legacy devices */ 15 extern int check_legacy_ioport(unsigned long base_port); 16 #define I8042_DATA_REG 0x60 17 #define FDC_BASE 0x3f0 18 19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) 20 extern struct pci_dev *isa_bridge_pcidev; 21 /* 22 * has legacy ISA devices ? 23 */ 24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special) 25 #endif 26 27 #include <linux/device.h> 28 #include <linux/io.h> 29 30 #include <linux/compiler.h> 31 #include <asm/page.h> 32 #include <asm/byteorder.h> 33 #include <asm/synch.h> 34 #include <asm/delay.h> 35 #include <asm/mmu.h> 36 37 #include <asm-generic/iomap.h> 38 39 #ifdef CONFIG_PPC64 40 #include <asm/paca.h> 41 #endif 42 43 #define SIO_CONFIG_RA 0x398 44 #define SIO_CONFIG_RD 0x399 45 46 #define SLOW_DOWN_IO 47 48 /* 32 bits uses slightly different variables for the various IO 49 * bases. Most of this file only uses _IO_BASE though which we 50 * define properly based on the platform 51 */ 52 #ifndef CONFIG_PCI 53 #define _IO_BASE 0 54 #define _ISA_MEM_BASE 0 55 #define PCI_DRAM_OFFSET 0 56 #elif defined(CONFIG_PPC32) 57 #define _IO_BASE isa_io_base 58 #define _ISA_MEM_BASE isa_mem_base 59 #define PCI_DRAM_OFFSET pci_dram_offset 60 #else 61 #define _IO_BASE pci_io_base 62 #define _ISA_MEM_BASE isa_mem_base 63 #define PCI_DRAM_OFFSET 0 64 #endif 65 66 extern unsigned long isa_io_base; 67 extern unsigned long pci_io_base; 68 extern unsigned long pci_dram_offset; 69 70 extern resource_size_t isa_mem_base; 71 72 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE 73 * is not set or addresses cannot be translated to MMIO. This is typically 74 * set when the platform supports "special" PIO accesses via a non memory 75 * mapped mechanism, and allows things like the early udbg UART code to 76 * function. 77 */ 78 extern bool isa_io_special; 79 80 #ifdef CONFIG_PPC32 81 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 82 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits 83 #endif 84 #endif 85 86 /* 87 * 88 * Low level MMIO accessors 89 * 90 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 91 * specific and thus shouldn't be used in generic code. The accessors 92 * provided here are: 93 * 94 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 95 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 96 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 97 * 98 * Those operate directly on a kernel virtual address. Note that the prototype 99 * for the out_* accessors has the arguments in opposite order from the usual 100 * linux PCI accessors. Unlike those, they take the address first and the value 101 * next. 102 * 103 * Note: I might drop the _ns suffix on the stream operations soon as it is 104 * simply normal for stream operations to not swap in the first place. 105 * 106 */ 107 108 #ifdef CONFIG_PPC64 109 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) 110 #else 111 #define IO_SET_SYNC_FLAG() 112 #endif 113 114 /* gcc 4.0 and older doesn't have 'Z' constraint */ 115 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0) 116 #define DEF_MMIO_IN_X(name, size, insn) \ 117 static inline u##size name(const volatile u##size __iomem *addr) \ 118 { \ 119 u##size ret; \ 120 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \ 121 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \ 122 return ret; \ 123 } 124 125 #define DEF_MMIO_OUT_X(name, size, insn) \ 126 static inline void name(volatile u##size __iomem *addr, u##size val) \ 127 { \ 128 __asm__ __volatile__("sync;"#insn" %1,0,%2" \ 129 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \ 130 IO_SET_SYNC_FLAG(); \ 131 } 132 #else /* newer gcc */ 133 #define DEF_MMIO_IN_X(name, size, insn) \ 134 static inline u##size name(const volatile u##size __iomem *addr) \ 135 { \ 136 u##size ret; \ 137 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ 138 : "=r" (ret) : "Z" (*addr) : "memory"); \ 139 return ret; \ 140 } 141 142 #define DEF_MMIO_OUT_X(name, size, insn) \ 143 static inline void name(volatile u##size __iomem *addr, u##size val) \ 144 { \ 145 __asm__ __volatile__("sync;"#insn" %1,%y0" \ 146 : "=Z" (*addr) : "r" (val) : "memory"); \ 147 IO_SET_SYNC_FLAG(); \ 148 } 149 #endif 150 151 #define DEF_MMIO_IN_D(name, size, insn) \ 152 static inline u##size name(const volatile u##size __iomem *addr) \ 153 { \ 154 u##size ret; \ 155 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ 156 : "=r" (ret) : "m" (*addr) : "memory"); \ 157 return ret; \ 158 } 159 160 #define DEF_MMIO_OUT_D(name, size, insn) \ 161 static inline void name(volatile u##size __iomem *addr, u##size val) \ 162 { \ 163 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ 164 : "=m" (*addr) : "r" (val) : "memory"); \ 165 IO_SET_SYNC_FLAG(); \ 166 } 167 168 DEF_MMIO_IN_D(in_8, 8, lbz); 169 DEF_MMIO_OUT_D(out_8, 8, stb); 170 171 #ifdef __BIG_ENDIAN__ 172 DEF_MMIO_IN_D(in_be16, 16, lhz); 173 DEF_MMIO_IN_D(in_be32, 32, lwz); 174 DEF_MMIO_IN_X(in_le16, 16, lhbrx); 175 DEF_MMIO_IN_X(in_le32, 32, lwbrx); 176 177 DEF_MMIO_OUT_D(out_be16, 16, sth); 178 DEF_MMIO_OUT_D(out_be32, 32, stw); 179 DEF_MMIO_OUT_X(out_le16, 16, sthbrx); 180 DEF_MMIO_OUT_X(out_le32, 32, stwbrx); 181 #else 182 DEF_MMIO_IN_X(in_be16, 16, lhbrx); 183 DEF_MMIO_IN_X(in_be32, 32, lwbrx); 184 DEF_MMIO_IN_D(in_le16, 16, lhz); 185 DEF_MMIO_IN_D(in_le32, 32, lwz); 186 187 DEF_MMIO_OUT_X(out_be16, 16, sthbrx); 188 DEF_MMIO_OUT_X(out_be32, 32, stwbrx); 189 DEF_MMIO_OUT_D(out_le16, 16, sth); 190 DEF_MMIO_OUT_D(out_le32, 32, stw); 191 192 #endif /* __BIG_ENDIAN */ 193 194 #ifdef __powerpc64__ 195 196 #ifdef __BIG_ENDIAN__ 197 DEF_MMIO_OUT_D(out_be64, 64, std); 198 DEF_MMIO_IN_D(in_be64, 64, ld); 199 200 /* There is no asm instructions for 64 bits reverse loads and stores */ 201 static inline u64 in_le64(const volatile u64 __iomem *addr) 202 { 203 return swab64(in_be64(addr)); 204 } 205 206 static inline void out_le64(volatile u64 __iomem *addr, u64 val) 207 { 208 out_be64(addr, swab64(val)); 209 } 210 #else 211 DEF_MMIO_OUT_D(out_le64, 64, std); 212 DEF_MMIO_IN_D(in_le64, 64, ld); 213 214 /* There is no asm instructions for 64 bits reverse loads and stores */ 215 static inline u64 in_be64(const volatile u64 __iomem *addr) 216 { 217 return swab64(in_le64(addr)); 218 } 219 220 static inline void out_be64(volatile u64 __iomem *addr, u64 val) 221 { 222 out_le64(addr, swab64(val)); 223 } 224 225 #endif 226 #endif /* __powerpc64__ */ 227 228 /* 229 * Low level IO stream instructions are defined out of line for now 230 */ 231 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 232 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 233 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 234 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 235 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 236 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 237 238 /* The _ns naming is historical and will be removed. For now, just #define 239 * the non _ns equivalent names 240 */ 241 #define _insw _insw_ns 242 #define _insl _insl_ns 243 #define _outsw _outsw_ns 244 #define _outsl _outsl_ns 245 246 247 /* 248 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 249 */ 250 251 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 252 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 253 unsigned long n); 254 extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 255 unsigned long n); 256 257 /* 258 * 259 * PCI and standard ISA accessors 260 * 261 * Those are globally defined linux accessors for devices on PCI or ISA 262 * busses. They follow the Linux defined semantics. The current implementation 263 * for PowerPC is as close as possible to the x86 version of these, and thus 264 * provides fairly heavy weight barriers for the non-raw versions 265 * 266 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO 267 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its 268 * own implementation of some or all of the accessors. 269 */ 270 271 /* 272 * Include the EEH definitions when EEH is enabled only so they don't get 273 * in the way when building for 32 bits 274 */ 275 #ifdef CONFIG_EEH 276 #include <asm/eeh.h> 277 #endif 278 279 /* Shortcut to the MMIO argument pointer */ 280 #define PCI_IO_ADDR volatile void __iomem * 281 282 /* Indirect IO address tokens: 283 * 284 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks 285 * on all MMIOs. (Note that this is all 64 bits only for now) 286 * 287 * To help platforms who may need to differenciate MMIO addresses in 288 * their hooks, a bitfield is reserved for use by the platform near the 289 * top of MMIO addresses (not PIO, those have to cope the hard way). 290 * 291 * This bit field is 12 bits and is at the top of the IO virtual 292 * addresses PCI_IO_INDIRECT_TOKEN_MASK. 293 * 294 * The kernel virtual space is thus: 295 * 296 * 0xD000000000000000 : vmalloc 297 * 0xD000080000000000 : PCI PHB IO space 298 * 0xD000080080000000 : ioremap 299 * 0xD0000fffffffffff : end of ioremap region 300 * 301 * Since the top 4 bits are reserved as the region ID, we use thus 302 * the next 12 bits and keep 4 bits available for the future if the 303 * virtual address space is ever to be extended. 304 * 305 * The direct IO mapping operations will then mask off those bits 306 * before doing the actual access, though that only happen when 307 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that 308 * mechanism 309 * 310 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes 311 * all PIO functions call through a hook. 312 */ 313 314 #ifdef CONFIG_PPC_INDIRECT_MMIO 315 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul 316 #define PCI_IO_IND_TOKEN_SHIFT 48 317 #define PCI_FIX_ADDR(addr) \ 318 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 319 #define PCI_GET_ADDR_TOKEN(addr) \ 320 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 321 PCI_IO_IND_TOKEN_SHIFT) 322 #define PCI_SET_ADDR_TOKEN(addr, token) \ 323 do { \ 324 unsigned long __a = (unsigned long)(addr); \ 325 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 326 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 327 (addr) = (void __iomem *)__a; \ 328 } while(0) 329 #else 330 #define PCI_FIX_ADDR(addr) (addr) 331 #endif 332 333 334 /* 335 * Non ordered and non-swapping "raw" accessors 336 */ 337 338 static inline unsigned char __raw_readb(const volatile void __iomem *addr) 339 { 340 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 341 } 342 static inline unsigned short __raw_readw(const volatile void __iomem *addr) 343 { 344 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 345 } 346 static inline unsigned int __raw_readl(const volatile void __iomem *addr) 347 { 348 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 349 } 350 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 351 { 352 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 353 } 354 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 355 { 356 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 357 } 358 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 359 { 360 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 361 } 362 363 #ifdef __powerpc64__ 364 static inline unsigned long __raw_readq(const volatile void __iomem *addr) 365 { 366 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 367 } 368 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 369 { 370 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 371 } 372 #endif /* __powerpc64__ */ 373 374 /* 375 * 376 * PCI PIO and MMIO accessors. 377 * 378 * 379 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 380 * machine checks (which they occasionally do when probing non existing 381 * IO ports on some platforms, like PowerMac and 8xx). 382 * I always found it to be of dubious reliability and I am tempted to get 383 * rid of it one of these days. So if you think it's important to keep it, 384 * please voice up asap. We never had it for 64 bits and I do not intend 385 * to port it over 386 */ 387 388 #ifdef CONFIG_PPC32 389 390 #define __do_in_asm(name, op) \ 391 static inline unsigned int name(unsigned int port) \ 392 { \ 393 unsigned int x; \ 394 __asm__ __volatile__( \ 395 "sync\n" \ 396 "0:" op " %0,0,%1\n" \ 397 "1: twi 0,%0,0\n" \ 398 "2: isync\n" \ 399 "3: nop\n" \ 400 "4:\n" \ 401 ".section .fixup,\"ax\"\n" \ 402 "5: li %0,-1\n" \ 403 " b 4b\n" \ 404 ".previous\n" \ 405 ".section __ex_table,\"a\"\n" \ 406 " .align 2\n" \ 407 " .long 0b,5b\n" \ 408 " .long 1b,5b\n" \ 409 " .long 2b,5b\n" \ 410 " .long 3b,5b\n" \ 411 ".previous" \ 412 : "=&r" (x) \ 413 : "r" (port + _IO_BASE) \ 414 : "memory"); \ 415 return x; \ 416 } 417 418 #define __do_out_asm(name, op) \ 419 static inline void name(unsigned int val, unsigned int port) \ 420 { \ 421 __asm__ __volatile__( \ 422 "sync\n" \ 423 "0:" op " %0,0,%1\n" \ 424 "1: sync\n" \ 425 "2:\n" \ 426 ".section __ex_table,\"a\"\n" \ 427 " .align 2\n" \ 428 " .long 0b,2b\n" \ 429 " .long 1b,2b\n" \ 430 ".previous" \ 431 : : "r" (val), "r" (port + _IO_BASE) \ 432 : "memory"); \ 433 } 434 435 __do_in_asm(_rec_inb, "lbzx") 436 __do_in_asm(_rec_inw, "lhbrx") 437 __do_in_asm(_rec_inl, "lwbrx") 438 __do_out_asm(_rec_outb, "stbx") 439 __do_out_asm(_rec_outw, "sthbrx") 440 __do_out_asm(_rec_outl, "stwbrx") 441 442 #endif /* CONFIG_PPC32 */ 443 444 /* The "__do_*" operations below provide the actual "base" implementation 445 * for each of the defined accessors. Some of them use the out_* functions 446 * directly, some of them still use EEH, though we might change that in the 447 * future. Those macros below provide the necessary argument swapping and 448 * handling of the IO base for PIO. 449 * 450 * They are themselves used by the macros that define the actual accessors 451 * and can be used by the hooks if any. 452 * 453 * Note that PIO operations are always defined in terms of their corresonding 454 * MMIO operations. That allows platforms like iSeries who want to modify the 455 * behaviour of both to only hook on the MMIO version and get both. It's also 456 * possible to hook directly at the toplevel PIO operation if they have to 457 * be handled differently 458 */ 459 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 460 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 461 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 462 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 463 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 464 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 465 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 466 467 #ifdef CONFIG_EEH 468 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 469 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 470 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 471 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 472 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 473 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 474 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 475 #else /* CONFIG_EEH */ 476 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 477 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 478 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 479 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 480 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 481 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 482 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 483 #endif /* !defined(CONFIG_EEH) */ 484 485 #ifdef CONFIG_PPC32 486 #define __do_outb(val, port) _rec_outb(val, port) 487 #define __do_outw(val, port) _rec_outw(val, port) 488 #define __do_outl(val, port) _rec_outl(val, port) 489 #define __do_inb(port) _rec_inb(port) 490 #define __do_inw(port) _rec_inw(port) 491 #define __do_inl(port) _rec_inl(port) 492 #else /* CONFIG_PPC32 */ 493 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 494 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 495 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 496 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 497 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 498 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 499 #endif /* !CONFIG_PPC32 */ 500 501 #ifdef CONFIG_EEH 502 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 503 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 504 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 505 #else /* CONFIG_EEH */ 506 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 507 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 508 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 509 #endif /* !CONFIG_EEH */ 510 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 511 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 512 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 513 514 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 515 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 516 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 517 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 518 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 519 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 520 521 #define __do_memset_io(addr, c, n) \ 522 _memset_io(PCI_FIX_ADDR(addr), c, n) 523 #define __do_memcpy_toio(dst, src, n) \ 524 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 525 526 #ifdef CONFIG_EEH 527 #define __do_memcpy_fromio(dst, src, n) \ 528 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 529 #else /* CONFIG_EEH */ 530 #define __do_memcpy_fromio(dst, src, n) \ 531 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 532 #endif /* !CONFIG_EEH */ 533 534 #ifdef CONFIG_PPC_INDIRECT_PIO 535 #define DEF_PCI_HOOK_pio(x) x 536 #else 537 #define DEF_PCI_HOOK_pio(x) NULL 538 #endif 539 540 #ifdef CONFIG_PPC_INDIRECT_MMIO 541 #define DEF_PCI_HOOK_mem(x) x 542 #else 543 #define DEF_PCI_HOOK_mem(x) NULL 544 #endif 545 546 /* Structure containing all the hooks */ 547 extern struct ppc_pci_io { 548 549 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; 550 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; 551 552 #include <asm/io-defs.h> 553 554 #undef DEF_PCI_AC_RET 555 #undef DEF_PCI_AC_NORET 556 557 } ppc_pci_io; 558 559 /* The inline wrappers */ 560 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 561 static inline ret name at \ 562 { \ 563 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 564 return ppc_pci_io.name al; \ 565 return __do_##name al; \ 566 } 567 568 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 569 static inline void name at \ 570 { \ 571 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 572 ppc_pci_io.name al; \ 573 else \ 574 __do_##name al; \ 575 } 576 577 #include <asm/io-defs.h> 578 579 #undef DEF_PCI_AC_RET 580 #undef DEF_PCI_AC_NORET 581 582 /* Some drivers check for the presence of readq & writeq with 583 * a #ifdef, so we make them happy here. 584 */ 585 #ifdef __powerpc64__ 586 #define readq readq 587 #define writeq writeq 588 #endif 589 590 /* 591 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 592 * access 593 */ 594 #define xlate_dev_mem_ptr(p) __va(p) 595 596 /* 597 * Convert a virtual cached pointer to an uncached pointer 598 */ 599 #define xlate_dev_kmem_ptr(p) p 600 601 /* 602 * We don't do relaxed operations yet, at least not with this semantic 603 */ 604 #define readb_relaxed(addr) readb(addr) 605 #define readw_relaxed(addr) readw(addr) 606 #define readl_relaxed(addr) readl(addr) 607 #define readq_relaxed(addr) readq(addr) 608 609 #ifdef CONFIG_PPC32 610 #define mmiowb() 611 #else 612 /* 613 * Enforce synchronisation of stores vs. spin_unlock 614 * (this does it explicitly, though our implementation of spin_unlock 615 * does it implicitely too) 616 */ 617 static inline void mmiowb(void) 618 { 619 unsigned long tmp; 620 621 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" 622 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 623 : "memory"); 624 } 625 #endif /* !CONFIG_PPC32 */ 626 627 static inline void iosync(void) 628 { 629 __asm__ __volatile__ ("sync" : : : "memory"); 630 } 631 632 /* Enforce in-order execution of data I/O. 633 * No distinction between read/write on PPC; use eieio for all three. 634 * Those are fairly week though. They don't provide a barrier between 635 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 636 * they only provide barriers between 2 __raw MMIO operations and 637 * possibly break write combining. 638 */ 639 #define iobarrier_rw() eieio() 640 #define iobarrier_r() eieio() 641 #define iobarrier_w() eieio() 642 643 644 /* 645 * output pause versions need a delay at least for the 646 * w83c105 ide controller in a p610. 647 */ 648 #define inb_p(port) inb(port) 649 #define outb_p(val, port) (udelay(1), outb((val), (port))) 650 #define inw_p(port) inw(port) 651 #define outw_p(val, port) (udelay(1), outw((val), (port))) 652 #define inl_p(port) inl(port) 653 #define outl_p(val, port) (udelay(1), outl((val), (port))) 654 655 656 #define IO_SPACE_LIMIT ~(0UL) 657 658 659 /** 660 * ioremap - map bus memory into CPU space 661 * @address: bus address of the memory 662 * @size: size of the resource to map 663 * 664 * ioremap performs a platform specific sequence of operations to 665 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 666 * writew/writel functions and the other mmio helpers. The returned 667 * address is not guaranteed to be usable directly as a virtual 668 * address. 669 * 670 * We provide a few variations of it: 671 * 672 * * ioremap is the standard one and provides non-cacheable guarded mappings 673 * and can be hooked by the platform via ppc_md 674 * 675 * * ioremap_prot allows to specify the page flags as an argument and can 676 * also be hooked by the platform via ppc_md. 677 * 678 * * ioremap_nocache is identical to ioremap 679 * 680 * * ioremap_wc enables write combining 681 * 682 * * iounmap undoes such a mapping and can be hooked 683 * 684 * * __ioremap_at (and the pending __iounmap_at) are low level functions to 685 * create hand-made mappings for use only by the PCI code and cannot 686 * currently be hooked. Must be page aligned. 687 * 688 * * __ioremap is the low level implementation used by ioremap and 689 * ioremap_prot and cannot be hooked (but can be used by a hook on one 690 * of the previous ones) 691 * 692 * * __ioremap_caller is the same as above but takes an explicit caller 693 * reference rather than using __builtin_return_address(0) 694 * 695 * * __iounmap, is the low level implementation used by iounmap and cannot 696 * be hooked (but can be used by a hook on iounmap) 697 * 698 */ 699 extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 700 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, 701 unsigned long flags); 702 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); 703 #define ioremap_nocache(addr, size) ioremap((addr), (size)) 704 705 extern void iounmap(volatile void __iomem *addr); 706 707 extern void __iomem *__ioremap(phys_addr_t, unsigned long size, 708 unsigned long flags); 709 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, 710 unsigned long flags, void *caller); 711 712 extern void __iounmap(volatile void __iomem *addr); 713 714 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea, 715 unsigned long size, unsigned long flags); 716 extern void __iounmap_at(void *ea, unsigned long size); 717 718 /* 719 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation 720 * which needs some additional definitions here. They basically allow PIO 721 * space overall to be 1GB. This will work as long as we never try to use 722 * iomap to map MMIO below 1GB which should be fine on ppc64 723 */ 724 #define HAVE_ARCH_PIO_SIZE 1 725 #define PIO_OFFSET 0x00000000UL 726 #define PIO_MASK (FULL_IO_SIZE - 1) 727 #define PIO_RESERVED (FULL_IO_SIZE) 728 729 #define mmio_read16be(addr) readw_be(addr) 730 #define mmio_read32be(addr) readl_be(addr) 731 #define mmio_write16be(val, addr) writew_be(val, addr) 732 #define mmio_write32be(val, addr) writel_be(val, addr) 733 #define mmio_insb(addr, dst, count) readsb(addr, dst, count) 734 #define mmio_insw(addr, dst, count) readsw(addr, dst, count) 735 #define mmio_insl(addr, dst, count) readsl(addr, dst, count) 736 #define mmio_outsb(addr, src, count) writesb(addr, src, count) 737 #define mmio_outsw(addr, src, count) writesw(addr, src, count) 738 #define mmio_outsl(addr, src, count) writesl(addr, src, count) 739 740 /** 741 * virt_to_phys - map virtual addresses to physical 742 * @address: address to remap 743 * 744 * The returned physical address is the physical (CPU) mapping for 745 * the memory address given. It is only valid to use this function on 746 * addresses directly mapped or allocated via kmalloc. 747 * 748 * This function does not give bus mappings for DMA transfers. In 749 * almost all conceivable cases a device driver should not be using 750 * this function 751 */ 752 static inline unsigned long virt_to_phys(volatile void * address) 753 { 754 return __pa((unsigned long)address); 755 } 756 757 /** 758 * phys_to_virt - map physical address to virtual 759 * @address: address to remap 760 * 761 * The returned virtual address is a current CPU mapping for 762 * the memory address given. It is only valid to use this function on 763 * addresses that have a kernel mapping 764 * 765 * This function does not handle bus mappings for DMA transfers. In 766 * almost all conceivable cases a device driver should not be using 767 * this function 768 */ 769 static inline void * phys_to_virt(unsigned long address) 770 { 771 return (void *)__va(address); 772 } 773 774 /* 775 * Change "struct page" to physical address. 776 */ 777 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT) 778 779 /* 780 * 32 bits still uses virt_to_bus() for it's implementation of DMA 781 * mappings se we have to keep it defined here. We also have some old 782 * drivers (shame shame shame) that use bus_to_virt() and haven't been 783 * fixed yet so I need to define it here. 784 */ 785 #ifdef CONFIG_PPC32 786 787 static inline unsigned long virt_to_bus(volatile void * address) 788 { 789 if (address == NULL) 790 return 0; 791 return __pa(address) + PCI_DRAM_OFFSET; 792 } 793 794 static inline void * bus_to_virt(unsigned long address) 795 { 796 if (address == 0) 797 return NULL; 798 return __va(address - PCI_DRAM_OFFSET); 799 } 800 801 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 802 803 #endif /* CONFIG_PPC32 */ 804 805 /* access ports */ 806 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 807 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 808 809 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 810 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 811 812 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) 813 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) 814 815 /* Clear and set bits in one shot. These macros can be used to clear and 816 * set multiple bits in a register using a single read-modify-write. These 817 * macros can also be used to set a multiple-bit bit pattern using a mask, 818 * by specifying the mask in the 'clear' parameter and the new bit pattern 819 * in the 'set' parameter. 820 */ 821 822 #define clrsetbits(type, addr, clear, set) \ 823 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 824 825 #ifdef __powerpc64__ 826 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) 827 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) 828 #endif 829 830 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 831 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 832 833 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 834 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 835 836 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 837 838 void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset, 839 size_t size, unsigned long flags); 840 841 #endif /* __KERNEL__ */ 842 843 #endif /* _ASM_POWERPC_IO_H */ 844