1b8b572e1SStephen Rothwell /* Freescale Local Bus Controller 2b8b572e1SStephen Rothwell * 33ab8f2a2SRoy Zang * Copyright © 2006-2007, 2010 Freescale Semiconductor 4b8b572e1SStephen Rothwell * 5b8b572e1SStephen Rothwell * Authors: Nick Spence <nick.spence@freescale.com>, 6b8b572e1SStephen Rothwell * Scott Wood <scottwood@freescale.com> 73ab8f2a2SRoy Zang * Jack Lan <jack.lan@freescale.com> 8b8b572e1SStephen Rothwell * 9b8b572e1SStephen Rothwell * This program is free software; you can redistribute it and/or modify 10b8b572e1SStephen Rothwell * it under the terms of the GNU General Public License as published by 11b8b572e1SStephen Rothwell * the Free Software Foundation; either version 2 of the License, or 12b8b572e1SStephen Rothwell * (at your option) any later version. 13b8b572e1SStephen Rothwell * 14b8b572e1SStephen Rothwell * This program is distributed in the hope that it will be useful, 15b8b572e1SStephen Rothwell * but WITHOUT ANY WARRANTY; without even the implied warranty of 16b8b572e1SStephen Rothwell * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17b8b572e1SStephen Rothwell * GNU General Public License for more details. 18b8b572e1SStephen Rothwell * 19b8b572e1SStephen Rothwell * You should have received a copy of the GNU General Public License 20b8b572e1SStephen Rothwell * along with this program; if not, write to the Free Software 21b8b572e1SStephen Rothwell * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22b8b572e1SStephen Rothwell */ 23b8b572e1SStephen Rothwell 24b8b572e1SStephen Rothwell #ifndef __ASM_FSL_LBC_H 25b8b572e1SStephen Rothwell #define __ASM_FSL_LBC_H 26b8b572e1SStephen Rothwell 27c0da99d5SAnton Vorontsov #include <linux/compiler.h> 28b8b572e1SStephen Rothwell #include <linux/types.h> 29c0da99d5SAnton Vorontsov #include <linux/io.h> 303ab8f2a2SRoy Zang #include <linux/device.h> 313ab8f2a2SRoy Zang #include <linux/spinlock.h> 32b8b572e1SStephen Rothwell 33b8b572e1SStephen Rothwell struct fsl_lbc_bank { 34b8b572e1SStephen Rothwell __be32 br; /**< Base Register */ 35b8b572e1SStephen Rothwell #define BR_BA 0xFFFF8000 36b8b572e1SStephen Rothwell #define BR_BA_SHIFT 15 37b8b572e1SStephen Rothwell #define BR_PS 0x00001800 38b8b572e1SStephen Rothwell #define BR_PS_SHIFT 11 39b8b572e1SStephen Rothwell #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 40b8b572e1SStephen Rothwell #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 41b8b572e1SStephen Rothwell #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 42b8b572e1SStephen Rothwell #define BR_DECC 0x00000600 43b8b572e1SStephen Rothwell #define BR_DECC_SHIFT 9 44b8b572e1SStephen Rothwell #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */ 45b8b572e1SStephen Rothwell #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */ 46b8b572e1SStephen Rothwell #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */ 47b8b572e1SStephen Rothwell #define BR_WP 0x00000100 48b8b572e1SStephen Rothwell #define BR_WP_SHIFT 8 49b8b572e1SStephen Rothwell #define BR_MSEL 0x000000E0 50b8b572e1SStephen Rothwell #define BR_MSEL_SHIFT 5 51b8b572e1SStephen Rothwell #define BR_MS_GPCM 0x00000000 /* GPCM */ 52b8b572e1SStephen Rothwell #define BR_MS_FCM 0x00000020 /* FCM */ 53b8b572e1SStephen Rothwell #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 54b8b572e1SStephen Rothwell #define BR_MS_UPMA 0x00000080 /* UPMA */ 55b8b572e1SStephen Rothwell #define BR_MS_UPMB 0x000000A0 /* UPMB */ 56b8b572e1SStephen Rothwell #define BR_MS_UPMC 0x000000C0 /* UPMC */ 57b8b572e1SStephen Rothwell #define BR_V 0x00000001 58b8b572e1SStephen Rothwell #define BR_V_SHIFT 0 59b8b572e1SStephen Rothwell #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) 60b8b572e1SStephen Rothwell 61b8b572e1SStephen Rothwell __be32 or; /**< Base Register */ 62b8b572e1SStephen Rothwell #define OR0 0x5004 63b8b572e1SStephen Rothwell #define OR1 0x500C 64b8b572e1SStephen Rothwell #define OR2 0x5014 65b8b572e1SStephen Rothwell #define OR3 0x501C 66b8b572e1SStephen Rothwell #define OR4 0x5024 67b8b572e1SStephen Rothwell #define OR5 0x502C 68b8b572e1SStephen Rothwell #define OR6 0x5034 69b8b572e1SStephen Rothwell #define OR7 0x503C 70b8b572e1SStephen Rothwell 71b8b572e1SStephen Rothwell #define OR_FCM_AM 0xFFFF8000 72b8b572e1SStephen Rothwell #define OR_FCM_AM_SHIFT 15 73b8b572e1SStephen Rothwell #define OR_FCM_BCTLD 0x00001000 74b8b572e1SStephen Rothwell #define OR_FCM_BCTLD_SHIFT 12 75b8b572e1SStephen Rothwell #define OR_FCM_PGS 0x00000400 76b8b572e1SStephen Rothwell #define OR_FCM_PGS_SHIFT 10 77b8b572e1SStephen Rothwell #define OR_FCM_CSCT 0x00000200 78b8b572e1SStephen Rothwell #define OR_FCM_CSCT_SHIFT 9 79b8b572e1SStephen Rothwell #define OR_FCM_CST 0x00000100 80b8b572e1SStephen Rothwell #define OR_FCM_CST_SHIFT 8 81b8b572e1SStephen Rothwell #define OR_FCM_CHT 0x00000080 82b8b572e1SStephen Rothwell #define OR_FCM_CHT_SHIFT 7 83b8b572e1SStephen Rothwell #define OR_FCM_SCY 0x00000070 84b8b572e1SStephen Rothwell #define OR_FCM_SCY_SHIFT 4 85b8b572e1SStephen Rothwell #define OR_FCM_SCY_1 0x00000010 86b8b572e1SStephen Rothwell #define OR_FCM_SCY_2 0x00000020 87b8b572e1SStephen Rothwell #define OR_FCM_SCY_3 0x00000030 88b8b572e1SStephen Rothwell #define OR_FCM_SCY_4 0x00000040 89b8b572e1SStephen Rothwell #define OR_FCM_SCY_5 0x00000050 90b8b572e1SStephen Rothwell #define OR_FCM_SCY_6 0x00000060 91b8b572e1SStephen Rothwell #define OR_FCM_SCY_7 0x00000070 92b8b572e1SStephen Rothwell #define OR_FCM_RST 0x00000008 93b8b572e1SStephen Rothwell #define OR_FCM_RST_SHIFT 3 94b8b572e1SStephen Rothwell #define OR_FCM_TRLX 0x00000004 95b8b572e1SStephen Rothwell #define OR_FCM_TRLX_SHIFT 2 96b8b572e1SStephen Rothwell #define OR_FCM_EHTR 0x00000002 97b8b572e1SStephen Rothwell #define OR_FCM_EHTR_SHIFT 1 98*fbc4a8a8SJohn Ogness 99*fbc4a8a8SJohn Ogness #define OR_GPCM_AM 0xFFFF8000 100*fbc4a8a8SJohn Ogness #define OR_GPCM_AM_SHIFT 15 101b8b572e1SStephen Rothwell }; 102b8b572e1SStephen Rothwell 103b8b572e1SStephen Rothwell struct fsl_lbc_regs { 104e86b4998Smware@internode.on.net struct fsl_lbc_bank bank[12]; 105e86b4998Smware@internode.on.net u8 res0[0x8]; 106b8b572e1SStephen Rothwell __be32 mar; /**< UPM Address Register */ 107b8b572e1SStephen Rothwell u8 res1[0x4]; 108b8b572e1SStephen Rothwell __be32 mamr; /**< UPMA Mode Register */ 109b8b572e1SStephen Rothwell #define MxMR_OP_NO (0 << 28) /**< normal operation */ 110b8b572e1SStephen Rothwell #define MxMR_OP_WA (1 << 28) /**< write array */ 111b8b572e1SStephen Rothwell #define MxMR_OP_RA (2 << 28) /**< read array */ 112b8b572e1SStephen Rothwell #define MxMR_OP_RP (3 << 28) /**< run pattern */ 113b8b572e1SStephen Rothwell #define MxMR_MAD 0x3f /**< machine address */ 114b8b572e1SStephen Rothwell __be32 mbmr; /**< UPMB Mode Register */ 115b8b572e1SStephen Rothwell __be32 mcmr; /**< UPMC Mode Register */ 116b8b572e1SStephen Rothwell u8 res2[0x8]; 117b8b572e1SStephen Rothwell __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ 118b8b572e1SStephen Rothwell __be32 mdr; /**< UPM Data Register */ 119b8b572e1SStephen Rothwell u8 res3[0x4]; 120b8b572e1SStephen Rothwell __be32 lsor; /**< Special Operation Initiation Register */ 121b8b572e1SStephen Rothwell __be32 lsdmr; /**< SDRAM Mode Register */ 122b8b572e1SStephen Rothwell u8 res4[0x8]; 123b8b572e1SStephen Rothwell __be32 lurt; /**< UPM Refresh Timer */ 124b8b572e1SStephen Rothwell __be32 lsrt; /**< SDRAM Refresh Timer */ 125b8b572e1SStephen Rothwell u8 res5[0x8]; 126b8b572e1SStephen Rothwell __be32 ltesr; /**< Transfer Error Status Register */ 127b8b572e1SStephen Rothwell #define LTESR_BM 0x80000000 128b8b572e1SStephen Rothwell #define LTESR_FCT 0x40000000 129b8b572e1SStephen Rothwell #define LTESR_PAR 0x20000000 130b8b572e1SStephen Rothwell #define LTESR_WP 0x04000000 131b8b572e1SStephen Rothwell #define LTESR_ATMW 0x00800000 132b8b572e1SStephen Rothwell #define LTESR_ATMR 0x00400000 133b8b572e1SStephen Rothwell #define LTESR_CS 0x00080000 1343ab8f2a2SRoy Zang #define LTESR_UPM 0x00000002 135b8b572e1SStephen Rothwell #define LTESR_CC 0x00000001 136b8b572e1SStephen Rothwell #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) 1373ab8f2a2SRoy Zang #define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \ 1383ab8f2a2SRoy Zang | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \ 1393ab8f2a2SRoy Zang | LTESR_CC) 1403ab8f2a2SRoy Zang #define LTESR_CLEAR 0xFFFFFFFF 1413ab8f2a2SRoy Zang #define LTECCR_CLEAR 0xFFFFFFFF 1423ab8f2a2SRoy Zang #define LTESR_STATUS LTESR_MASK 1433ab8f2a2SRoy Zang #define LTEIR_ENABLE LTESR_MASK 1443ab8f2a2SRoy Zang #define LTEDR_ENABLE 0x00000000 145b8b572e1SStephen Rothwell __be32 ltedr; /**< Transfer Error Disable Register */ 146b8b572e1SStephen Rothwell __be32 lteir; /**< Transfer Error Interrupt Register */ 147b8b572e1SStephen Rothwell __be32 lteatr; /**< Transfer Error Attributes Register */ 148b8b572e1SStephen Rothwell __be32 ltear; /**< Transfer Error Address Register */ 1493ab8f2a2SRoy Zang __be32 lteccr; /**< Transfer Error ECC Register */ 1503ab8f2a2SRoy Zang u8 res6[0x8]; 151b8b572e1SStephen Rothwell __be32 lbcr; /**< Configuration Register */ 152b8b572e1SStephen Rothwell #define LBCR_LDIS 0x80000000 153b8b572e1SStephen Rothwell #define LBCR_LDIS_SHIFT 31 154b8b572e1SStephen Rothwell #define LBCR_BCTLC 0x00C00000 155b8b572e1SStephen Rothwell #define LBCR_BCTLC_SHIFT 22 156b8b572e1SStephen Rothwell #define LBCR_AHD 0x00200000 157b8b572e1SStephen Rothwell #define LBCR_LPBSE 0x00020000 158b8b572e1SStephen Rothwell #define LBCR_LPBSE_SHIFT 17 159b8b572e1SStephen Rothwell #define LBCR_EPAR 0x00010000 160b8b572e1SStephen Rothwell #define LBCR_EPAR_SHIFT 16 161b8b572e1SStephen Rothwell #define LBCR_BMT 0x0000FF00 162b8b572e1SStephen Rothwell #define LBCR_BMT_SHIFT 8 163d08e4457SShengzhou Liu #define LBCR_BMTPS 0x0000000F 164d08e4457SShengzhou Liu #define LBCR_BMTPS_SHIFT 0 165b8b572e1SStephen Rothwell #define LBCR_INIT 0x00040000 166b8b572e1SStephen Rothwell __be32 lcrr; /**< Clock Ratio Register */ 167b8b572e1SStephen Rothwell #define LCRR_DBYP 0x80000000 168b8b572e1SStephen Rothwell #define LCRR_DBYP_SHIFT 31 169b8b572e1SStephen Rothwell #define LCRR_BUFCMDC 0x30000000 170b8b572e1SStephen Rothwell #define LCRR_BUFCMDC_SHIFT 28 171b8b572e1SStephen Rothwell #define LCRR_ECL 0x03000000 172b8b572e1SStephen Rothwell #define LCRR_ECL_SHIFT 24 173b8b572e1SStephen Rothwell #define LCRR_EADC 0x00030000 174b8b572e1SStephen Rothwell #define LCRR_EADC_SHIFT 16 175b8b572e1SStephen Rothwell #define LCRR_CLKDIV 0x0000000F 176b8b572e1SStephen Rothwell #define LCRR_CLKDIV_SHIFT 0 177b8b572e1SStephen Rothwell u8 res7[0x8]; 178b8b572e1SStephen Rothwell __be32 fmr; /**< Flash Mode Register */ 179b8b572e1SStephen Rothwell #define FMR_CWTO 0x0000F000 180b8b572e1SStephen Rothwell #define FMR_CWTO_SHIFT 12 181b8b572e1SStephen Rothwell #define FMR_BOOT 0x00000800 182b8b572e1SStephen Rothwell #define FMR_ECCM 0x00000100 183b8b572e1SStephen Rothwell #define FMR_AL 0x00000030 184b8b572e1SStephen Rothwell #define FMR_AL_SHIFT 4 185b8b572e1SStephen Rothwell #define FMR_OP 0x00000003 186b8b572e1SStephen Rothwell #define FMR_OP_SHIFT 0 187b8b572e1SStephen Rothwell __be32 fir; /**< Flash Instruction Register */ 188b8b572e1SStephen Rothwell #define FIR_OP0 0xF0000000 189b8b572e1SStephen Rothwell #define FIR_OP0_SHIFT 28 190b8b572e1SStephen Rothwell #define FIR_OP1 0x0F000000 191b8b572e1SStephen Rothwell #define FIR_OP1_SHIFT 24 192b8b572e1SStephen Rothwell #define FIR_OP2 0x00F00000 193b8b572e1SStephen Rothwell #define FIR_OP2_SHIFT 20 194b8b572e1SStephen Rothwell #define FIR_OP3 0x000F0000 195b8b572e1SStephen Rothwell #define FIR_OP3_SHIFT 16 196b8b572e1SStephen Rothwell #define FIR_OP4 0x0000F000 197b8b572e1SStephen Rothwell #define FIR_OP4_SHIFT 12 198b8b572e1SStephen Rothwell #define FIR_OP5 0x00000F00 199b8b572e1SStephen Rothwell #define FIR_OP5_SHIFT 8 200b8b572e1SStephen Rothwell #define FIR_OP6 0x000000F0 201b8b572e1SStephen Rothwell #define FIR_OP6_SHIFT 4 202b8b572e1SStephen Rothwell #define FIR_OP7 0x0000000F 203b8b572e1SStephen Rothwell #define FIR_OP7_SHIFT 0 204b8b572e1SStephen Rothwell #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 205b8b572e1SStephen Rothwell #define FIR_OP_CA 0x1 /* Issue current column address */ 206b8b572e1SStephen Rothwell #define FIR_OP_PA 0x2 /* Issue current block+page address */ 207b8b572e1SStephen Rothwell #define FIR_OP_UA 0x3 /* Issue user defined address */ 208b8b572e1SStephen Rothwell #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 209b8b572e1SStephen Rothwell #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 210b8b572e1SStephen Rothwell #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 211b8b572e1SStephen Rothwell #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 212b8b572e1SStephen Rothwell #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 213b8b572e1SStephen Rothwell #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 214b8b572e1SStephen Rothwell #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 215b8b572e1SStephen Rothwell #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 216b8b572e1SStephen Rothwell #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 217b8b572e1SStephen Rothwell #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 218b8b572e1SStephen Rothwell #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 219b8b572e1SStephen Rothwell #define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */ 220b8b572e1SStephen Rothwell __be32 fcr; /**< Flash Command Register */ 221b8b572e1SStephen Rothwell #define FCR_CMD0 0xFF000000 222b8b572e1SStephen Rothwell #define FCR_CMD0_SHIFT 24 223b8b572e1SStephen Rothwell #define FCR_CMD1 0x00FF0000 224b8b572e1SStephen Rothwell #define FCR_CMD1_SHIFT 16 225b8b572e1SStephen Rothwell #define FCR_CMD2 0x0000FF00 226b8b572e1SStephen Rothwell #define FCR_CMD2_SHIFT 8 227b8b572e1SStephen Rothwell #define FCR_CMD3 0x000000FF 228b8b572e1SStephen Rothwell #define FCR_CMD3_SHIFT 0 229b8b572e1SStephen Rothwell __be32 fbar; /**< Flash Block Address Register */ 230b8b572e1SStephen Rothwell #define FBAR_BLK 0x00FFFFFF 231b8b572e1SStephen Rothwell __be32 fpar; /**< Flash Page Address Register */ 232b8b572e1SStephen Rothwell #define FPAR_SP_PI 0x00007C00 233b8b572e1SStephen Rothwell #define FPAR_SP_PI_SHIFT 10 234b8b572e1SStephen Rothwell #define FPAR_SP_MS 0x00000200 235b8b572e1SStephen Rothwell #define FPAR_SP_CI 0x000001FF 236b8b572e1SStephen Rothwell #define FPAR_SP_CI_SHIFT 0 237b8b572e1SStephen Rothwell #define FPAR_LP_PI 0x0003F000 238b8b572e1SStephen Rothwell #define FPAR_LP_PI_SHIFT 12 239b8b572e1SStephen Rothwell #define FPAR_LP_MS 0x00000800 240b8b572e1SStephen Rothwell #define FPAR_LP_CI 0x000007FF 241b8b572e1SStephen Rothwell #define FPAR_LP_CI_SHIFT 0 242b8b572e1SStephen Rothwell __be32 fbcr; /**< Flash Byte Count Register */ 243b8b572e1SStephen Rothwell #define FBCR_BC 0x00000FFF 244b8b572e1SStephen Rothwell }; 245b8b572e1SStephen Rothwell 246b8b572e1SStephen Rothwell /* 247b8b572e1SStephen Rothwell * FSL UPM routines 248b8b572e1SStephen Rothwell */ 249b8b572e1SStephen Rothwell struct fsl_upm { 250b8b572e1SStephen Rothwell __be32 __iomem *mxmr; 251b8b572e1SStephen Rothwell int width; 252b8b572e1SStephen Rothwell }; 253b8b572e1SStephen Rothwell 2540b824d2bSLan Chunhe-B25806 extern u32 fsl_lbc_addr(phys_addr_t addr_base); 255b8b572e1SStephen Rothwell extern int fsl_lbc_find(phys_addr_t addr_base); 256b8b572e1SStephen Rothwell extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm); 257b8b572e1SStephen Rothwell 258b8b572e1SStephen Rothwell /** 259b8b572e1SStephen Rothwell * fsl_upm_start_pattern - start UPM patterns execution 260b8b572e1SStephen Rothwell * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find 261b8b572e1SStephen Rothwell * @pat_offset: UPM pattern offset for the command to be executed 262b8b572e1SStephen Rothwell * 263b8b572e1SStephen Rothwell * This routine programmes UPM so the next memory access that hits an UPM 264b8b572e1SStephen Rothwell * will trigger pattern execution, starting at pat_offset. 265b8b572e1SStephen Rothwell */ 266b8b572e1SStephen Rothwell static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset) 267b8b572e1SStephen Rothwell { 268b8b572e1SStephen Rothwell clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); 269b8b572e1SStephen Rothwell } 270b8b572e1SStephen Rothwell 271b8b572e1SStephen Rothwell /** 272b8b572e1SStephen Rothwell * fsl_upm_end_pattern - end UPM patterns execution 273b8b572e1SStephen Rothwell * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find 274b8b572e1SStephen Rothwell * 275b8b572e1SStephen Rothwell * This routine reverts UPM to normal operation mode. 276b8b572e1SStephen Rothwell */ 277b8b572e1SStephen Rothwell static inline void fsl_upm_end_pattern(struct fsl_upm *upm) 278b8b572e1SStephen Rothwell { 279b8b572e1SStephen Rothwell clrbits32(upm->mxmr, MxMR_OP_RP); 280b8b572e1SStephen Rothwell 281b8b572e1SStephen Rothwell while (in_be32(upm->mxmr) & MxMR_OP_RP) 282b8b572e1SStephen Rothwell cpu_relax(); 283b8b572e1SStephen Rothwell } 284b8b572e1SStephen Rothwell 2853ab8f2a2SRoy Zang /* overview of the fsl lbc controller */ 2863ab8f2a2SRoy Zang 2873ab8f2a2SRoy Zang struct fsl_lbc_ctrl { 2883ab8f2a2SRoy Zang /* device info */ 2893ab8f2a2SRoy Zang struct device *dev; 2903ab8f2a2SRoy Zang struct fsl_lbc_regs __iomem *regs; 291a655f724SShaohui Xie int irq[2]; 2923ab8f2a2SRoy Zang wait_queue_head_t irq_wait; 2933ab8f2a2SRoy Zang spinlock_t lock; 2943ab8f2a2SRoy Zang void *nand; 2953ab8f2a2SRoy Zang 2963ab8f2a2SRoy Zang /* status read from LTESR by irq handler */ 2973ab8f2a2SRoy Zang unsigned int irq_status; 29809cef8bdSJia Hongtao 29909cef8bdSJia Hongtao #ifdef CONFIG_SUSPEND 30009cef8bdSJia Hongtao /* save regs when system go to deep-sleep */ 30109cef8bdSJia Hongtao struct fsl_lbc_regs *saved_regs; 30209cef8bdSJia Hongtao #endif 3033ab8f2a2SRoy Zang }; 3043ab8f2a2SRoy Zang 305c0da99d5SAnton Vorontsov extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, 306c0da99d5SAnton Vorontsov u32 mar); 3073ab8f2a2SRoy Zang extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev; 308b8b572e1SStephen Rothwell 309b8b572e1SStephen Rothwell #endif /* __ASM_FSL_LBC_H */ 310