1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2b8b572e1SStephen Rothwell /* Freescale Local Bus Controller 3b8b572e1SStephen Rothwell * 43ab8f2a2SRoy Zang * Copyright © 2006-2007, 2010 Freescale Semiconductor 5b8b572e1SStephen Rothwell * 6b8b572e1SStephen Rothwell * Authors: Nick Spence <nick.spence@freescale.com>, 7b8b572e1SStephen Rothwell * Scott Wood <scottwood@freescale.com> 83ab8f2a2SRoy Zang * Jack Lan <jack.lan@freescale.com> 9b8b572e1SStephen Rothwell */ 10b8b572e1SStephen Rothwell 11b8b572e1SStephen Rothwell #ifndef __ASM_FSL_LBC_H 12b8b572e1SStephen Rothwell #define __ASM_FSL_LBC_H 13b8b572e1SStephen Rothwell 14c0da99d5SAnton Vorontsov #include <linux/compiler.h> 15b8b572e1SStephen Rothwell #include <linux/types.h> 16c0da99d5SAnton Vorontsov #include <linux/io.h> 173ab8f2a2SRoy Zang #include <linux/device.h> 183ab8f2a2SRoy Zang #include <linux/spinlock.h> 19b8b572e1SStephen Rothwell 20b8b572e1SStephen Rothwell struct fsl_lbc_bank { 21b8b572e1SStephen Rothwell __be32 br; /**< Base Register */ 22b8b572e1SStephen Rothwell #define BR_BA 0xFFFF8000 23b8b572e1SStephen Rothwell #define BR_BA_SHIFT 15 24b8b572e1SStephen Rothwell #define BR_PS 0x00001800 25b8b572e1SStephen Rothwell #define BR_PS_SHIFT 11 26b8b572e1SStephen Rothwell #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 27b8b572e1SStephen Rothwell #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 28b8b572e1SStephen Rothwell #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 29b8b572e1SStephen Rothwell #define BR_DECC 0x00000600 30b8b572e1SStephen Rothwell #define BR_DECC_SHIFT 9 31b8b572e1SStephen Rothwell #define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */ 32b8b572e1SStephen Rothwell #define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */ 33b8b572e1SStephen Rothwell #define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */ 34b8b572e1SStephen Rothwell #define BR_WP 0x00000100 35b8b572e1SStephen Rothwell #define BR_WP_SHIFT 8 36b8b572e1SStephen Rothwell #define BR_MSEL 0x000000E0 37b8b572e1SStephen Rothwell #define BR_MSEL_SHIFT 5 38b8b572e1SStephen Rothwell #define BR_MS_GPCM 0x00000000 /* GPCM */ 39b8b572e1SStephen Rothwell #define BR_MS_FCM 0x00000020 /* FCM */ 40b8b572e1SStephen Rothwell #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 41b8b572e1SStephen Rothwell #define BR_MS_UPMA 0x00000080 /* UPMA */ 42b8b572e1SStephen Rothwell #define BR_MS_UPMB 0x000000A0 /* UPMB */ 43b8b572e1SStephen Rothwell #define BR_MS_UPMC 0x000000C0 /* UPMC */ 44b8b572e1SStephen Rothwell #define BR_V 0x00000001 45b8b572e1SStephen Rothwell #define BR_V_SHIFT 0 46b8b572e1SStephen Rothwell #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) 47b8b572e1SStephen Rothwell 48b8b572e1SStephen Rothwell __be32 or; /**< Base Register */ 49b8b572e1SStephen Rothwell #define OR0 0x5004 50b8b572e1SStephen Rothwell #define OR1 0x500C 51b8b572e1SStephen Rothwell #define OR2 0x5014 52b8b572e1SStephen Rothwell #define OR3 0x501C 53b8b572e1SStephen Rothwell #define OR4 0x5024 54b8b572e1SStephen Rothwell #define OR5 0x502C 55b8b572e1SStephen Rothwell #define OR6 0x5034 56b8b572e1SStephen Rothwell #define OR7 0x503C 57b8b572e1SStephen Rothwell 58b8b572e1SStephen Rothwell #define OR_FCM_AM 0xFFFF8000 59b8b572e1SStephen Rothwell #define OR_FCM_AM_SHIFT 15 60b8b572e1SStephen Rothwell #define OR_FCM_BCTLD 0x00001000 61b8b572e1SStephen Rothwell #define OR_FCM_BCTLD_SHIFT 12 62b8b572e1SStephen Rothwell #define OR_FCM_PGS 0x00000400 63b8b572e1SStephen Rothwell #define OR_FCM_PGS_SHIFT 10 64b8b572e1SStephen Rothwell #define OR_FCM_CSCT 0x00000200 65b8b572e1SStephen Rothwell #define OR_FCM_CSCT_SHIFT 9 66b8b572e1SStephen Rothwell #define OR_FCM_CST 0x00000100 67b8b572e1SStephen Rothwell #define OR_FCM_CST_SHIFT 8 68b8b572e1SStephen Rothwell #define OR_FCM_CHT 0x00000080 69b8b572e1SStephen Rothwell #define OR_FCM_CHT_SHIFT 7 70b8b572e1SStephen Rothwell #define OR_FCM_SCY 0x00000070 71b8b572e1SStephen Rothwell #define OR_FCM_SCY_SHIFT 4 72b8b572e1SStephen Rothwell #define OR_FCM_SCY_1 0x00000010 73b8b572e1SStephen Rothwell #define OR_FCM_SCY_2 0x00000020 74b8b572e1SStephen Rothwell #define OR_FCM_SCY_3 0x00000030 75b8b572e1SStephen Rothwell #define OR_FCM_SCY_4 0x00000040 76b8b572e1SStephen Rothwell #define OR_FCM_SCY_5 0x00000050 77b8b572e1SStephen Rothwell #define OR_FCM_SCY_6 0x00000060 78b8b572e1SStephen Rothwell #define OR_FCM_SCY_7 0x00000070 79b8b572e1SStephen Rothwell #define OR_FCM_RST 0x00000008 80b8b572e1SStephen Rothwell #define OR_FCM_RST_SHIFT 3 81b8b572e1SStephen Rothwell #define OR_FCM_TRLX 0x00000004 82b8b572e1SStephen Rothwell #define OR_FCM_TRLX_SHIFT 2 83b8b572e1SStephen Rothwell #define OR_FCM_EHTR 0x00000002 84b8b572e1SStephen Rothwell #define OR_FCM_EHTR_SHIFT 1 85fbc4a8a8SJohn Ogness 86fbc4a8a8SJohn Ogness #define OR_GPCM_AM 0xFFFF8000 87fbc4a8a8SJohn Ogness #define OR_GPCM_AM_SHIFT 15 88b8b572e1SStephen Rothwell }; 89b8b572e1SStephen Rothwell 90b8b572e1SStephen Rothwell struct fsl_lbc_regs { 91e86b4998Smware@internode.on.net struct fsl_lbc_bank bank[12]; 92e86b4998Smware@internode.on.net u8 res0[0x8]; 93b8b572e1SStephen Rothwell __be32 mar; /**< UPM Address Register */ 94b8b572e1SStephen Rothwell u8 res1[0x4]; 95b8b572e1SStephen Rothwell __be32 mamr; /**< UPMA Mode Register */ 96b8b572e1SStephen Rothwell #define MxMR_OP_NO (0 << 28) /**< normal operation */ 97b8b572e1SStephen Rothwell #define MxMR_OP_WA (1 << 28) /**< write array */ 98b8b572e1SStephen Rothwell #define MxMR_OP_RA (2 << 28) /**< read array */ 99b8b572e1SStephen Rothwell #define MxMR_OP_RP (3 << 28) /**< run pattern */ 100b8b572e1SStephen Rothwell #define MxMR_MAD 0x3f /**< machine address */ 101b8b572e1SStephen Rothwell __be32 mbmr; /**< UPMB Mode Register */ 102b8b572e1SStephen Rothwell __be32 mcmr; /**< UPMC Mode Register */ 103b8b572e1SStephen Rothwell u8 res2[0x8]; 104b8b572e1SStephen Rothwell __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ 105b8b572e1SStephen Rothwell __be32 mdr; /**< UPM Data Register */ 106b8b572e1SStephen Rothwell u8 res3[0x4]; 107b8b572e1SStephen Rothwell __be32 lsor; /**< Special Operation Initiation Register */ 108b8b572e1SStephen Rothwell __be32 lsdmr; /**< SDRAM Mode Register */ 109b8b572e1SStephen Rothwell u8 res4[0x8]; 110b8b572e1SStephen Rothwell __be32 lurt; /**< UPM Refresh Timer */ 111b8b572e1SStephen Rothwell __be32 lsrt; /**< SDRAM Refresh Timer */ 112b8b572e1SStephen Rothwell u8 res5[0x8]; 113b8b572e1SStephen Rothwell __be32 ltesr; /**< Transfer Error Status Register */ 114b8b572e1SStephen Rothwell #define LTESR_BM 0x80000000 115b8b572e1SStephen Rothwell #define LTESR_FCT 0x40000000 116b8b572e1SStephen Rothwell #define LTESR_PAR 0x20000000 117b8b572e1SStephen Rothwell #define LTESR_WP 0x04000000 118b8b572e1SStephen Rothwell #define LTESR_ATMW 0x00800000 119b8b572e1SStephen Rothwell #define LTESR_ATMR 0x00400000 120b8b572e1SStephen Rothwell #define LTESR_CS 0x00080000 1213ab8f2a2SRoy Zang #define LTESR_UPM 0x00000002 122b8b572e1SStephen Rothwell #define LTESR_CC 0x00000001 123b8b572e1SStephen Rothwell #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) 1243ab8f2a2SRoy Zang #define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \ 1253ab8f2a2SRoy Zang | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \ 1263ab8f2a2SRoy Zang | LTESR_CC) 1273ab8f2a2SRoy Zang #define LTESR_CLEAR 0xFFFFFFFF 1283ab8f2a2SRoy Zang #define LTECCR_CLEAR 0xFFFFFFFF 1293ab8f2a2SRoy Zang #define LTESR_STATUS LTESR_MASK 1303ab8f2a2SRoy Zang #define LTEIR_ENABLE LTESR_MASK 1313ab8f2a2SRoy Zang #define LTEDR_ENABLE 0x00000000 132b8b572e1SStephen Rothwell __be32 ltedr; /**< Transfer Error Disable Register */ 133b8b572e1SStephen Rothwell __be32 lteir; /**< Transfer Error Interrupt Register */ 134b8b572e1SStephen Rothwell __be32 lteatr; /**< Transfer Error Attributes Register */ 135b8b572e1SStephen Rothwell __be32 ltear; /**< Transfer Error Address Register */ 1363ab8f2a2SRoy Zang __be32 lteccr; /**< Transfer Error ECC Register */ 1373ab8f2a2SRoy Zang u8 res6[0x8]; 138b8b572e1SStephen Rothwell __be32 lbcr; /**< Configuration Register */ 139b8b572e1SStephen Rothwell #define LBCR_LDIS 0x80000000 140b8b572e1SStephen Rothwell #define LBCR_LDIS_SHIFT 31 141b8b572e1SStephen Rothwell #define LBCR_BCTLC 0x00C00000 142b8b572e1SStephen Rothwell #define LBCR_BCTLC_SHIFT 22 143b8b572e1SStephen Rothwell #define LBCR_AHD 0x00200000 144b8b572e1SStephen Rothwell #define LBCR_LPBSE 0x00020000 145b8b572e1SStephen Rothwell #define LBCR_LPBSE_SHIFT 17 146b8b572e1SStephen Rothwell #define LBCR_EPAR 0x00010000 147b8b572e1SStephen Rothwell #define LBCR_EPAR_SHIFT 16 148b8b572e1SStephen Rothwell #define LBCR_BMT 0x0000FF00 149b8b572e1SStephen Rothwell #define LBCR_BMT_SHIFT 8 150d08e4457SShengzhou Liu #define LBCR_BMTPS 0x0000000F 151d08e4457SShengzhou Liu #define LBCR_BMTPS_SHIFT 0 152b8b572e1SStephen Rothwell #define LBCR_INIT 0x00040000 153b8b572e1SStephen Rothwell __be32 lcrr; /**< Clock Ratio Register */ 154b8b572e1SStephen Rothwell #define LCRR_DBYP 0x80000000 155b8b572e1SStephen Rothwell #define LCRR_DBYP_SHIFT 31 156b8b572e1SStephen Rothwell #define LCRR_BUFCMDC 0x30000000 157b8b572e1SStephen Rothwell #define LCRR_BUFCMDC_SHIFT 28 158b8b572e1SStephen Rothwell #define LCRR_ECL 0x03000000 159b8b572e1SStephen Rothwell #define LCRR_ECL_SHIFT 24 160b8b572e1SStephen Rothwell #define LCRR_EADC 0x00030000 161b8b572e1SStephen Rothwell #define LCRR_EADC_SHIFT 16 162b8b572e1SStephen Rothwell #define LCRR_CLKDIV 0x0000000F 163b8b572e1SStephen Rothwell #define LCRR_CLKDIV_SHIFT 0 164b8b572e1SStephen Rothwell u8 res7[0x8]; 165b8b572e1SStephen Rothwell __be32 fmr; /**< Flash Mode Register */ 166b8b572e1SStephen Rothwell #define FMR_CWTO 0x0000F000 167b8b572e1SStephen Rothwell #define FMR_CWTO_SHIFT 12 168b8b572e1SStephen Rothwell #define FMR_BOOT 0x00000800 169b8b572e1SStephen Rothwell #define FMR_ECCM 0x00000100 170b8b572e1SStephen Rothwell #define FMR_AL 0x00000030 171b8b572e1SStephen Rothwell #define FMR_AL_SHIFT 4 172b8b572e1SStephen Rothwell #define FMR_OP 0x00000003 173b8b572e1SStephen Rothwell #define FMR_OP_SHIFT 0 174b8b572e1SStephen Rothwell __be32 fir; /**< Flash Instruction Register */ 175b8b572e1SStephen Rothwell #define FIR_OP0 0xF0000000 176b8b572e1SStephen Rothwell #define FIR_OP0_SHIFT 28 177b8b572e1SStephen Rothwell #define FIR_OP1 0x0F000000 178b8b572e1SStephen Rothwell #define FIR_OP1_SHIFT 24 179b8b572e1SStephen Rothwell #define FIR_OP2 0x00F00000 180b8b572e1SStephen Rothwell #define FIR_OP2_SHIFT 20 181b8b572e1SStephen Rothwell #define FIR_OP3 0x000F0000 182b8b572e1SStephen Rothwell #define FIR_OP3_SHIFT 16 183b8b572e1SStephen Rothwell #define FIR_OP4 0x0000F000 184b8b572e1SStephen Rothwell #define FIR_OP4_SHIFT 12 185b8b572e1SStephen Rothwell #define FIR_OP5 0x00000F00 186b8b572e1SStephen Rothwell #define FIR_OP5_SHIFT 8 187b8b572e1SStephen Rothwell #define FIR_OP6 0x000000F0 188b8b572e1SStephen Rothwell #define FIR_OP6_SHIFT 4 189b8b572e1SStephen Rothwell #define FIR_OP7 0x0000000F 190b8b572e1SStephen Rothwell #define FIR_OP7_SHIFT 0 191b8b572e1SStephen Rothwell #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 192b8b572e1SStephen Rothwell #define FIR_OP_CA 0x1 /* Issue current column address */ 193b8b572e1SStephen Rothwell #define FIR_OP_PA 0x2 /* Issue current block+page address */ 194b8b572e1SStephen Rothwell #define FIR_OP_UA 0x3 /* Issue user defined address */ 195b8b572e1SStephen Rothwell #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 196b8b572e1SStephen Rothwell #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 197b8b572e1SStephen Rothwell #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 198b8b572e1SStephen Rothwell #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 199b8b572e1SStephen Rothwell #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 200b8b572e1SStephen Rothwell #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 201b8b572e1SStephen Rothwell #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 202b8b572e1SStephen Rothwell #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 203b8b572e1SStephen Rothwell #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 204b8b572e1SStephen Rothwell #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 205b8b572e1SStephen Rothwell #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 206b8b572e1SStephen Rothwell #define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */ 207b8b572e1SStephen Rothwell __be32 fcr; /**< Flash Command Register */ 208b8b572e1SStephen Rothwell #define FCR_CMD0 0xFF000000 209b8b572e1SStephen Rothwell #define FCR_CMD0_SHIFT 24 210b8b572e1SStephen Rothwell #define FCR_CMD1 0x00FF0000 211b8b572e1SStephen Rothwell #define FCR_CMD1_SHIFT 16 212b8b572e1SStephen Rothwell #define FCR_CMD2 0x0000FF00 213b8b572e1SStephen Rothwell #define FCR_CMD2_SHIFT 8 214b8b572e1SStephen Rothwell #define FCR_CMD3 0x000000FF 215b8b572e1SStephen Rothwell #define FCR_CMD3_SHIFT 0 216b8b572e1SStephen Rothwell __be32 fbar; /**< Flash Block Address Register */ 217b8b572e1SStephen Rothwell #define FBAR_BLK 0x00FFFFFF 218b8b572e1SStephen Rothwell __be32 fpar; /**< Flash Page Address Register */ 219b8b572e1SStephen Rothwell #define FPAR_SP_PI 0x00007C00 220b8b572e1SStephen Rothwell #define FPAR_SP_PI_SHIFT 10 221b8b572e1SStephen Rothwell #define FPAR_SP_MS 0x00000200 222b8b572e1SStephen Rothwell #define FPAR_SP_CI 0x000001FF 223b8b572e1SStephen Rothwell #define FPAR_SP_CI_SHIFT 0 224b8b572e1SStephen Rothwell #define FPAR_LP_PI 0x0003F000 225b8b572e1SStephen Rothwell #define FPAR_LP_PI_SHIFT 12 226b8b572e1SStephen Rothwell #define FPAR_LP_MS 0x00000800 227b8b572e1SStephen Rothwell #define FPAR_LP_CI 0x000007FF 228b8b572e1SStephen Rothwell #define FPAR_LP_CI_SHIFT 0 229b8b572e1SStephen Rothwell __be32 fbcr; /**< Flash Byte Count Register */ 230b8b572e1SStephen Rothwell #define FBCR_BC 0x00000FFF 231b8b572e1SStephen Rothwell }; 232b8b572e1SStephen Rothwell 233b8b572e1SStephen Rothwell /* 234b8b572e1SStephen Rothwell * FSL UPM routines 235b8b572e1SStephen Rothwell */ 236b8b572e1SStephen Rothwell struct fsl_upm { 237b8b572e1SStephen Rothwell __be32 __iomem *mxmr; 238b8b572e1SStephen Rothwell int width; 239b8b572e1SStephen Rothwell }; 240b8b572e1SStephen Rothwell 2410b824d2bSLan Chunhe-B25806 extern u32 fsl_lbc_addr(phys_addr_t addr_base); 242b8b572e1SStephen Rothwell extern int fsl_lbc_find(phys_addr_t addr_base); 243b8b572e1SStephen Rothwell extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm); 244b8b572e1SStephen Rothwell 245b8b572e1SStephen Rothwell /** 246b8b572e1SStephen Rothwell * fsl_upm_start_pattern - start UPM patterns execution 247b8b572e1SStephen Rothwell * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find 248b8b572e1SStephen Rothwell * @pat_offset: UPM pattern offset for the command to be executed 249b8b572e1SStephen Rothwell * 250b8b572e1SStephen Rothwell * This routine programmes UPM so the next memory access that hits an UPM 251b8b572e1SStephen Rothwell * will trigger pattern execution, starting at pat_offset. 252b8b572e1SStephen Rothwell */ 253b8b572e1SStephen Rothwell static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset) 254b8b572e1SStephen Rothwell { 255b8b572e1SStephen Rothwell clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); 256b8b572e1SStephen Rothwell } 257b8b572e1SStephen Rothwell 258b8b572e1SStephen Rothwell /** 259b8b572e1SStephen Rothwell * fsl_upm_end_pattern - end UPM patterns execution 260b8b572e1SStephen Rothwell * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find 261b8b572e1SStephen Rothwell * 262b8b572e1SStephen Rothwell * This routine reverts UPM to normal operation mode. 263b8b572e1SStephen Rothwell */ 264b8b572e1SStephen Rothwell static inline void fsl_upm_end_pattern(struct fsl_upm *upm) 265b8b572e1SStephen Rothwell { 266b8b572e1SStephen Rothwell clrbits32(upm->mxmr, MxMR_OP_RP); 267b8b572e1SStephen Rothwell 268b8b572e1SStephen Rothwell while (in_be32(upm->mxmr) & MxMR_OP_RP) 269b8b572e1SStephen Rothwell cpu_relax(); 270b8b572e1SStephen Rothwell } 271b8b572e1SStephen Rothwell 2723ab8f2a2SRoy Zang /* overview of the fsl lbc controller */ 2733ab8f2a2SRoy Zang 2743ab8f2a2SRoy Zang struct fsl_lbc_ctrl { 2753ab8f2a2SRoy Zang /* device info */ 2763ab8f2a2SRoy Zang struct device *dev; 2773ab8f2a2SRoy Zang struct fsl_lbc_regs __iomem *regs; 278a655f724SShaohui Xie int irq[2]; 2793ab8f2a2SRoy Zang wait_queue_head_t irq_wait; 2803ab8f2a2SRoy Zang spinlock_t lock; 2813ab8f2a2SRoy Zang void *nand; 2823ab8f2a2SRoy Zang 2833ab8f2a2SRoy Zang /* status read from LTESR by irq handler */ 2843ab8f2a2SRoy Zang unsigned int irq_status; 28509cef8bdSJia Hongtao 28609cef8bdSJia Hongtao #ifdef CONFIG_SUSPEND 28709cef8bdSJia Hongtao /* save regs when system go to deep-sleep */ 28809cef8bdSJia Hongtao struct fsl_lbc_regs *saved_regs; 28909cef8bdSJia Hongtao #endif 2903ab8f2a2SRoy Zang }; 2913ab8f2a2SRoy Zang 292c0da99d5SAnton Vorontsov extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, 293c0da99d5SAnton Vorontsov u32 mar); 2943ab8f2a2SRoy Zang extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev; 295b8b572e1SStephen Rothwell 296b8b572e1SStephen Rothwell #endif /* __ASM_FSL_LBC_H */ 297