1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _ASM_PPC_ENTRY_COMMON_H 4 #define _ASM_PPC_ENTRY_COMMON_H 5 6 #include <asm/cputime.h> 7 #include <asm/interrupt.h> 8 #include <asm/stacktrace.h> 9 #include <asm/tm.h> 10 11 static __always_inline void booke_load_dbcr0(void) 12 { 13 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 14 unsigned long dbcr0 = current->thread.debug.dbcr0; 15 16 if (likely(!(dbcr0 & DBCR0_IDM))) 17 return; 18 19 /* 20 * Check to see if the dbcr0 register is set up to debug. 21 * Use the internal debug mode bit to do this. 22 */ 23 mtmsr(mfmsr() & ~MSR_DE); 24 if (IS_ENABLED(CONFIG_PPC32)) { 25 isync(); 26 global_dbcr0[smp_processor_id()] = mfspr(SPRN_DBCR0); 27 } 28 mtspr(SPRN_DBCR0, dbcr0); 29 mtspr(SPRN_DBSR, -1); 30 #endif 31 } 32 33 static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) 34 { 35 kuap_lock(); 36 37 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) 38 BUG_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED); 39 40 BUG_ON(regs_is_unrecoverable(regs)); 41 BUG_ON(!user_mode(regs)); 42 BUG_ON(regs_irqs_disabled(regs)); 43 44 #ifdef CONFIG_PPC_PKEY 45 if (mmu_has_feature(MMU_FTR_PKEY) && trap_is_syscall(regs)) { 46 unsigned long amr, iamr; 47 bool flush_needed = false; 48 /* 49 * When entering from userspace we mostly have the AMR/IAMR 50 * different from kernel default values. Hence don't compare. 51 */ 52 amr = mfspr(SPRN_AMR); 53 iamr = mfspr(SPRN_IAMR); 54 regs->amr = amr; 55 regs->iamr = iamr; 56 if (mmu_has_feature(MMU_FTR_KUAP)) { 57 mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); 58 flush_needed = true; 59 } 60 if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) { 61 mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED); 62 flush_needed = true; 63 } 64 if (flush_needed) 65 isync(); 66 } 67 #endif 68 kuap_assert_locked(); 69 booke_restore_dbcr0(); 70 account_cpu_user_entry(); 71 account_stolen_time(); 72 73 /* 74 * This is not required for the syscall exit path, but makes the 75 * stack frame look nicer. If this was initialised in the first stack 76 * frame, or if the unwinder was taught the first stack frame always 77 * returns to user with IRQS_ENABLED, this store could be avoided! 78 */ 79 irq_soft_mask_regs_set_state(regs, IRQS_ENABLED); 80 81 /* 82 * If system call is called with TM active, set _TIF_RESTOREALL to 83 * prevent RFSCV being used to return to userspace, because POWER9 84 * TM implementation has problems with this instruction returning to 85 * transactional state. Final register values are not relevant because 86 * the transaction will be aborted upon return anyway. Or in the case 87 * of unsupported_scv SIGILL fault, the return state does not much 88 * matter because it's an edge case. 89 */ 90 if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && 91 unlikely(MSR_TM_TRANSACTIONAL(regs->msr))) 92 set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags); 93 94 /* 95 * If the system call was made with a transaction active, doom it and 96 * return without performing the system call. Unless it was an 97 * unsupported scv vector, in which case it's treated like an illegal 98 * instruction. 99 */ 100 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 101 if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) && 102 !trap_is_unsupported_scv(regs)) { 103 /* Enable TM in the kernel, and disable EE (for scv) */ 104 hard_irq_disable(); 105 mtmsr(mfmsr() | MSR_TM); 106 107 /* tabort, this dooms the transaction, nothing else */ 108 asm volatile(".long 0x7c00071d | ((%0) << 16)" 109 :: "r"(TM_CAUSE_SYSCALL | TM_CAUSE_PERSISTENT)); 110 111 /* 112 * Userspace will never see the return value. Execution will 113 * resume after the tbegin. of the aborted transaction with the 114 * checkpointed register state. A context switch could occur 115 * or signal delivered to the process before resuming the 116 * doomed transaction context, but that should all be handled 117 * as expected. 118 */ 119 return; 120 } 121 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 122 } 123 124 #define arch_enter_from_user_mode arch_enter_from_user_mode 125 126 #endif /* _ASM_PPC_ENTRY_COMMON_H */ 127