1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _ASM_PPC_ENTRY_COMMON_H 4 #define _ASM_PPC_ENTRY_COMMON_H 5 6 #include <asm/cputime.h> 7 #include <asm/interrupt.h> 8 #include <asm/stacktrace.h> 9 #include <asm/switch_to.h> 10 #include <asm/tm.h> 11 12 static __always_inline void booke_load_dbcr0(void) 13 { 14 #ifdef CONFIG_PPC_ADV_DEBUG_REGS 15 unsigned long dbcr0 = current->thread.debug.dbcr0; 16 17 if (likely(!(dbcr0 & DBCR0_IDM))) 18 return; 19 20 /* 21 * Check to see if the dbcr0 register is set up to debug. 22 * Use the internal debug mode bit to do this. 23 */ 24 mtmsr(mfmsr() & ~MSR_DE); 25 if (IS_ENABLED(CONFIG_PPC32)) { 26 isync(); 27 global_dbcr0[smp_processor_id()] = mfspr(SPRN_DBCR0); 28 } 29 mtspr(SPRN_DBCR0, dbcr0); 30 mtspr(SPRN_DBSR, -1); 31 #endif 32 } 33 34 static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) 35 { 36 kuap_lock(); 37 38 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) 39 BUG_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED); 40 41 BUG_ON(regs_is_unrecoverable(regs)); 42 BUG_ON(!user_mode(regs)); 43 BUG_ON(regs_irqs_disabled(regs)); 44 45 #ifdef CONFIG_PPC_PKEY 46 if (mmu_has_feature(MMU_FTR_PKEY) && trap_is_syscall(regs)) { 47 unsigned long amr, iamr; 48 bool flush_needed = false; 49 /* 50 * When entering from userspace we mostly have the AMR/IAMR 51 * different from kernel default values. Hence don't compare. 52 */ 53 amr = mfspr(SPRN_AMR); 54 iamr = mfspr(SPRN_IAMR); 55 regs->amr = amr; 56 regs->iamr = iamr; 57 if (mmu_has_feature(MMU_FTR_KUAP)) { 58 mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); 59 flush_needed = true; 60 } 61 if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) { 62 mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED); 63 flush_needed = true; 64 } 65 if (flush_needed) 66 isync(); 67 } 68 #endif 69 kuap_assert_locked(); 70 booke_restore_dbcr0(); 71 account_cpu_user_entry(); 72 account_stolen_time(); 73 74 /* 75 * This is not required for the syscall exit path, but makes the 76 * stack frame look nicer. If this was initialised in the first stack 77 * frame, or if the unwinder was taught the first stack frame always 78 * returns to user with IRQS_ENABLED, this store could be avoided! 79 */ 80 irq_soft_mask_regs_set_state(regs, IRQS_ENABLED); 81 82 /* 83 * If system call is called with TM active, set _TIF_RESTOREALL to 84 * prevent RFSCV being used to return to userspace, because POWER9 85 * TM implementation has problems with this instruction returning to 86 * transactional state. Final register values are not relevant because 87 * the transaction will be aborted upon return anyway. Or in the case 88 * of unsupported_scv SIGILL fault, the return state does not much 89 * matter because it's an edge case. 90 */ 91 if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && 92 unlikely(MSR_TM_TRANSACTIONAL(regs->msr))) 93 set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags); 94 95 /* 96 * If the system call was made with a transaction active, doom it and 97 * return without performing the system call. Unless it was an 98 * unsupported scv vector, in which case it's treated like an illegal 99 * instruction. 100 */ 101 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 102 if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) && 103 !trap_is_unsupported_scv(regs)) { 104 /* Enable TM in the kernel, and disable EE (for scv) */ 105 hard_irq_disable(); 106 mtmsr(mfmsr() | MSR_TM); 107 108 /* tabort, this dooms the transaction, nothing else */ 109 asm volatile(".long 0x7c00071d | ((%0) << 16)" 110 :: "r"(TM_CAUSE_SYSCALL | TM_CAUSE_PERSISTENT)); 111 112 /* 113 * Userspace will never see the return value. Execution will 114 * resume after the tbegin. of the aborted transaction with the 115 * checkpointed register state. A context switch could occur 116 * or signal delivered to the process before resuming the 117 * doomed transaction context, but that should all be handled 118 * as expected. 119 */ 120 return; 121 } 122 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 123 } 124 125 #define arch_enter_from_user_mode arch_enter_from_user_mode 126 127 static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, 128 unsigned long ti_work) 129 { 130 unsigned long mathflags; 131 132 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) { 133 if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && 134 unlikely((ti_work & _TIF_RESTORE_TM))) { 135 restore_tm_state(regs); 136 } else { 137 mathflags = MSR_FP; 138 139 if (cpu_has_feature(CPU_FTR_VSX)) 140 mathflags |= MSR_VEC | MSR_VSX; 141 else if (cpu_has_feature(CPU_FTR_ALTIVEC)) 142 mathflags |= MSR_VEC; 143 144 /* 145 * If userspace MSR has all available FP bits set, 146 * then they are live and no need to restore. If not, 147 * it means the regs were given up and restore_math 148 * may decide to restore them (to avoid taking an FP 149 * fault). 150 */ 151 if ((regs->msr & mathflags) != mathflags) 152 restore_math(regs); 153 } 154 } 155 156 check_return_regs_valid(regs); 157 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 158 local_paca->tm_scratch = regs->msr; 159 #endif 160 /* Restore user access locks last */ 161 kuap_user_restore(regs); 162 } 163 164 #define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare 165 166 static __always_inline void arch_exit_to_user_mode(void) 167 { 168 booke_load_dbcr0(); 169 170 account_cpu_user_exit(); 171 } 172 173 #define arch_exit_to_user_mode arch_exit_to_user_mode 174 175 #endif /* _ASM_PPC_ENTRY_COMMON_H */ 176