1 #ifndef _ASM_POWERPC_DMA_H 2 #define _ASM_POWERPC_DMA_H 3 #ifdef __KERNEL__ 4 5 /* 6 * Defines for using and allocating dma channels. 7 * Written by Hennus Bergman, 1992. 8 * High DMA channel support & info by Hannu Savolainen 9 * and John Boyd, Nov. 1992. 10 * Changes for ppc sound by Christoph Nadig 11 */ 12 13 /* 14 * Note: Adapted for PowerPC by Gary Thomas 15 * Modified by Cort Dougan <cort@cs.nmt.edu> 16 * 17 * None of this really applies for Power Macintoshes. There is 18 * basically just enough here to get kernel/dma.c to compile. 19 * 20 * There may be some comments or restrictions made here which are 21 * not valid for the PReP platform. Take what you read 22 * with a grain of salt. 23 */ 24 25 #include <asm/io.h> 26 #include <linux/spinlock.h> 27 #include <asm/system.h> 28 29 #ifndef MAX_DMA_CHANNELS 30 #define MAX_DMA_CHANNELS 8 31 #endif 32 33 /* The maximum address that we can perform a DMA transfer to on this platform */ 34 /* Doesn't really apply... */ 35 #define MAX_DMA_ADDRESS (~0UL) 36 37 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER 38 #define dma_outb outb_p 39 #else 40 #define dma_outb outb 41 #endif 42 43 #define dma_inb inb 44 45 /* 46 * NOTES about DMA transfers: 47 * 48 * controller 1: channels 0-3, byte operations, ports 00-1F 49 * controller 2: channels 4-7, word operations, ports C0-DF 50 * 51 * - ALL registers are 8 bits only, regardless of transfer size 52 * - channel 4 is not used - cascades 1 into 2. 53 * - channels 0-3 are byte - addresses/counts are for physical bytes 54 * - channels 5-7 are word - addresses/counts are for physical words 55 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries 56 * - transfer count loaded to registers is 1 less than actual count 57 * - controller 2 offsets are all even (2x offsets for controller 1) 58 * - page registers for 5-7 don't use data bit 0, represent 128K pages 59 * - page registers for 0-3 use bit 0, represent 64K pages 60 * 61 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. 62 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing. 63 * Note that addresses loaded into registers must be _physical_ addresses, 64 * not logical addresses (which may differ if paging is active). 65 * 66 * Address mapping for channels 0-3: 67 * 68 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) 69 * | ... | | ... | | ... | 70 * | ... | | ... | | ... | 71 * | ... | | ... | | ... | 72 * P7 ... P0 A7 ... A0 A7 ... A0 73 * | Page | Addr MSB | Addr LSB | (DMA registers) 74 * 75 * Address mapping for channels 5-7: 76 * 77 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) 78 * | ... | \ \ ... \ \ \ ... \ \ 79 * | ... | \ \ ... \ \ \ ... \ (not used) 80 * | ... | \ \ ... \ \ \ ... \ 81 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 82 * | Page | Addr MSB | Addr LSB | (DMA registers) 83 * 84 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses 85 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at 86 * the hardware level, so odd-byte transfers aren't possible). 87 * 88 * Transfer count (_not # bytes_) is limited to 64K, represented as actual 89 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, 90 * and up to 128K bytes may be transferred on channels 5-7 in one operation. 91 * 92 */ 93 94 /* 8237 DMA controllers */ 95 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 96 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 97 98 /* DMA controller registers */ 99 #define DMA1_CMD_REG 0x08 /* command register (w) */ 100 #define DMA1_STAT_REG 0x08 /* status register (r) */ 101 #define DMA1_REQ_REG 0x09 /* request register (w) */ 102 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 103 #define DMA1_MODE_REG 0x0B /* mode register (w) */ 104 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 105 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 106 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 107 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 108 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 109 110 #define DMA2_CMD_REG 0xD0 /* command register (w) */ 111 #define DMA2_STAT_REG 0xD0 /* status register (r) */ 112 #define DMA2_REQ_REG 0xD2 /* request register (w) */ 113 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 114 #define DMA2_MODE_REG 0xD6 /* mode register (w) */ 115 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 116 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 117 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 118 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 119 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 120 121 #define DMA_ADDR_0 0x00 /* DMA address registers */ 122 #define DMA_ADDR_1 0x02 123 #define DMA_ADDR_2 0x04 124 #define DMA_ADDR_3 0x06 125 #define DMA_ADDR_4 0xC0 126 #define DMA_ADDR_5 0xC4 127 #define DMA_ADDR_6 0xC8 128 #define DMA_ADDR_7 0xCC 129 130 #define DMA_CNT_0 0x01 /* DMA count registers */ 131 #define DMA_CNT_1 0x03 132 #define DMA_CNT_2 0x05 133 #define DMA_CNT_3 0x07 134 #define DMA_CNT_4 0xC2 135 #define DMA_CNT_5 0xC6 136 #define DMA_CNT_6 0xCA 137 #define DMA_CNT_7 0xCE 138 139 #define DMA_LO_PAGE_0 0x87 /* DMA page registers */ 140 #define DMA_LO_PAGE_1 0x83 141 #define DMA_LO_PAGE_2 0x81 142 #define DMA_LO_PAGE_3 0x82 143 #define DMA_LO_PAGE_5 0x8B 144 #define DMA_LO_PAGE_6 0x89 145 #define DMA_LO_PAGE_7 0x8A 146 147 #define DMA_HI_PAGE_0 0x487 /* DMA page registers */ 148 #define DMA_HI_PAGE_1 0x483 149 #define DMA_HI_PAGE_2 0x481 150 #define DMA_HI_PAGE_3 0x482 151 #define DMA_HI_PAGE_5 0x48B 152 #define DMA_HI_PAGE_6 0x489 153 #define DMA_HI_PAGE_7 0x48A 154 155 #define DMA1_EXT_REG 0x40B 156 #define DMA2_EXT_REG 0x4D6 157 158 #ifndef __powerpc64__ 159 /* in arch/ppc/kernel/setup.c -- Cort */ 160 extern unsigned int DMA_MODE_WRITE; 161 extern unsigned int DMA_MODE_READ; 162 extern unsigned long ISA_DMA_THRESHOLD; 163 #else 164 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 165 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 166 #endif 167 168 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 169 170 #define DMA_AUTOINIT 0x10 171 172 extern spinlock_t dma_spin_lock; 173 174 static __inline__ unsigned long claim_dma_lock(void) 175 { 176 unsigned long flags; 177 spin_lock_irqsave(&dma_spin_lock, flags); 178 return flags; 179 } 180 181 static __inline__ void release_dma_lock(unsigned long flags) 182 { 183 spin_unlock_irqrestore(&dma_spin_lock, flags); 184 } 185 186 /* enable/disable a specific DMA channel */ 187 static __inline__ void enable_dma(unsigned int dmanr) 188 { 189 unsigned char ucDmaCmd = 0x00; 190 191 if (dmanr != 4) { 192 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ 193 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ 194 } 195 if (dmanr <= 3) { 196 dma_outb(dmanr, DMA1_MASK_REG); 197 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ 198 } else { 199 dma_outb(dmanr & 3, DMA2_MASK_REG); 200 } 201 } 202 203 static __inline__ void disable_dma(unsigned int dmanr) 204 { 205 if (dmanr <= 3) 206 dma_outb(dmanr | 4, DMA1_MASK_REG); 207 else 208 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 209 } 210 211 /* Clear the 'DMA Pointer Flip Flop'. 212 * Write 0 for LSB/MSB, 1 for MSB/LSB access. 213 * Use this once to initialize the FF to a known state. 214 * After that, keep track of it. :-) 215 * --- In order to do that, the DMA routines below should --- 216 * --- only be used while interrupts are disabled! --- 217 */ 218 static __inline__ void clear_dma_ff(unsigned int dmanr) 219 { 220 if (dmanr <= 3) 221 dma_outb(0, DMA1_CLEAR_FF_REG); 222 else 223 dma_outb(0, DMA2_CLEAR_FF_REG); 224 } 225 226 /* set mode (above) for a specific DMA channel */ 227 static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 228 { 229 if (dmanr <= 3) 230 dma_outb(mode | dmanr, DMA1_MODE_REG); 231 else 232 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG); 233 } 234 235 /* Set only the page register bits of the transfer address. 236 * This is used for successive transfers when we know the contents of 237 * the lower 16 bits of the DMA current address register, but a 64k boundary 238 * may have been crossed. 239 */ 240 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr) 241 { 242 switch (dmanr) { 243 case 0: 244 dma_outb(pagenr, DMA_LO_PAGE_0); 245 dma_outb(pagenr >> 8, DMA_HI_PAGE_0); 246 break; 247 case 1: 248 dma_outb(pagenr, DMA_LO_PAGE_1); 249 dma_outb(pagenr >> 8, DMA_HI_PAGE_1); 250 break; 251 case 2: 252 dma_outb(pagenr, DMA_LO_PAGE_2); 253 dma_outb(pagenr >> 8, DMA_HI_PAGE_2); 254 break; 255 case 3: 256 dma_outb(pagenr, DMA_LO_PAGE_3); 257 dma_outb(pagenr >> 8, DMA_HI_PAGE_3); 258 break; 259 case 5: 260 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5); 261 dma_outb(pagenr >> 8, DMA_HI_PAGE_5); 262 break; 263 case 6: 264 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6); 265 dma_outb(pagenr >> 8, DMA_HI_PAGE_6); 266 break; 267 case 7: 268 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7); 269 dma_outb(pagenr >> 8, DMA_HI_PAGE_7); 270 break; 271 } 272 } 273 274 /* Set transfer address & page bits for specific DMA channel. 275 * Assumes dma flipflop is clear. 276 */ 277 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys) 278 { 279 if (dmanr <= 3) { 280 dma_outb(phys & 0xff, 281 ((dmanr & 3) << 1) + IO_DMA1_BASE); 282 dma_outb((phys >> 8) & 0xff, 283 ((dmanr & 3) << 1) + IO_DMA1_BASE); 284 } else { 285 dma_outb((phys >> 1) & 0xff, 286 ((dmanr & 3) << 2) + IO_DMA2_BASE); 287 dma_outb((phys >> 9) & 0xff, 288 ((dmanr & 3) << 2) + IO_DMA2_BASE); 289 } 290 set_dma_page(dmanr, phys >> 16); 291 } 292 293 294 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for 295 * a specific DMA channel. 296 * You must ensure the parameters are valid. 297 * NOTE: from a manual: "the number of transfers is one more 298 * than the initial word count"! This is taken into account. 299 * Assumes dma flip-flop is clear. 300 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 301 */ 302 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 303 { 304 count--; 305 if (dmanr <= 3) { 306 dma_outb(count & 0xff, 307 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE); 308 dma_outb((count >> 8) & 0xff, 309 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE); 310 } else { 311 dma_outb((count >> 1) & 0xff, 312 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE); 313 dma_outb((count >> 9) & 0xff, 314 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE); 315 } 316 } 317 318 319 /* Get DMA residue count. After a DMA transfer, this 320 * should return zero. Reading this while a DMA transfer is 321 * still in progress will return unpredictable results. 322 * If called before the channel has been used, it may return 1. 323 * Otherwise, it returns the number of _bytes_ left to transfer. 324 * 325 * Assumes DMA flip-flop is clear. 326 */ 327 static __inline__ int get_dma_residue(unsigned int dmanr) 328 { 329 unsigned int io_port = (dmanr <= 3) 330 ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE 331 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE; 332 333 /* using short to get 16-bit wrap around */ 334 unsigned short count; 335 336 count = 1 + dma_inb(io_port); 337 count += dma_inb(io_port) << 8; 338 339 return (dmanr <= 3) ? count : (count << 1); 340 } 341 342 /* These are in kernel/dma.c: */ 343 344 /* reserve a DMA channel */ 345 extern int request_dma(unsigned int dmanr, const char *device_id); 346 /* release it again */ 347 extern void free_dma(unsigned int dmanr); 348 349 #ifdef CONFIG_PCI 350 extern int isa_dma_bridge_buggy; 351 #else 352 #define isa_dma_bridge_buggy (0) 353 #endif 354 355 #endif /* __KERNEL__ */ 356 #endif /* _ASM_POWERPC_DMA_H */ 357