1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Common DCR / SDR / CPR register definitions used on various IBM/AMCC 4 * 4xx processors 5 * 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp 7 * <benh@kernel.crashing.org> 8 * 9 * Mostly lifted from asm-ppc/ibm4xx.h by 10 * 11 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 12 * 13 */ 14 15 #ifndef __DCR_REGS_H__ 16 #define __DCR_REGS_H__ 17 18 /* 19 * Most DCRs used for controlling devices such as the MAL, DMA engine, 20 * etc... are obtained for the device tree. 21 * 22 * The definitions in this files are fixed DCRs and indirect DCRs that 23 * are commonly used outside of specific drivers or refer to core 24 * common registers that may occasionally have to be tweaked outside 25 * of the driver main register set 26 */ 27 28 /* CPRs (440GX and 440SP/440SPe) */ 29 #define DCRN_CPR0_CONFIG_ADDR 0xc 30 #define DCRN_CPR0_CONFIG_DATA 0xd 31 32 /* SDRs (440GX and 440SP/440SPe) */ 33 #define DCRN_SDR0_CONFIG_ADDR 0xe 34 #define DCRN_SDR0_CONFIG_DATA 0xf 35 36 #define SDR0_PFC0 0x4100 37 #define SDR0_PFC1 0x4101 38 #define SDR0_PFC1_EPS 0x1c00000 39 #define SDR0_PFC1_EPS_SHIFT 22 40 #define SDR0_PFC1_RMII 0x02000000 41 #define SDR0_MFR 0x4300 42 #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ 43 #define SDR0_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ 44 #define SDR0_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ 45 #define SDR0_MFR_ECS 0x08000000 /* EMAC int clk */ 46 #define SDR0_MFR_T0TXFL 0x00080000 47 #define SDR0_MFR_T0TXFH 0x00040000 48 #define SDR0_MFR_T1TXFL 0x00020000 49 #define SDR0_MFR_T1TXFH 0x00010000 50 #define SDR0_MFR_E0TXFL 0x00008000 51 #define SDR0_MFR_E0TXFH 0x00004000 52 #define SDR0_MFR_E0RXFL 0x00002000 53 #define SDR0_MFR_E0RXFH 0x00001000 54 #define SDR0_MFR_E1TXFL 0x00000800 55 #define SDR0_MFR_E1TXFH 0x00000400 56 #define SDR0_MFR_E1RXFL 0x00000200 57 #define SDR0_MFR_E1RXFH 0x00000100 58 #define SDR0_MFR_E2TXFL 0x00000080 59 #define SDR0_MFR_E2TXFH 0x00000040 60 #define SDR0_MFR_E2RXFL 0x00000020 61 #define SDR0_MFR_E2RXFH 0x00000010 62 #define SDR0_MFR_E3TXFL 0x00000008 63 #define SDR0_MFR_E3TXFH 0x00000004 64 #define SDR0_MFR_E3RXFL 0x00000002 65 #define SDR0_MFR_E3RXFH 0x00000001 66 #define SDR0_UART0 0x0120 67 #define SDR0_UART1 0x0121 68 #define SDR0_UART2 0x0122 69 #define SDR0_UART3 0x0123 70 #define SDR0_CUST0 0x4000 71 72 /* SDR for 405EZ */ 73 #define DCRN_SDR_ICINTSTAT 0x4510 74 #define ICINTSTAT_ICRX 0x80000000 75 #define ICINTSTAT_ICTX0 0x40000000 76 #define ICINTSTAT_ICTX1 0x20000000 77 #define ICINTSTAT_ICTX 0x60000000 78 79 /* SDRs (460EX/460GT) */ 80 #define SDR0_ETH_CFG 0x4103 81 #define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */ 82 83 /* 84 * All those DCR register addresses are offsets from the base address 85 * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is 86 * excluded here and configured in the device tree. 87 */ 88 #define DCRN_SRAM0_SB0CR 0x00 89 #define DCRN_SRAM0_SB1CR 0x01 90 #define DCRN_SRAM0_SB2CR 0x02 91 #define DCRN_SRAM0_SB3CR 0x03 92 #define SRAM_SBCR_BU_MASK 0x00000180 93 #define SRAM_SBCR_BS_64KB 0x00000800 94 #define SRAM_SBCR_BU_RO 0x00000080 95 #define SRAM_SBCR_BU_RW 0x00000180 96 #define DCRN_SRAM0_BEAR 0x04 97 #define DCRN_SRAM0_BESR0 0x05 98 #define DCRN_SRAM0_BESR1 0x06 99 #define DCRN_SRAM0_PMEG 0x07 100 #define DCRN_SRAM0_CID 0x08 101 #define DCRN_SRAM0_REVID 0x09 102 #define DCRN_SRAM0_DPC 0x0a 103 #define SRAM_DPC_ENABLE 0x80000000 104 105 /* 106 * All those DCR register addresses are offsets from the base address 107 * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is 108 * excluded here and configured in the device tree. 109 */ 110 #define DCRN_L2C0_CFG 0x00 111 #define L2C_CFG_L2M 0x80000000 112 #define L2C_CFG_ICU 0x40000000 113 #define L2C_CFG_DCU 0x20000000 114 #define L2C_CFG_DCW_MASK 0x1e000000 115 #define L2C_CFG_TPC 0x01000000 116 #define L2C_CFG_CPC 0x00800000 117 #define L2C_CFG_FRAN 0x00200000 118 #define L2C_CFG_SS_MASK 0x00180000 119 #define L2C_CFG_SS_256 0x00000000 120 #define L2C_CFG_CPIM 0x00040000 121 #define L2C_CFG_TPIM 0x00020000 122 #define L2C_CFG_LIM 0x00010000 123 #define L2C_CFG_PMUX_MASK 0x00007000 124 #define L2C_CFG_PMUX_SNP 0x00000000 125 #define L2C_CFG_PMUX_IF 0x00001000 126 #define L2C_CFG_PMUX_DF 0x00002000 127 #define L2C_CFG_PMUX_DS 0x00003000 128 #define L2C_CFG_PMIM 0x00000800 129 #define L2C_CFG_TPEI 0x00000400 130 #define L2C_CFG_CPEI 0x00000200 131 #define L2C_CFG_NAM 0x00000100 132 #define L2C_CFG_SMCM 0x00000080 133 #define L2C_CFG_NBRM 0x00000040 134 #define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */ 135 #define DCRN_L2C0_CMD 0x01 136 #define L2C_CMD_CLR 0x80000000 137 #define L2C_CMD_DIAG 0x40000000 138 #define L2C_CMD_INV 0x20000000 139 #define L2C_CMD_CCP 0x10000000 140 #define L2C_CMD_CTE 0x08000000 141 #define L2C_CMD_STRC 0x04000000 142 #define L2C_CMD_STPC 0x02000000 143 #define L2C_CMD_RPMC 0x01000000 144 #define L2C_CMD_HCC 0x00800000 145 #define DCRN_L2C0_ADDR 0x02 146 #define DCRN_L2C0_DATA 0x03 147 #define DCRN_L2C0_SR 0x04 148 #define L2C_SR_CC 0x80000000 149 #define L2C_SR_CPE 0x40000000 150 #define L2C_SR_TPE 0x20000000 151 #define L2C_SR_LRU 0x10000000 152 #define L2C_SR_PCS 0x08000000 153 #define DCRN_L2C0_REVID 0x05 154 #define DCRN_L2C0_SNP0 0x06 155 #define DCRN_L2C0_SNP1 0x07 156 #define L2C_SNP_BA_MASK 0xffff0000 157 #define L2C_SNP_SSR_MASK 0x0000f000 158 #define L2C_SNP_SSR_32G 0x0000f000 159 #define L2C_SNP_ESR 0x00000800 160 161 /* 162 * DCR register offsets for 440SP/440SPe I2O/DMA controller. 163 * The base address is configured in the device tree. 164 */ 165 #define DCRN_I2O0_IBAL 0x006 166 #define DCRN_I2O0_IBAH 0x007 167 #define I2O_REG_ENABLE 0x00000001 /* Enable I2O/DMA access */ 168 169 /* 440SP/440SPe Software Reset DCR */ 170 #define DCRN_SDR0_SRST 0x0200 171 #define DCRN_SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */ 172 173 /* 440SP/440SPe Memory Queue DCR offsets */ 174 #define DCRN_MQ0_XORBA 0x04 175 #define DCRN_MQ0_CF2H 0x06 176 #define DCRN_MQ0_CFBHL 0x0f 177 #define DCRN_MQ0_BAUH 0x10 178 179 /* HB/LL Paths Configuration Register */ 180 #define MQ0_CFBHL_TPLM 28 181 #define MQ0_CFBHL_HBCL 23 182 #define MQ0_CFBHL_POLY 15 183 184 #endif /* __DCR_REGS_H__ */ 185