1 #ifndef __ASM_POWERPC_CPUTABLE_H 2 #define __ASM_POWERPC_CPUTABLE_H 3 4 5 #include <linux/types.h> 6 #include <asm/asm-compat.h> 7 #include <asm/feature-fixups.h> 8 #include <uapi/asm/cputable.h> 9 10 #ifndef __ASSEMBLY__ 11 12 /* This structure can grow, it's real size is used by head.S code 13 * via the mkdefs mechanism. 14 */ 15 struct cpu_spec; 16 17 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 18 typedef void (*cpu_restore_t)(void); 19 20 enum powerpc_oprofile_type { 21 PPC_OPROFILE_INVALID = 0, 22 PPC_OPROFILE_RS64 = 1, 23 PPC_OPROFILE_POWER4 = 2, 24 PPC_OPROFILE_G4 = 3, 25 PPC_OPROFILE_FSL_EMB = 4, 26 PPC_OPROFILE_CELL = 5, 27 PPC_OPROFILE_PA6T = 6, 28 }; 29 30 enum powerpc_pmc_type { 31 PPC_PMC_DEFAULT = 0, 32 PPC_PMC_IBM = 1, 33 PPC_PMC_PA6T = 2, 34 PPC_PMC_G4 = 3, 35 }; 36 37 struct pt_regs; 38 39 extern int machine_check_generic(struct pt_regs *regs); 40 extern int machine_check_4xx(struct pt_regs *regs); 41 extern int machine_check_440A(struct pt_regs *regs); 42 extern int machine_check_e500mc(struct pt_regs *regs); 43 extern int machine_check_e500(struct pt_regs *regs); 44 extern int machine_check_e200(struct pt_regs *regs); 45 extern int machine_check_47x(struct pt_regs *regs); 46 int machine_check_8xx(struct pt_regs *regs); 47 48 extern void cpu_down_flush_e500v2(void); 49 extern void cpu_down_flush_e500mc(void); 50 extern void cpu_down_flush_e5500(void); 51 extern void cpu_down_flush_e6500(void); 52 53 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 54 struct cpu_spec { 55 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 56 unsigned int pvr_mask; 57 unsigned int pvr_value; 58 59 char *cpu_name; 60 unsigned long cpu_features; /* Kernel features */ 61 unsigned int cpu_user_features; /* Userland features */ 62 unsigned int cpu_user_features2; /* Userland features v2 */ 63 unsigned int mmu_features; /* MMU features */ 64 65 /* cache line sizes */ 66 unsigned int icache_bsize; 67 unsigned int dcache_bsize; 68 69 /* flush caches inside the current cpu */ 70 void (*cpu_down_flush)(void); 71 72 /* number of performance monitor counters */ 73 unsigned int num_pmcs; 74 enum powerpc_pmc_type pmc_type; 75 76 /* this is called to initialize various CPU bits like L1 cache, 77 * BHT, SPD, etc... from head.S before branching to identify_machine 78 */ 79 cpu_setup_t cpu_setup; 80 /* Used to restore cpu setup on secondary processors and at resume */ 81 cpu_restore_t cpu_restore; 82 83 /* Used by oprofile userspace to select the right counters */ 84 char *oprofile_cpu_type; 85 86 /* Processor specific oprofile operations */ 87 enum powerpc_oprofile_type oprofile_type; 88 89 /* Bit locations inside the mmcra change */ 90 unsigned long oprofile_mmcra_sihv; 91 unsigned long oprofile_mmcra_sipr; 92 93 /* Bits to clear during an oprofile exception */ 94 unsigned long oprofile_mmcra_clear; 95 96 /* Name of processor class, for the ELF AT_PLATFORM entry */ 97 char *platform; 98 99 /* Processor specific machine check handling. Return negative 100 * if the error is fatal, 1 if it was fully recovered and 0 to 101 * pass up (not CPU originated) */ 102 int (*machine_check)(struct pt_regs *regs); 103 104 /* 105 * Processor specific early machine check handler which is 106 * called in real mode to handle SLB and TLB errors. 107 */ 108 long (*machine_check_early)(struct pt_regs *regs); 109 110 /* 111 * Processor specific routine to flush tlbs. 112 */ 113 void (*flush_tlb)(unsigned int action); 114 115 }; 116 117 extern struct cpu_spec *cur_cpu_spec; 118 119 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 120 121 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 122 extern void do_feature_fixups(unsigned long value, void *fixup_start, 123 void *fixup_end); 124 125 extern const char *powerpc_base_platform; 126 127 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 128 extern void cpu_feature_keys_init(void); 129 #else 130 static inline void cpu_feature_keys_init(void) { } 131 #endif 132 133 /* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */ 134 enum { 135 TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */ 136 TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */ 137 }; 138 139 #endif /* __ASSEMBLY__ */ 140 141 /* CPU kernel features */ 142 143 /* Retain the 32b definitions all use bottom half of word */ 144 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 145 #define CPU_FTR_L2CR ASM_CONST(0x00000002) 146 #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004) 147 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008) 148 #define CPU_FTR_TAU ASM_CONST(0x00000010) 149 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020) 150 #define CPU_FTR_USE_TB ASM_CONST(0x00000040) 151 #define CPU_FTR_L2CSR ASM_CONST(0x00000080) 152 #define CPU_FTR_601 ASM_CONST(0x00000100) 153 #define CPU_FTR_DBELL ASM_CONST(0x00000200) 154 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400) 155 #define CPU_FTR_L3CR ASM_CONST(0x00000800) 156 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000) 157 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000) 158 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000) 159 #define CPU_FTR_NO_DPM ASM_CONST(0x00008000) 160 #define CPU_FTR_476_DD2 ASM_CONST(0x00010000) 161 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000) 162 #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000) 163 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000) 164 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000) 165 #define CPU_FTR_PPC_LE ASM_CONST(0x00200000) 166 #define CPU_FTR_REAL_LE ASM_CONST(0x00400000) 167 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000) 168 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000) 169 #define CPU_FTR_SPE ASM_CONST(0x02000000) 170 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000) 171 #define CPU_FTR_LWSYNC ASM_CONST(0x08000000) 172 #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000) 173 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000) 174 #define CPU_FTR_EMB_HV ASM_CONST(0x40000000) 175 176 /* 177 * Add the 64-bit processor unique features in the top half of the word; 178 * on 32-bit, make the names available but defined to be 0. 179 */ 180 #ifdef __powerpc64__ 181 #define LONG_ASM_CONST(x) ASM_CONST(x) 182 #else 183 #define LONG_ASM_CONST(x) 0 184 #endif 185 186 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000) 187 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000) 188 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000) 189 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000) 190 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000) 191 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000) 192 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000) 193 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000) 194 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000) 195 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000) 196 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000) 197 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000) 198 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000) 199 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000) 200 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000) 201 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000) 202 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000) 203 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000) 204 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000) 205 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000) 206 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000) 207 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000) 208 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000) 209 #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000) 210 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) 211 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) 212 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) 213 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) 214 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000) 215 #define CPU_FTR_SUBCORE LONG_ASM_CONST(0x2000000000000000) 216 #define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000) 217 218 #ifndef __ASSEMBLY__ 219 220 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 221 222 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) 223 224 /* We only set the altivec features if the kernel was compiled with altivec 225 * support 226 */ 227 #ifdef CONFIG_ALTIVEC 228 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 229 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 230 #else 231 #define CPU_FTR_ALTIVEC_COMP 0 232 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 233 #endif 234 235 /* We only set the VSX features if the kernel was compiled with VSX 236 * support 237 */ 238 #ifdef CONFIG_VSX 239 #define CPU_FTR_VSX_COMP CPU_FTR_VSX 240 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 241 #else 242 #define CPU_FTR_VSX_COMP 0 243 #define PPC_FEATURE_HAS_VSX_COMP 0 244 #endif 245 246 /* We only set the spe features if the kernel was compiled with spe 247 * support 248 */ 249 #ifdef CONFIG_SPE 250 #define CPU_FTR_SPE_COMP CPU_FTR_SPE 251 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 252 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 253 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 254 #else 255 #define CPU_FTR_SPE_COMP 0 256 #define PPC_FEATURE_HAS_SPE_COMP 0 257 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 258 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 259 #endif 260 261 /* We only set the TM feature if the kernel was compiled with TM supprt */ 262 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 263 #define CPU_FTR_TM_COMP CPU_FTR_TM 264 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 265 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC 266 #else 267 #define CPU_FTR_TM_COMP 0 268 #define PPC_FEATURE2_HTM_COMP 0 269 #define PPC_FEATURE2_HTM_NOSC_COMP 0 270 #endif 271 272 /* We need to mark all pages as being coherent if we're SMP or we have a 273 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 274 * require it for PCI "streaming/prefetch" to work properly. 275 * This is also required by 52xx family. 276 */ 277 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 278 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 279 || defined(CONFIG_PPC_MPC52xx) 280 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 281 #else 282 #define CPU_FTR_COMMON 0 283 #endif 284 285 /* The powersave features NAP & DOZE seems to confuse BDI when 286 debugging. So if a BDI is used, disable theses 287 */ 288 #ifndef CONFIG_BDI_SWITCH 289 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 290 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 291 #else 292 #define CPU_FTR_MAYBE_CAN_DOZE 0 293 #define CPU_FTR_MAYBE_CAN_NAP 0 294 #endif 295 296 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ 297 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 298 #define CPU_FTRS_603 (CPU_FTR_COMMON | \ 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 301 #define CPU_FTRS_604 (CPU_FTR_COMMON | \ 302 CPU_FTR_USE_TB | CPU_FTR_PPC_LE) 303 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 304 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 305 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 306 #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 307 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 308 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 309 CPU_FTR_PPC_LE) 310 #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 311 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 312 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 313 CPU_FTR_PPC_LE) 314 #define CPU_FTRS_750CL (CPU_FTRS_750) 315 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 316 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 317 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 318 #define CPU_FTRS_750GX (CPU_FTRS_750FX) 319 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 320 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 321 CPU_FTR_ALTIVEC_COMP | \ 322 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 323 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 324 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 325 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 326 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 327 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 328 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 329 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 330 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 331 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 332 CPU_FTR_USE_TB | \ 333 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 334 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 335 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 336 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 337 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 338 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 339 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 340 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 341 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 342 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 343 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 344 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 345 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 346 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 347 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 348 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 349 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 350 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 351 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 352 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 353 CPU_FTR_USE_TB | \ 354 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 355 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 356 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 357 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 358 CPU_FTR_USE_TB | \ 359 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 360 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 361 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 362 CPU_FTR_NEED_PAIRED_STWCX) 363 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 364 CPU_FTR_USE_TB | \ 365 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 366 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 367 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 368 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 369 CPU_FTR_USE_TB | \ 370 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 371 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 372 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 373 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 374 CPU_FTR_USE_TB | \ 375 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 376 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 377 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 378 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 379 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 380 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 381 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) 382 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 383 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 384 CPU_FTR_COMMON) 385 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 386 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 387 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 388 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) 389 #define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE) 390 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 391 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 392 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 393 CPU_FTR_INDEXED_DCR) 394 #define CPU_FTRS_47X (CPU_FTRS_440x6) 395 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 396 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 397 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \ 398 CPU_FTR_DEBUG_LVL_EXC) 399 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 400 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 401 CPU_FTR_NOEXECUTE) 402 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 403 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 404 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 405 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 406 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 407 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 408 /* 409 * e5500/e6500 erratum A-006958 is a timebase bug that can use the 410 * same workaround as CPU_FTR_CELL_TB_BUG. 411 */ 412 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 413 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 414 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 415 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 416 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 417 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 418 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 419 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 420 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) 421 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 422 423 /* 64-bit CPUs */ 424 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 425 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 426 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \ 427 CPU_FTR_STCX_CHECKS_ADDRESS) 428 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 429 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ 430 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 431 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 432 CPU_FTR_HVMODE | CPU_FTR_DABRX) 433 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 434 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 435 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 436 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 437 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 438 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 439 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 440 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 441 CPU_FTR_COHERENT_ICACHE | \ 442 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 443 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 444 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 445 CPU_FTR_DABRX) 446 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 447 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 448 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 449 CPU_FTR_COHERENT_ICACHE | \ 450 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 451 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 452 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 453 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 454 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX) 455 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 456 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 457 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 458 CPU_FTR_COHERENT_ICACHE | \ 459 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 460 CPU_FTR_DSCR | CPU_FTR_SAO | \ 461 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 462 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 463 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 464 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_SUBCORE) 465 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) 466 #define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL) 467 #define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 468 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 469 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 470 CPU_FTR_COHERENT_ICACHE | \ 471 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 472 CPU_FTR_DSCR | CPU_FTR_SAO | \ 473 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 474 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 475 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 476 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300) 477 #define CPU_FTRS_POWER9_DD1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) 478 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 479 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 480 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 481 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 482 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 483 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 484 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 485 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 486 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 487 488 #ifdef __powerpc64__ 489 #ifdef CONFIG_PPC_BOOK3E 490 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) 491 #else 492 #define CPU_FTRS_POSSIBLE \ 493 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \ 494 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \ 495 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \ 496 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD1) 497 #endif 498 #else 499 enum { 500 CPU_FTRS_POSSIBLE = 501 #ifdef CONFIG_PPC_BOOK3S_32 502 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 503 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 504 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 505 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 506 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 507 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 508 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 509 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 510 CPU_FTRS_CLASSIC32 | 511 #else 512 CPU_FTRS_GENERIC_32 | 513 #endif 514 #ifdef CONFIG_8xx 515 CPU_FTRS_8XX | 516 #endif 517 #ifdef CONFIG_40x 518 CPU_FTRS_40X | 519 #endif 520 #ifdef CONFIG_44x 521 CPU_FTRS_44X | CPU_FTRS_440x6 | 522 #endif 523 #ifdef CONFIG_PPC_47x 524 CPU_FTRS_47X | CPU_FTR_476_DD2 | 525 #endif 526 #ifdef CONFIG_E200 527 CPU_FTRS_E200 | 528 #endif 529 #ifdef CONFIG_E500 530 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 531 #endif 532 #ifdef CONFIG_PPC_E500MC 533 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 534 #endif 535 0, 536 }; 537 #endif /* __powerpc64__ */ 538 539 #ifdef __powerpc64__ 540 #ifdef CONFIG_PPC_BOOK3E 541 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) 542 #else 543 #define CPU_FTRS_ALWAYS \ 544 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \ 545 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \ 546 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \ 547 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \ 548 CPU_FTRS_POWER9) 549 #endif 550 #else 551 enum { 552 CPU_FTRS_ALWAYS = 553 #ifdef CONFIG_PPC_BOOK3S_32 554 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 555 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 556 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 557 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 558 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 559 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 560 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 561 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 562 CPU_FTRS_CLASSIC32 & 563 #else 564 CPU_FTRS_GENERIC_32 & 565 #endif 566 #ifdef CONFIG_8xx 567 CPU_FTRS_8XX & 568 #endif 569 #ifdef CONFIG_40x 570 CPU_FTRS_40X & 571 #endif 572 #ifdef CONFIG_44x 573 CPU_FTRS_44X & CPU_FTRS_440x6 & 574 #endif 575 #ifdef CONFIG_E200 576 CPU_FTRS_E200 & 577 #endif 578 #ifdef CONFIG_E500 579 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 580 #endif 581 #ifdef CONFIG_PPC_E500MC 582 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 583 #endif 584 ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 585 CPU_FTRS_POSSIBLE, 586 }; 587 #endif /* __powerpc64__ */ 588 589 #define HBP_NUM 1 590 591 #endif /* !__ASSEMBLY__ */ 592 593 #endif /* __ASM_POWERPC_CPUTABLE_H */ 594