1 #ifndef __ASM_POWERPC_CPUTABLE_H 2 #define __ASM_POWERPC_CPUTABLE_H 3 4 #define PPC_FEATURE_32 0x80000000 5 #define PPC_FEATURE_64 0x40000000 6 #define PPC_FEATURE_601_INSTR 0x20000000 7 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000 8 #define PPC_FEATURE_HAS_FPU 0x08000000 9 #define PPC_FEATURE_HAS_MMU 0x04000000 10 #define PPC_FEATURE_HAS_4xxMAC 0x02000000 11 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 12 #define PPC_FEATURE_HAS_SPE 0x00800000 13 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 14 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 15 #define PPC_FEATURE_NO_TB 0x00100000 16 #define PPC_FEATURE_POWER4 0x00080000 17 #define PPC_FEATURE_POWER5 0x00040000 18 #define PPC_FEATURE_POWER5_PLUS 0x00020000 19 #define PPC_FEATURE_CELL 0x00010000 20 #define PPC_FEATURE_BOOKE 0x00008000 21 #define PPC_FEATURE_SMT 0x00004000 22 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000 23 #define PPC_FEATURE_ARCH_2_05 0x00001000 24 #define PPC_FEATURE_PA6T 0x00000800 25 #define PPC_FEATURE_HAS_DFP 0x00000400 26 #define PPC_FEATURE_POWER6_EXT 0x00000200 27 #define PPC_FEATURE_ARCH_2_06 0x00000100 28 #define PPC_FEATURE_HAS_VSX 0x00000080 29 30 #define PPC_FEATURE_PSERIES_PERFMON_COMPAT \ 31 0x00000040 32 33 #define PPC_FEATURE_TRUE_LE 0x00000002 34 #define PPC_FEATURE_PPC_LE 0x00000001 35 36 #ifdef __KERNEL__ 37 38 #include <asm/asm-compat.h> 39 #include <asm/feature-fixups.h> 40 41 #ifndef __ASSEMBLY__ 42 43 /* This structure can grow, it's real size is used by head.S code 44 * via the mkdefs mechanism. 45 */ 46 struct cpu_spec; 47 48 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 49 typedef void (*cpu_restore_t)(void); 50 51 enum powerpc_oprofile_type { 52 PPC_OPROFILE_INVALID = 0, 53 PPC_OPROFILE_RS64 = 1, 54 PPC_OPROFILE_POWER4 = 2, 55 PPC_OPROFILE_G4 = 3, 56 PPC_OPROFILE_FSL_EMB = 4, 57 PPC_OPROFILE_CELL = 5, 58 PPC_OPROFILE_PA6T = 6, 59 }; 60 61 enum powerpc_pmc_type { 62 PPC_PMC_DEFAULT = 0, 63 PPC_PMC_IBM = 1, 64 PPC_PMC_PA6T = 2, 65 PPC_PMC_G4 = 3, 66 }; 67 68 struct pt_regs; 69 70 extern int machine_check_generic(struct pt_regs *regs); 71 extern int machine_check_4xx(struct pt_regs *regs); 72 extern int machine_check_440A(struct pt_regs *regs); 73 extern int machine_check_e500(struct pt_regs *regs); 74 extern int machine_check_e200(struct pt_regs *regs); 75 extern int machine_check_47x(struct pt_regs *regs); 76 77 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 78 struct cpu_spec { 79 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 80 unsigned int pvr_mask; 81 unsigned int pvr_value; 82 83 char *cpu_name; 84 unsigned long cpu_features; /* Kernel features */ 85 unsigned int cpu_user_features; /* Userland features */ 86 unsigned int mmu_features; /* MMU features */ 87 88 /* cache line sizes */ 89 unsigned int icache_bsize; 90 unsigned int dcache_bsize; 91 92 /* number of performance monitor counters */ 93 unsigned int num_pmcs; 94 enum powerpc_pmc_type pmc_type; 95 96 /* this is called to initialize various CPU bits like L1 cache, 97 * BHT, SPD, etc... from head.S before branching to identify_machine 98 */ 99 cpu_setup_t cpu_setup; 100 /* Used to restore cpu setup on secondary processors and at resume */ 101 cpu_restore_t cpu_restore; 102 103 /* Used by oprofile userspace to select the right counters */ 104 char *oprofile_cpu_type; 105 106 /* Processor specific oprofile operations */ 107 enum powerpc_oprofile_type oprofile_type; 108 109 /* Bit locations inside the mmcra change */ 110 unsigned long oprofile_mmcra_sihv; 111 unsigned long oprofile_mmcra_sipr; 112 113 /* Bits to clear during an oprofile exception */ 114 unsigned long oprofile_mmcra_clear; 115 116 /* Name of processor class, for the ELF AT_PLATFORM entry */ 117 char *platform; 118 119 /* Processor specific machine check handling. Return negative 120 * if the error is fatal, 1 if it was fully recovered and 0 to 121 * pass up (not CPU originated) */ 122 int (*machine_check)(struct pt_regs *regs); 123 }; 124 125 extern struct cpu_spec *cur_cpu_spec; 126 127 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 128 129 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 130 extern void do_feature_fixups(unsigned long value, void *fixup_start, 131 void *fixup_end); 132 133 extern const char *powerpc_base_platform; 134 135 #endif /* __ASSEMBLY__ */ 136 137 /* CPU kernel features */ 138 139 /* Retain the 32b definitions all use bottom half of word */ 140 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001) 141 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) 142 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) 143 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) 144 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010) 145 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) 146 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) 147 #define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080) 148 #define CPU_FTR_601 ASM_CONST(0x0000000000000100) 149 #define CPU_FTR_DBELL ASM_CONST(0x0000000000000200) 150 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) 151 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) 152 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) 153 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) 154 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) 155 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) 156 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) 157 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) 158 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 159 #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 160 #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 161 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) 162 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) 163 #define CPU_FTR_SPE ASM_CONST(0x0000000002000000) 164 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000) 165 #define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000) 166 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000) 167 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000) 168 169 /* 170 * Add the 64-bit processor unique features in the top half of the word; 171 * on 32-bit, make the names available but defined to be 0. 172 */ 173 #ifdef __powerpc64__ 174 #define LONG_ASM_CONST(x) ASM_CONST(x) 175 #else 176 #define LONG_ASM_CONST(x) 0 177 #endif 178 179 #define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000) 180 #define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000) 181 #define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000) 182 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000) 183 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) 184 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) 185 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) 186 #define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000) 187 #define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000) 188 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 189 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 190 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 191 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) 192 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) 193 #define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000) 194 #define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000) 195 #define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) 196 #define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000) 197 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000) 198 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000) 199 200 #ifndef __ASSEMBLY__ 201 202 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \ 203 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ 204 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE) 205 206 /* We only set the altivec features if the kernel was compiled with altivec 207 * support 208 */ 209 #ifdef CONFIG_ALTIVEC 210 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 211 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 212 #else 213 #define CPU_FTR_ALTIVEC_COMP 0 214 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 215 #endif 216 217 /* We only set the VSX features if the kernel was compiled with VSX 218 * support 219 */ 220 #ifdef CONFIG_VSX 221 #define CPU_FTR_VSX_COMP CPU_FTR_VSX 222 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 223 #else 224 #define CPU_FTR_VSX_COMP 0 225 #define PPC_FEATURE_HAS_VSX_COMP 0 226 #endif 227 228 /* We only set the spe features if the kernel was compiled with spe 229 * support 230 */ 231 #ifdef CONFIG_SPE 232 #define CPU_FTR_SPE_COMP CPU_FTR_SPE 233 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 234 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 235 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 236 #else 237 #define CPU_FTR_SPE_COMP 0 238 #define PPC_FEATURE_HAS_SPE_COMP 0 239 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 240 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 241 #endif 242 243 /* We need to mark all pages as being coherent if we're SMP or we have a 244 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 245 * require it for PCI "streaming/prefetch" to work properly. 246 * This is also required by 52xx family. 247 */ 248 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 249 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 250 || defined(CONFIG_PPC_MPC52xx) 251 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 252 #else 253 #define CPU_FTR_COMMON 0 254 #endif 255 256 /* The powersave features NAP & DOZE seems to confuse BDI when 257 debugging. So if a BDI is used, disable theses 258 */ 259 #ifndef CONFIG_BDI_SWITCH 260 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 261 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 262 #else 263 #define CPU_FTR_MAYBE_CAN_DOZE 0 264 #define CPU_FTR_MAYBE_CAN_NAP 0 265 #endif 266 267 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ 268 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ 269 !defined(CONFIG_BOOKE)) 270 271 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ 272 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 273 #define CPU_FTRS_603 (CPU_FTR_COMMON | \ 274 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 275 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 276 #define CPU_FTRS_604 (CPU_FTR_COMMON | \ 277 CPU_FTR_USE_TB | CPU_FTR_PPC_LE) 278 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 279 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 280 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 281 #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 283 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 284 CPU_FTR_PPC_LE) 285 #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 286 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 287 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 288 CPU_FTR_PPC_LE) 289 #define CPU_FTRS_750CL (CPU_FTRS_750) 290 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 291 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 292 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 293 #define CPU_FTRS_750GX (CPU_FTRS_750FX) 294 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 295 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 296 CPU_FTR_ALTIVEC_COMP | \ 297 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 298 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 300 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 302 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 303 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 304 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 305 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 306 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 307 CPU_FTR_USE_TB | \ 308 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 309 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 310 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 311 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 312 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 313 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 314 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 315 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 316 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 317 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 318 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 319 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 320 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 321 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 322 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 323 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 324 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 325 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 326 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 327 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 328 CPU_FTR_USE_TB | \ 329 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 330 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 331 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 332 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 333 CPU_FTR_USE_TB | \ 334 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 335 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 336 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 337 CPU_FTR_NEED_PAIRED_STWCX) 338 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 339 CPU_FTR_USE_TB | \ 340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 341 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 342 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 343 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 344 CPU_FTR_USE_TB | \ 345 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 346 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 347 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 348 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 349 CPU_FTR_USE_TB | \ 350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 351 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 352 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 353 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 354 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 355 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 356 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) 357 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 358 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 359 CPU_FTR_COMMON) 360 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 361 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 362 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 363 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) 364 #define CPU_FTRS_8XX (CPU_FTR_USE_TB) 365 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 366 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 367 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 368 CPU_FTR_INDEXED_DCR) 369 #define CPU_FTRS_47X (CPU_FTRS_440x6) 370 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 371 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 372 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE) 373 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 374 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 375 CPU_FTR_NOEXECUTE) 376 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 377 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 378 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 379 #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 380 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 381 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 382 CPU_FTR_DBELL) 383 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 384 385 /* 64-bit CPUs */ 386 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \ 387 CPU_FTR_IABR | CPU_FTR_PPC_LE) 388 #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \ 389 CPU_FTR_IABR | \ 390 CPU_FTR_MMCRA | CPU_FTR_CTRL) 391 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 392 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 393 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ) 394 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 395 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 396 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 397 CPU_FTR_CP_USE_DCBTZ) 398 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 399 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 400 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 401 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 402 CPU_FTR_PURR) 403 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 405 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 406 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 407 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 408 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD) 409 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 410 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 411 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 412 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ 413 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 414 CPU_FTR_DSCR | CPU_FTR_SAO) 415 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 416 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 417 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 418 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \ 419 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 420 CPU_FTR_UNALIGNED_LD_STD) 421 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 422 CPU_FTR_PPCAS_ARCH_V2 | \ 423 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ 424 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B) 425 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 426 427 #ifdef __powerpc64__ 428 #define CPU_FTRS_POSSIBLE \ 429 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 430 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 431 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 432 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX) 433 #else 434 enum { 435 CPU_FTRS_POSSIBLE = 436 #if CLASSIC_PPC 437 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 438 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 439 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 440 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 441 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 442 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 443 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 444 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 445 CPU_FTRS_CLASSIC32 | 446 #else 447 CPU_FTRS_GENERIC_32 | 448 #endif 449 #ifdef CONFIG_8xx 450 CPU_FTRS_8XX | 451 #endif 452 #ifdef CONFIG_40x 453 CPU_FTRS_40X | 454 #endif 455 #ifdef CONFIG_44x 456 CPU_FTRS_44X | CPU_FTRS_440x6 | 457 #endif 458 #ifdef CONFIG_PPC_47x 459 CPU_FTRS_47X | 460 #endif 461 #ifdef CONFIG_E200 462 CPU_FTRS_E200 | 463 #endif 464 #ifdef CONFIG_E500 465 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC | 466 #endif 467 0, 468 }; 469 #endif /* __powerpc64__ */ 470 471 #ifdef __powerpc64__ 472 #define CPU_FTRS_ALWAYS \ 473 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 474 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ 475 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) 476 #else 477 enum { 478 CPU_FTRS_ALWAYS = 479 #if CLASSIC_PPC 480 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 481 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 482 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 483 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 484 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 485 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 486 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 487 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 488 CPU_FTRS_CLASSIC32 & 489 #else 490 CPU_FTRS_GENERIC_32 & 491 #endif 492 #ifdef CONFIG_8xx 493 CPU_FTRS_8XX & 494 #endif 495 #ifdef CONFIG_40x 496 CPU_FTRS_40X & 497 #endif 498 #ifdef CONFIG_44x 499 CPU_FTRS_44X & CPU_FTRS_440x6 & 500 #endif 501 #ifdef CONFIG_E200 502 CPU_FTRS_E200 & 503 #endif 504 #ifdef CONFIG_E500 505 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC & 506 #endif 507 CPU_FTRS_POSSIBLE, 508 }; 509 #endif /* __powerpc64__ */ 510 511 static inline int cpu_has_feature(unsigned long feature) 512 { 513 return (CPU_FTRS_ALWAYS & feature) || 514 (CPU_FTRS_POSSIBLE 515 & cur_cpu_spec->cpu_features 516 & feature); 517 } 518 519 #endif /* !__ASSEMBLY__ */ 520 521 #endif /* __KERNEL__ */ 522 #endif /* __ASM_POWERPC_CPUTABLE_H */ 523