1 #ifndef __ASM_POWERPC_CPUTABLE_H 2 #define __ASM_POWERPC_CPUTABLE_H 3 4 5 #include <linux/types.h> 6 #include <asm/asm-compat.h> 7 #include <asm/feature-fixups.h> 8 #include <uapi/asm/cputable.h> 9 10 #ifndef __ASSEMBLY__ 11 12 /* This structure can grow, it's real size is used by head.S code 13 * via the mkdefs mechanism. 14 */ 15 struct cpu_spec; 16 17 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 18 typedef void (*cpu_restore_t)(void); 19 20 enum powerpc_oprofile_type { 21 PPC_OPROFILE_INVALID = 0, 22 PPC_OPROFILE_RS64 = 1, 23 PPC_OPROFILE_POWER4 = 2, 24 PPC_OPROFILE_G4 = 3, 25 PPC_OPROFILE_FSL_EMB = 4, 26 PPC_OPROFILE_CELL = 5, 27 PPC_OPROFILE_PA6T = 6, 28 }; 29 30 enum powerpc_pmc_type { 31 PPC_PMC_DEFAULT = 0, 32 PPC_PMC_IBM = 1, 33 PPC_PMC_PA6T = 2, 34 PPC_PMC_G4 = 3, 35 }; 36 37 struct pt_regs; 38 39 extern int machine_check_generic(struct pt_regs *regs); 40 extern int machine_check_4xx(struct pt_regs *regs); 41 extern int machine_check_440A(struct pt_regs *regs); 42 extern int machine_check_e500mc(struct pt_regs *regs); 43 extern int machine_check_e500(struct pt_regs *regs); 44 extern int machine_check_e200(struct pt_regs *regs); 45 extern int machine_check_47x(struct pt_regs *regs); 46 47 extern void cpu_down_flush_e500v2(void); 48 extern void cpu_down_flush_e500mc(void); 49 extern void cpu_down_flush_e5500(void); 50 extern void cpu_down_flush_e6500(void); 51 52 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 53 struct cpu_spec { 54 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 55 unsigned int pvr_mask; 56 unsigned int pvr_value; 57 58 char *cpu_name; 59 unsigned long cpu_features; /* Kernel features */ 60 unsigned int cpu_user_features; /* Userland features */ 61 unsigned int cpu_user_features2; /* Userland features v2 */ 62 unsigned int mmu_features; /* MMU features */ 63 64 /* cache line sizes */ 65 unsigned int icache_bsize; 66 unsigned int dcache_bsize; 67 68 /* flush caches inside the current cpu */ 69 void (*cpu_down_flush)(void); 70 71 /* number of performance monitor counters */ 72 unsigned int num_pmcs; 73 enum powerpc_pmc_type pmc_type; 74 75 /* this is called to initialize various CPU bits like L1 cache, 76 * BHT, SPD, etc... from head.S before branching to identify_machine 77 */ 78 cpu_setup_t cpu_setup; 79 /* Used to restore cpu setup on secondary processors and at resume */ 80 cpu_restore_t cpu_restore; 81 82 /* Used by oprofile userspace to select the right counters */ 83 char *oprofile_cpu_type; 84 85 /* Processor specific oprofile operations */ 86 enum powerpc_oprofile_type oprofile_type; 87 88 /* Bit locations inside the mmcra change */ 89 unsigned long oprofile_mmcra_sihv; 90 unsigned long oprofile_mmcra_sipr; 91 92 /* Bits to clear during an oprofile exception */ 93 unsigned long oprofile_mmcra_clear; 94 95 /* Name of processor class, for the ELF AT_PLATFORM entry */ 96 char *platform; 97 98 /* Processor specific machine check handling. Return negative 99 * if the error is fatal, 1 if it was fully recovered and 0 to 100 * pass up (not CPU originated) */ 101 int (*machine_check)(struct pt_regs *regs); 102 103 /* 104 * Processor specific early machine check handler which is 105 * called in real mode to handle SLB and TLB errors. 106 */ 107 long (*machine_check_early)(struct pt_regs *regs); 108 109 /* 110 * Processor specific routine to flush tlbs. 111 */ 112 void (*flush_tlb)(unsigned int action); 113 114 }; 115 116 extern struct cpu_spec *cur_cpu_spec; 117 118 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 119 120 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 121 extern void do_feature_fixups(unsigned long value, void *fixup_start, 122 void *fixup_end); 123 124 extern const char *powerpc_base_platform; 125 126 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 127 extern void cpu_feature_keys_init(void); 128 #else 129 static inline void cpu_feature_keys_init(void) { } 130 #endif 131 132 /* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */ 133 enum { 134 TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */ 135 TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */ 136 }; 137 138 #endif /* __ASSEMBLY__ */ 139 140 /* CPU kernel features */ 141 142 /* Retain the 32b definitions all use bottom half of word */ 143 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 144 #define CPU_FTR_L2CR ASM_CONST(0x00000002) 145 #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004) 146 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008) 147 #define CPU_FTR_TAU ASM_CONST(0x00000010) 148 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020) 149 #define CPU_FTR_USE_TB ASM_CONST(0x00000040) 150 #define CPU_FTR_L2CSR ASM_CONST(0x00000080) 151 #define CPU_FTR_601 ASM_CONST(0x00000100) 152 #define CPU_FTR_DBELL ASM_CONST(0x00000200) 153 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400) 154 #define CPU_FTR_L3CR ASM_CONST(0x00000800) 155 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000) 156 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000) 157 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000) 158 #define CPU_FTR_NO_DPM ASM_CONST(0x00008000) 159 #define CPU_FTR_476_DD2 ASM_CONST(0x00010000) 160 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000) 161 #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000) 162 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000) 163 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000) 164 #define CPU_FTR_PPC_LE ASM_CONST(0x00200000) 165 #define CPU_FTR_REAL_LE ASM_CONST(0x00400000) 166 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000) 167 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000) 168 #define CPU_FTR_SPE ASM_CONST(0x02000000) 169 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000) 170 #define CPU_FTR_LWSYNC ASM_CONST(0x08000000) 171 #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000) 172 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000) 173 #define CPU_FTR_EMB_HV ASM_CONST(0x40000000) 174 175 /* 176 * Add the 64-bit processor unique features in the top half of the word; 177 * on 32-bit, make the names available but defined to be 0. 178 */ 179 #ifdef __powerpc64__ 180 #define LONG_ASM_CONST(x) ASM_CONST(x) 181 #else 182 #define LONG_ASM_CONST(x) 0 183 #endif 184 185 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000) 186 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000) 187 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000) 188 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000) 189 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000) 190 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000) 191 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000) 192 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000) 193 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000) 194 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000) 195 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000) 196 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000) 197 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000) 198 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000) 199 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000) 200 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000) 201 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000) 202 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000) 203 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000) 204 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000) 205 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000) 206 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000) 207 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000) 208 #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000) 209 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) 210 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) 211 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) 212 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) 213 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000) 214 #define CPU_FTR_SUBCORE LONG_ASM_CONST(0x2000000000000000) 215 #define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000) 216 217 #ifndef __ASSEMBLY__ 218 219 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 220 221 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) 222 223 /* We only set the altivec features if the kernel was compiled with altivec 224 * support 225 */ 226 #ifdef CONFIG_ALTIVEC 227 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 228 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 229 #else 230 #define CPU_FTR_ALTIVEC_COMP 0 231 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 232 #endif 233 234 /* We only set the VSX features if the kernel was compiled with VSX 235 * support 236 */ 237 #ifdef CONFIG_VSX 238 #define CPU_FTR_VSX_COMP CPU_FTR_VSX 239 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 240 #else 241 #define CPU_FTR_VSX_COMP 0 242 #define PPC_FEATURE_HAS_VSX_COMP 0 243 #endif 244 245 /* We only set the spe features if the kernel was compiled with spe 246 * support 247 */ 248 #ifdef CONFIG_SPE 249 #define CPU_FTR_SPE_COMP CPU_FTR_SPE 250 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 251 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 252 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 253 #else 254 #define CPU_FTR_SPE_COMP 0 255 #define PPC_FEATURE_HAS_SPE_COMP 0 256 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 257 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 258 #endif 259 260 /* We only set the TM feature if the kernel was compiled with TM supprt */ 261 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 262 #define CPU_FTR_TM_COMP CPU_FTR_TM 263 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 264 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC 265 #else 266 #define CPU_FTR_TM_COMP 0 267 #define PPC_FEATURE2_HTM_COMP 0 268 #define PPC_FEATURE2_HTM_NOSC_COMP 0 269 #endif 270 271 /* We need to mark all pages as being coherent if we're SMP or we have a 272 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 273 * require it for PCI "streaming/prefetch" to work properly. 274 * This is also required by 52xx family. 275 */ 276 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 277 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 278 || defined(CONFIG_PPC_MPC52xx) 279 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 280 #else 281 #define CPU_FTR_COMMON 0 282 #endif 283 284 /* The powersave features NAP & DOZE seems to confuse BDI when 285 debugging. So if a BDI is used, disable theses 286 */ 287 #ifndef CONFIG_BDI_SWITCH 288 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 289 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 290 #else 291 #define CPU_FTR_MAYBE_CAN_DOZE 0 292 #define CPU_FTR_MAYBE_CAN_NAP 0 293 #endif 294 295 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ 296 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 297 #define CPU_FTRS_603 (CPU_FTR_COMMON | \ 298 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 299 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 300 #define CPU_FTRS_604 (CPU_FTR_COMMON | \ 301 CPU_FTR_USE_TB | CPU_FTR_PPC_LE) 302 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 303 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 305 #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 306 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 307 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 308 CPU_FTR_PPC_LE) 309 #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 310 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 311 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 312 CPU_FTR_PPC_LE) 313 #define CPU_FTRS_750CL (CPU_FTRS_750) 314 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 315 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 316 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 317 #define CPU_FTRS_750GX (CPU_FTRS_750FX) 318 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 319 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 320 CPU_FTR_ALTIVEC_COMP | \ 321 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 322 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 323 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 324 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 326 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 327 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 329 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 330 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 331 CPU_FTR_USE_TB | \ 332 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 333 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 334 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 335 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 336 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 337 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 338 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 339 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 340 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 341 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 342 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 343 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 344 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 345 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 346 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 347 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 348 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 349 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 350 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 351 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 352 CPU_FTR_USE_TB | \ 353 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 354 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 355 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 356 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 357 CPU_FTR_USE_TB | \ 358 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 359 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 360 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 361 CPU_FTR_NEED_PAIRED_STWCX) 362 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 363 CPU_FTR_USE_TB | \ 364 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 365 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 366 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 367 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 368 CPU_FTR_USE_TB | \ 369 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 370 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 371 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 372 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 373 CPU_FTR_USE_TB | \ 374 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 375 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 376 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 377 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 378 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 379 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 380 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) 381 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 382 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 383 CPU_FTR_COMMON) 384 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 385 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 386 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 387 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) 388 #define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE) 389 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 390 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 391 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 392 CPU_FTR_INDEXED_DCR) 393 #define CPU_FTRS_47X (CPU_FTRS_440x6) 394 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 395 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 396 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \ 397 CPU_FTR_DEBUG_LVL_EXC) 398 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 399 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 400 CPU_FTR_NOEXECUTE) 401 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 402 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 403 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 404 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 405 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 406 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 407 /* 408 * e5500/e6500 erratum A-006958 is a timebase bug that can use the 409 * same workaround as CPU_FTR_CELL_TB_BUG. 410 */ 411 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 412 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 413 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 414 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 415 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 416 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 417 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 418 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 419 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) 420 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 421 422 /* 64-bit CPUs */ 423 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 424 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 425 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \ 426 CPU_FTR_STCX_CHECKS_ADDRESS) 427 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 428 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ 429 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 430 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 431 CPU_FTR_HVMODE | CPU_FTR_DABRX) 432 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 433 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 434 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 435 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 436 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 437 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 438 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 439 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 440 CPU_FTR_COHERENT_ICACHE | \ 441 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 442 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 443 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 444 CPU_FTR_DABRX) 445 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 446 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 447 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 448 CPU_FTR_COHERENT_ICACHE | \ 449 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 450 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 451 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 452 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 453 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX) 454 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 455 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 456 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 457 CPU_FTR_COHERENT_ICACHE | \ 458 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 459 CPU_FTR_DSCR | CPU_FTR_SAO | \ 460 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 461 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 462 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 463 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_SUBCORE) 464 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) 465 #define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL) 466 #define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 467 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 468 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 469 CPU_FTR_COHERENT_ICACHE | \ 470 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 471 CPU_FTR_DSCR | CPU_FTR_SAO | \ 472 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 473 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 474 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 475 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300) 476 #define CPU_FTRS_POWER9_DD1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) 477 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 478 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 479 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 480 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 481 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 482 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 483 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 484 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 485 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 486 487 #ifdef __powerpc64__ 488 #ifdef CONFIG_PPC_BOOK3E 489 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) 490 #else 491 #define CPU_FTRS_POSSIBLE \ 492 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \ 493 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \ 494 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \ 495 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD1) 496 #endif 497 #else 498 enum { 499 CPU_FTRS_POSSIBLE = 500 #ifdef CONFIG_PPC_BOOK3S_32 501 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 502 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 503 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 504 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 505 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 506 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 507 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 508 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 509 CPU_FTRS_CLASSIC32 | 510 #else 511 CPU_FTRS_GENERIC_32 | 512 #endif 513 #ifdef CONFIG_8xx 514 CPU_FTRS_8XX | 515 #endif 516 #ifdef CONFIG_40x 517 CPU_FTRS_40X | 518 #endif 519 #ifdef CONFIG_44x 520 CPU_FTRS_44X | CPU_FTRS_440x6 | 521 #endif 522 #ifdef CONFIG_PPC_47x 523 CPU_FTRS_47X | CPU_FTR_476_DD2 | 524 #endif 525 #ifdef CONFIG_E200 526 CPU_FTRS_E200 | 527 #endif 528 #ifdef CONFIG_E500 529 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 530 #endif 531 #ifdef CONFIG_PPC_E500MC 532 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 533 #endif 534 0, 535 }; 536 #endif /* __powerpc64__ */ 537 538 #ifdef __powerpc64__ 539 #ifdef CONFIG_PPC_BOOK3E 540 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) 541 #else 542 #define CPU_FTRS_ALWAYS \ 543 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \ 544 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \ 545 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \ 546 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \ 547 CPU_FTRS_POWER9) 548 #endif 549 #else 550 enum { 551 CPU_FTRS_ALWAYS = 552 #ifdef CONFIG_PPC_BOOK3S_32 553 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 554 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 555 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 556 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 557 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 558 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 559 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 560 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 561 CPU_FTRS_CLASSIC32 & 562 #else 563 CPU_FTRS_GENERIC_32 & 564 #endif 565 #ifdef CONFIG_8xx 566 CPU_FTRS_8XX & 567 #endif 568 #ifdef CONFIG_40x 569 CPU_FTRS_40X & 570 #endif 571 #ifdef CONFIG_44x 572 CPU_FTRS_44X & CPU_FTRS_440x6 & 573 #endif 574 #ifdef CONFIG_E200 575 CPU_FTRS_E200 & 576 #endif 577 #ifdef CONFIG_E500 578 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 579 #endif 580 #ifdef CONFIG_PPC_E500MC 581 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 582 #endif 583 ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 584 CPU_FTRS_POSSIBLE, 585 }; 586 #endif /* __powerpc64__ */ 587 588 #define HBP_NUM 1 589 590 #endif /* !__ASSEMBLY__ */ 591 592 #endif /* __ASM_POWERPC_CPUTABLE_H */ 593