1 #ifndef __ASM_POWERPC_CPUTABLE_H 2 #define __ASM_POWERPC_CPUTABLE_H 3 4 #define PPC_FEATURE_32 0x80000000 5 #define PPC_FEATURE_64 0x40000000 6 #define PPC_FEATURE_601_INSTR 0x20000000 7 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000 8 #define PPC_FEATURE_HAS_FPU 0x08000000 9 #define PPC_FEATURE_HAS_MMU 0x04000000 10 #define PPC_FEATURE_HAS_4xxMAC 0x02000000 11 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 12 #define PPC_FEATURE_HAS_SPE 0x00800000 13 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 14 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 15 #define PPC_FEATURE_NO_TB 0x00100000 16 #define PPC_FEATURE_POWER4 0x00080000 17 #define PPC_FEATURE_POWER5 0x00040000 18 #define PPC_FEATURE_POWER5_PLUS 0x00020000 19 #define PPC_FEATURE_CELL 0x00010000 20 #define PPC_FEATURE_BOOKE 0x00008000 21 #define PPC_FEATURE_SMT 0x00004000 22 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000 23 #define PPC_FEATURE_ARCH_2_05 0x00001000 24 #define PPC_FEATURE_PA6T 0x00000800 25 #define PPC_FEATURE_HAS_DFP 0x00000400 26 #define PPC_FEATURE_POWER6_EXT 0x00000200 27 #define PPC_FEATURE_ARCH_2_06 0x00000100 28 #define PPC_FEATURE_HAS_VSX 0x00000080 29 30 #define PPC_FEATURE_PSERIES_PERFMON_COMPAT \ 31 0x00000040 32 33 #define PPC_FEATURE_TRUE_LE 0x00000002 34 #define PPC_FEATURE_PPC_LE 0x00000001 35 36 #ifdef __KERNEL__ 37 38 #include <asm/asm-compat.h> 39 #include <asm/feature-fixups.h> 40 41 #ifndef __ASSEMBLY__ 42 43 /* This structure can grow, it's real size is used by head.S code 44 * via the mkdefs mechanism. 45 */ 46 struct cpu_spec; 47 48 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 49 typedef void (*cpu_restore_t)(void); 50 51 enum powerpc_oprofile_type { 52 PPC_OPROFILE_INVALID = 0, 53 PPC_OPROFILE_RS64 = 1, 54 PPC_OPROFILE_POWER4 = 2, 55 PPC_OPROFILE_G4 = 3, 56 PPC_OPROFILE_FSL_EMB = 4, 57 PPC_OPROFILE_CELL = 5, 58 PPC_OPROFILE_PA6T = 6, 59 }; 60 61 enum powerpc_pmc_type { 62 PPC_PMC_DEFAULT = 0, 63 PPC_PMC_IBM = 1, 64 PPC_PMC_PA6T = 2, 65 PPC_PMC_G4 = 3, 66 }; 67 68 struct pt_regs; 69 70 extern int machine_check_generic(struct pt_regs *regs); 71 extern int machine_check_4xx(struct pt_regs *regs); 72 extern int machine_check_440A(struct pt_regs *regs); 73 extern int machine_check_e500mc(struct pt_regs *regs); 74 extern int machine_check_e500(struct pt_regs *regs); 75 extern int machine_check_e200(struct pt_regs *regs); 76 extern int machine_check_47x(struct pt_regs *regs); 77 78 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 79 struct cpu_spec { 80 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 81 unsigned int pvr_mask; 82 unsigned int pvr_value; 83 84 char *cpu_name; 85 unsigned long cpu_features; /* Kernel features */ 86 unsigned int cpu_user_features; /* Userland features */ 87 unsigned int mmu_features; /* MMU features */ 88 89 /* cache line sizes */ 90 unsigned int icache_bsize; 91 unsigned int dcache_bsize; 92 93 /* number of performance monitor counters */ 94 unsigned int num_pmcs; 95 enum powerpc_pmc_type pmc_type; 96 97 /* this is called to initialize various CPU bits like L1 cache, 98 * BHT, SPD, etc... from head.S before branching to identify_machine 99 */ 100 cpu_setup_t cpu_setup; 101 /* Used to restore cpu setup on secondary processors and at resume */ 102 cpu_restore_t cpu_restore; 103 104 /* Used by oprofile userspace to select the right counters */ 105 char *oprofile_cpu_type; 106 107 /* Processor specific oprofile operations */ 108 enum powerpc_oprofile_type oprofile_type; 109 110 /* Bit locations inside the mmcra change */ 111 unsigned long oprofile_mmcra_sihv; 112 unsigned long oprofile_mmcra_sipr; 113 114 /* Bits to clear during an oprofile exception */ 115 unsigned long oprofile_mmcra_clear; 116 117 /* Name of processor class, for the ELF AT_PLATFORM entry */ 118 char *platform; 119 120 /* Processor specific machine check handling. Return negative 121 * if the error is fatal, 1 if it was fully recovered and 0 to 122 * pass up (not CPU originated) */ 123 int (*machine_check)(struct pt_regs *regs); 124 }; 125 126 extern struct cpu_spec *cur_cpu_spec; 127 128 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 129 130 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 131 extern void do_feature_fixups(unsigned long value, void *fixup_start, 132 void *fixup_end); 133 134 extern const char *powerpc_base_platform; 135 136 #endif /* __ASSEMBLY__ */ 137 138 /* CPU kernel features */ 139 140 /* Retain the 32b definitions all use bottom half of word */ 141 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001) 142 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) 143 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) 144 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) 145 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010) 146 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) 147 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) 148 #define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080) 149 #define CPU_FTR_601 ASM_CONST(0x0000000000000100) 150 #define CPU_FTR_DBELL ASM_CONST(0x0000000000000200) 151 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) 152 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) 153 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) 154 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) 155 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) 156 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) 157 #define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000) 158 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) 159 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) 160 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000) 161 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 162 #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 163 #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 164 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000) 165 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000) 166 #define CPU_FTR_SPE ASM_CONST(0x0000000002000000) 167 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000) 168 #define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000) 169 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000) 170 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000) 171 172 /* 173 * Add the 64-bit processor unique features in the top half of the word; 174 * on 32-bit, make the names available but defined to be 0. 175 */ 176 #ifdef __powerpc64__ 177 #define LONG_ASM_CONST(x) ASM_CONST(x) 178 #else 179 #define LONG_ASM_CONST(x) 0 180 #endif 181 182 183 #define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x0000000800000000) 184 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000001000000000) 185 #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000) 186 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) 187 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) 188 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) 189 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) 190 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) 191 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000) 192 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000) 193 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000) 194 #define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000) 195 #define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000) 196 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000) 197 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000) 198 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000) 199 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000) 200 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000) 201 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000) 202 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000) 203 204 #ifndef __ASSEMBLY__ 205 206 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 207 208 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \ 209 MMU_FTR_16M_PAGE) 210 211 /* We only set the altivec features if the kernel was compiled with altivec 212 * support 213 */ 214 #ifdef CONFIG_ALTIVEC 215 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 216 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 217 #else 218 #define CPU_FTR_ALTIVEC_COMP 0 219 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 220 #endif 221 222 /* We only set the VSX features if the kernel was compiled with VSX 223 * support 224 */ 225 #ifdef CONFIG_VSX 226 #define CPU_FTR_VSX_COMP CPU_FTR_VSX 227 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 228 #else 229 #define CPU_FTR_VSX_COMP 0 230 #define PPC_FEATURE_HAS_VSX_COMP 0 231 #endif 232 233 /* We only set the spe features if the kernel was compiled with spe 234 * support 235 */ 236 #ifdef CONFIG_SPE 237 #define CPU_FTR_SPE_COMP CPU_FTR_SPE 238 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 239 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 240 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 241 #else 242 #define CPU_FTR_SPE_COMP 0 243 #define PPC_FEATURE_HAS_SPE_COMP 0 244 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 245 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 246 #endif 247 248 /* We need to mark all pages as being coherent if we're SMP or we have a 249 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 250 * require it for PCI "streaming/prefetch" to work properly. 251 * This is also required by 52xx family. 252 */ 253 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 254 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 255 || defined(CONFIG_PPC_MPC52xx) 256 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 257 #else 258 #define CPU_FTR_COMMON 0 259 #endif 260 261 /* The powersave features NAP & DOZE seems to confuse BDI when 262 debugging. So if a BDI is used, disable theses 263 */ 264 #ifndef CONFIG_BDI_SWITCH 265 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 266 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 267 #else 268 #define CPU_FTR_MAYBE_CAN_DOZE 0 269 #define CPU_FTR_MAYBE_CAN_NAP 0 270 #endif 271 272 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ 273 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ 274 !defined(CONFIG_BOOKE)) 275 276 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ 277 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 278 #define CPU_FTRS_603 (CPU_FTR_COMMON | \ 279 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 280 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 281 #define CPU_FTRS_604 (CPU_FTR_COMMON | \ 282 CPU_FTR_USE_TB | CPU_FTR_PPC_LE) 283 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 284 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 285 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 286 #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 287 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 288 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 289 CPU_FTR_PPC_LE) 290 #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 291 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 292 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 293 CPU_FTR_PPC_LE) 294 #define CPU_FTRS_750CL (CPU_FTRS_750) 295 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 296 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 297 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 298 #define CPU_FTRS_750GX (CPU_FTRS_750FX) 299 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 300 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 301 CPU_FTR_ALTIVEC_COMP | \ 302 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 303 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 304 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 305 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 306 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 307 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 308 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 309 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 311 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 312 CPU_FTR_USE_TB | \ 313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 316 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 317 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 318 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 320 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 321 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 322 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 323 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 324 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 325 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 326 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 327 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 328 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 329 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 330 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 331 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 332 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 333 CPU_FTR_USE_TB | \ 334 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 335 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 336 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 337 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 338 CPU_FTR_USE_TB | \ 339 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 340 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 341 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 342 CPU_FTR_NEED_PAIRED_STWCX) 343 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 344 CPU_FTR_USE_TB | \ 345 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 346 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 347 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 348 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 349 CPU_FTR_USE_TB | \ 350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 351 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 352 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 353 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 354 CPU_FTR_USE_TB | \ 355 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 356 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 357 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 358 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 359 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 360 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 361 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) 362 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 363 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 364 CPU_FTR_COMMON) 365 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 366 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 367 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 368 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) 369 #define CPU_FTRS_8XX (CPU_FTR_USE_TB) 370 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 371 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 372 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 373 CPU_FTR_INDEXED_DCR) 374 #define CPU_FTRS_47X (CPU_FTRS_440x6) 375 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 376 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 377 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE) 378 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 379 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 380 CPU_FTR_NOEXECUTE) 381 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 382 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 383 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 384 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 385 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 386 CPU_FTR_DBELL) 387 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 388 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 389 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 390 CPU_FTR_DEBUG_LVL_EXC) 391 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 392 393 /* 64-bit CPUs */ 394 #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \ 395 CPU_FTR_IABR | CPU_FTR_PPC_LE) 396 #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \ 397 CPU_FTR_IABR | \ 398 CPU_FTR_MMCRA | CPU_FTR_CTRL) 399 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 400 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 401 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \ 402 CPU_FTR_STCX_CHECKS_ADDRESS) 403 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 405 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 406 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS) 407 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 409 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 410 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 411 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB) 412 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 414 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 415 CPU_FTR_COHERENT_ICACHE | \ 416 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 417 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 418 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR) 419 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 420 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\ 421 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 422 CPU_FTR_COHERENT_ICACHE | \ 423 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 424 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 425 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 426 CPU_FTR_ICSWX | CPU_FTR_CFAR) 427 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 428 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 429 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 430 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 431 CPU_FTR_UNALIGNED_LD_STD) 432 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 433 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 434 CPU_FTR_PURR | CPU_FTR_REAL_LE) 435 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 436 437 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ 438 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 439 440 #ifdef __powerpc64__ 441 #ifdef CONFIG_PPC_BOOK3E 442 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E5500 | CPU_FTRS_A2) 443 #else 444 #define CPU_FTRS_POSSIBLE \ 445 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 446 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ 447 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 448 CPU_FTR_VSX) 449 #endif 450 #else 451 enum { 452 CPU_FTRS_POSSIBLE = 453 #if CLASSIC_PPC 454 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 455 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 456 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 457 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 458 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 459 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 460 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 461 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 462 CPU_FTRS_CLASSIC32 | 463 #else 464 CPU_FTRS_GENERIC_32 | 465 #endif 466 #ifdef CONFIG_8xx 467 CPU_FTRS_8XX | 468 #endif 469 #ifdef CONFIG_40x 470 CPU_FTRS_40X | 471 #endif 472 #ifdef CONFIG_44x 473 CPU_FTRS_44X | CPU_FTRS_440x6 | 474 #endif 475 #ifdef CONFIG_PPC_47x 476 CPU_FTRS_47X | CPU_FTR_476_DD2 | 477 #endif 478 #ifdef CONFIG_E200 479 CPU_FTRS_E200 | 480 #endif 481 #ifdef CONFIG_E500 482 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC | 483 CPU_FTRS_E5500 | 484 #endif 485 0, 486 }; 487 #endif /* __powerpc64__ */ 488 489 #ifdef __powerpc64__ 490 #ifdef CONFIG_PPC_BOOK3E 491 #define CPU_FTRS_ALWAYS (CPU_FTRS_E5500 & CPU_FTRS_A2) 492 #else 493 #define CPU_FTRS_ALWAYS \ 494 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 495 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ 496 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE) 497 #endif 498 #else 499 enum { 500 CPU_FTRS_ALWAYS = 501 #if CLASSIC_PPC 502 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 503 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 504 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 505 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 506 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 507 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 508 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 509 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 510 CPU_FTRS_CLASSIC32 & 511 #else 512 CPU_FTRS_GENERIC_32 & 513 #endif 514 #ifdef CONFIG_8xx 515 CPU_FTRS_8XX & 516 #endif 517 #ifdef CONFIG_40x 518 CPU_FTRS_40X & 519 #endif 520 #ifdef CONFIG_44x 521 CPU_FTRS_44X & CPU_FTRS_440x6 & 522 #endif 523 #ifdef CONFIG_E200 524 CPU_FTRS_E200 & 525 #endif 526 #ifdef CONFIG_E500 527 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC & 528 CPU_FTRS_E5500 & 529 #endif 530 CPU_FTRS_POSSIBLE, 531 }; 532 #endif /* __powerpc64__ */ 533 534 static inline int cpu_has_feature(unsigned long feature) 535 { 536 return (CPU_FTRS_ALWAYS & feature) || 537 (CPU_FTRS_POSSIBLE 538 & cur_cpu_spec->cpu_features 539 & feature); 540 } 541 542 #ifdef CONFIG_HAVE_HW_BREAKPOINT 543 #define HBP_NUM 1 544 #endif /* CONFIG_HAVE_HW_BREAKPOINT */ 545 546 #endif /* !__ASSEMBLY__ */ 547 548 #endif /* __KERNEL__ */ 549 #endif /* __ASM_POWERPC_CPUTABLE_H */ 550