1b8b572e1SStephen Rothwell #ifndef __ASM_POWERPC_CPUTABLE_H 2b8b572e1SStephen Rothwell #define __ASM_POWERPC_CPUTABLE_H 3b8b572e1SStephen Rothwell 4b8b572e1SStephen Rothwell 56574ba95SMichael Ellerman #include <linux/types.h> 6b8b572e1SStephen Rothwell #include <asm/asm-compat.h> 7b8b572e1SStephen Rothwell #include <asm/feature-fixups.h> 8c3617f72SDavid Howells #include <uapi/asm/cputable.h> 9b8b572e1SStephen Rothwell 10b8b572e1SStephen Rothwell #ifndef __ASSEMBLY__ 11b8b572e1SStephen Rothwell 12b8b572e1SStephen Rothwell /* This structure can grow, it's real size is used by head.S code 13b8b572e1SStephen Rothwell * via the mkdefs mechanism. 14b8b572e1SStephen Rothwell */ 15b8b572e1SStephen Rothwell struct cpu_spec; 16b8b572e1SStephen Rothwell 17b8b572e1SStephen Rothwell typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 18b8b572e1SStephen Rothwell typedef void (*cpu_restore_t)(void); 19b8b572e1SStephen Rothwell 20b8b572e1SStephen Rothwell enum powerpc_oprofile_type { 21b8b572e1SStephen Rothwell PPC_OPROFILE_INVALID = 0, 22b8b572e1SStephen Rothwell PPC_OPROFILE_RS64 = 1, 23b8b572e1SStephen Rothwell PPC_OPROFILE_POWER4 = 2, 24b8b572e1SStephen Rothwell PPC_OPROFILE_G4 = 3, 25b8b572e1SStephen Rothwell PPC_OPROFILE_FSL_EMB = 4, 26b8b572e1SStephen Rothwell PPC_OPROFILE_CELL = 5, 27b8b572e1SStephen Rothwell PPC_OPROFILE_PA6T = 6, 28b8b572e1SStephen Rothwell }; 29b8b572e1SStephen Rothwell 30b8b572e1SStephen Rothwell enum powerpc_pmc_type { 31b8b572e1SStephen Rothwell PPC_PMC_DEFAULT = 0, 32b8b572e1SStephen Rothwell PPC_PMC_IBM = 1, 33b8b572e1SStephen Rothwell PPC_PMC_PA6T = 2, 34b950bdd0SBenjamin Herrenschmidt PPC_PMC_G4 = 3, 35b8b572e1SStephen Rothwell }; 36b8b572e1SStephen Rothwell 37b8b572e1SStephen Rothwell struct pt_regs; 38b8b572e1SStephen Rothwell 39b8b572e1SStephen Rothwell extern int machine_check_generic(struct pt_regs *regs); 40b8b572e1SStephen Rothwell extern int machine_check_4xx(struct pt_regs *regs); 41b8b572e1SStephen Rothwell extern int machine_check_440A(struct pt_regs *regs); 42fe04b112SScott Wood extern int machine_check_e500mc(struct pt_regs *regs); 43b8b572e1SStephen Rothwell extern int machine_check_e500(struct pt_regs *regs); 44b8b572e1SStephen Rothwell extern int machine_check_e200(struct pt_regs *regs); 45fc5e7097SDave Kleikamp extern int machine_check_47x(struct pt_regs *regs); 46e627f8dcSChristophe Leroy int machine_check_8xx(struct pt_regs *regs); 47b8b572e1SStephen Rothwell 48e7affb1dSchenhui zhao extern void cpu_down_flush_e500v2(void); 49e7affb1dSchenhui zhao extern void cpu_down_flush_e500mc(void); 50e7affb1dSchenhui zhao extern void cpu_down_flush_e5500(void); 51e7affb1dSchenhui zhao extern void cpu_down_flush_e6500(void); 52e7affb1dSchenhui zhao 53b8b572e1SStephen Rothwell /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 54b8b572e1SStephen Rothwell struct cpu_spec { 55b8b572e1SStephen Rothwell /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 56b8b572e1SStephen Rothwell unsigned int pvr_mask; 57b8b572e1SStephen Rothwell unsigned int pvr_value; 58b8b572e1SStephen Rothwell 59b8b572e1SStephen Rothwell char *cpu_name; 60b8b572e1SStephen Rothwell unsigned long cpu_features; /* Kernel features */ 61b8b572e1SStephen Rothwell unsigned int cpu_user_features; /* Userland features */ 622171364dSMichael Neuling unsigned int cpu_user_features2; /* Userland features v2 */ 637c03d653SBenjamin Herrenschmidt unsigned int mmu_features; /* MMU features */ 64b8b572e1SStephen Rothwell 65b8b572e1SStephen Rothwell /* cache line sizes */ 66b8b572e1SStephen Rothwell unsigned int icache_bsize; 67b8b572e1SStephen Rothwell unsigned int dcache_bsize; 68b8b572e1SStephen Rothwell 69e7affb1dSchenhui zhao /* flush caches inside the current cpu */ 70e7affb1dSchenhui zhao void (*cpu_down_flush)(void); 71e7affb1dSchenhui zhao 72b8b572e1SStephen Rothwell /* number of performance monitor counters */ 73b8b572e1SStephen Rothwell unsigned int num_pmcs; 74b8b572e1SStephen Rothwell enum powerpc_pmc_type pmc_type; 75b8b572e1SStephen Rothwell 76b8b572e1SStephen Rothwell /* this is called to initialize various CPU bits like L1 cache, 77b8b572e1SStephen Rothwell * BHT, SPD, etc... from head.S before branching to identify_machine 78b8b572e1SStephen Rothwell */ 79b8b572e1SStephen Rothwell cpu_setup_t cpu_setup; 80b8b572e1SStephen Rothwell /* Used to restore cpu setup on secondary processors and at resume */ 81b8b572e1SStephen Rothwell cpu_restore_t cpu_restore; 82b8b572e1SStephen Rothwell 83b8b572e1SStephen Rothwell /* Used by oprofile userspace to select the right counters */ 84b8b572e1SStephen Rothwell char *oprofile_cpu_type; 85b8b572e1SStephen Rothwell 86b8b572e1SStephen Rothwell /* Processor specific oprofile operations */ 87b8b572e1SStephen Rothwell enum powerpc_oprofile_type oprofile_type; 88b8b572e1SStephen Rothwell 89b8b572e1SStephen Rothwell /* Bit locations inside the mmcra change */ 90b8b572e1SStephen Rothwell unsigned long oprofile_mmcra_sihv; 91b8b572e1SStephen Rothwell unsigned long oprofile_mmcra_sipr; 92b8b572e1SStephen Rothwell 93b8b572e1SStephen Rothwell /* Bits to clear during an oprofile exception */ 94b8b572e1SStephen Rothwell unsigned long oprofile_mmcra_clear; 95b8b572e1SStephen Rothwell 96b8b572e1SStephen Rothwell /* Name of processor class, for the ELF AT_PLATFORM entry */ 97b8b572e1SStephen Rothwell char *platform; 98b8b572e1SStephen Rothwell 99b8b572e1SStephen Rothwell /* Processor specific machine check handling. Return negative 100b8b572e1SStephen Rothwell * if the error is fatal, 1 if it was fully recovered and 0 to 101b8b572e1SStephen Rothwell * pass up (not CPU originated) */ 102b8b572e1SStephen Rothwell int (*machine_check)(struct pt_regs *regs); 1034c703416SMahesh Salgaonkar 1044c703416SMahesh Salgaonkar /* 1054c703416SMahesh Salgaonkar * Processor specific early machine check handler which is 1064c703416SMahesh Salgaonkar * called in real mode to handle SLB and TLB errors. 1074c703416SMahesh Salgaonkar */ 1084c703416SMahesh Salgaonkar long (*machine_check_early)(struct pt_regs *regs); 1094c703416SMahesh Salgaonkar 11004407050SMahesh Salgaonkar /* 11104407050SMahesh Salgaonkar * Processor specific routine to flush tlbs. 11204407050SMahesh Salgaonkar */ 11345706bb5SMahesh Salgaonkar void (*flush_tlb)(unsigned int action); 11404407050SMahesh Salgaonkar 115b8b572e1SStephen Rothwell }; 116b8b572e1SStephen Rothwell 117b8b572e1SStephen Rothwell extern struct cpu_spec *cur_cpu_spec; 118b8b572e1SStephen Rothwell 119b8b572e1SStephen Rothwell extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 120b8b572e1SStephen Rothwell 1215a61ef74SNicholas Piggin extern void set_cur_cpu_spec(struct cpu_spec *s); 122b8b572e1SStephen Rothwell extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 1235a61ef74SNicholas Piggin extern void identify_cpu_name(unsigned int pvr); 124b8b572e1SStephen Rothwell extern void do_feature_fixups(unsigned long value, void *fixup_start, 125b8b572e1SStephen Rothwell void *fixup_end); 126b8b572e1SStephen Rothwell 127b8b572e1SStephen Rothwell extern const char *powerpc_base_platform; 128b8b572e1SStephen Rothwell 1294db73271SKevin Hao #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 1304db73271SKevin Hao extern void cpu_feature_keys_init(void); 1314db73271SKevin Hao #else 1324db73271SKevin Hao static inline void cpu_feature_keys_init(void) { } 1334db73271SKevin Hao #endif 1344db73271SKevin Hao 13545706bb5SMahesh Salgaonkar /* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */ 13645706bb5SMahesh Salgaonkar enum { 13745706bb5SMahesh Salgaonkar TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */ 13845706bb5SMahesh Salgaonkar TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */ 13945706bb5SMahesh Salgaonkar }; 14045706bb5SMahesh Salgaonkar 141b8b572e1SStephen Rothwell #endif /* __ASSEMBLY__ */ 142b8b572e1SStephen Rothwell 143b8b572e1SStephen Rothwell /* CPU kernel features */ 144b8b572e1SStephen Rothwell 145b8b572e1SStephen Rothwell /* Retain the 32b definitions all use bottom half of word */ 146cde4d494SMichael Neuling #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 147cde4d494SMichael Neuling #define CPU_FTR_L2CR ASM_CONST(0x00000002) 148cde4d494SMichael Neuling #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004) 149cde4d494SMichael Neuling #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008) 150cde4d494SMichael Neuling #define CPU_FTR_TAU ASM_CONST(0x00000010) 151cde4d494SMichael Neuling #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020) 152cde4d494SMichael Neuling #define CPU_FTR_USE_TB ASM_CONST(0x00000040) 153cde4d494SMichael Neuling #define CPU_FTR_L2CSR ASM_CONST(0x00000080) 154cde4d494SMichael Neuling #define CPU_FTR_601 ASM_CONST(0x00000100) 155cde4d494SMichael Neuling #define CPU_FTR_DBELL ASM_CONST(0x00000200) 156cde4d494SMichael Neuling #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400) 157cde4d494SMichael Neuling #define CPU_FTR_L3CR ASM_CONST(0x00000800) 158cde4d494SMichael Neuling #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000) 159cde4d494SMichael Neuling #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000) 160cde4d494SMichael Neuling #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000) 161cde4d494SMichael Neuling #define CPU_FTR_NO_DPM ASM_CONST(0x00008000) 162cde4d494SMichael Neuling #define CPU_FTR_476_DD2 ASM_CONST(0x00010000) 163cde4d494SMichael Neuling #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000) 164cde4d494SMichael Neuling #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000) 165cde4d494SMichael Neuling #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000) 166cde4d494SMichael Neuling #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000) 167cde4d494SMichael Neuling #define CPU_FTR_PPC_LE ASM_CONST(0x00200000) 168cde4d494SMichael Neuling #define CPU_FTR_REAL_LE ASM_CONST(0x00400000) 169cde4d494SMichael Neuling #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000) 170cde4d494SMichael Neuling #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000) 171cde4d494SMichael Neuling #define CPU_FTR_SPE ASM_CONST(0x02000000) 172cde4d494SMichael Neuling #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000) 173cde4d494SMichael Neuling #define CPU_FTR_LWSYNC ASM_CONST(0x08000000) 174cde4d494SMichael Neuling #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000) 175cde4d494SMichael Neuling #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000) 176cde4d494SMichael Neuling #define CPU_FTR_EMB_HV ASM_CONST(0x40000000) 177b8b572e1SStephen Rothwell 178b8b572e1SStephen Rothwell /* 179b8b572e1SStephen Rothwell * Add the 64-bit processor unique features in the top half of the word; 180b8b572e1SStephen Rothwell * on 32-bit, make the names available but defined to be 0. 181b8b572e1SStephen Rothwell */ 182b8b572e1SStephen Rothwell #ifdef __powerpc64__ 183b8b572e1SStephen Rothwell #define LONG_ASM_CONST(x) ASM_CONST(x) 184b8b572e1SStephen Rothwell #else 185b8b572e1SStephen Rothwell #define LONG_ASM_CONST(x) 0 186b8b572e1SStephen Rothwell #endif 187b8b572e1SStephen Rothwell 1881580b3b8SMichael Neuling #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000) 1891580b3b8SMichael Neuling #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000) 1901580b3b8SMichael Neuling #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000) 1911de2bd4eSMichael Ellerman #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000) 192c3ab300eSMichael Neuling #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000) 1931580b3b8SMichael Neuling #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000) 1941580b3b8SMichael Neuling #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000) 1951580b3b8SMichael Neuling #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000) 1961580b3b8SMichael Neuling #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000) 1971580b3b8SMichael Neuling #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000) 1981580b3b8SMichael Neuling #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000) 1991580b3b8SMichael Neuling #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000) 2001580b3b8SMichael Neuling #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000) 2011580b3b8SMichael Neuling #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000) 2021580b3b8SMichael Neuling #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000) 2031580b3b8SMichael Neuling #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000) 2041580b3b8SMichael Neuling #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000) 2051580b3b8SMichael Neuling #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000) 2061580b3b8SMichael Neuling #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000) 2071580b3b8SMichael Neuling #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000) 2081580b3b8SMichael Neuling #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000) 2091580b3b8SMichael Neuling #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000) 2101580b3b8SMichael Neuling #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000) 2111580b3b8SMichael Neuling #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000) 2121de2bd4eSMichael Ellerman #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) 2131580b3b8SMichael Neuling #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) 21479879c17SMichael Neuling #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) 21582a9f16aSMichael Neuling #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000) 21668f2f0d4SMichael Ellerman #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000) 2177dccfbc3SAneesh Kumar K.V #define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000) 218b8b572e1SStephen Rothwell 219b8b572e1SStephen Rothwell #ifndef __ASSEMBLY__ 220b8b572e1SStephen Rothwell 22144ae3ab3SMatt Evans #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 22244ae3ab3SMatt Evans 22313b3d13bSMichael Ellerman #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) 224b8b572e1SStephen Rothwell 225b8b572e1SStephen Rothwell /* We only set the altivec features if the kernel was compiled with altivec 226b8b572e1SStephen Rothwell * support 227b8b572e1SStephen Rothwell */ 228b8b572e1SStephen Rothwell #ifdef CONFIG_ALTIVEC 229b8b572e1SStephen Rothwell #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 230b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 231b8b572e1SStephen Rothwell #else 232b8b572e1SStephen Rothwell #define CPU_FTR_ALTIVEC_COMP 0 233b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 234b8b572e1SStephen Rothwell #endif 235b8b572e1SStephen Rothwell 236b8b572e1SStephen Rothwell /* We only set the VSX features if the kernel was compiled with VSX 237b8b572e1SStephen Rothwell * support 238b8b572e1SStephen Rothwell */ 239b8b572e1SStephen Rothwell #ifdef CONFIG_VSX 240b8b572e1SStephen Rothwell #define CPU_FTR_VSX_COMP CPU_FTR_VSX 241b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 242b8b572e1SStephen Rothwell #else 243b8b572e1SStephen Rothwell #define CPU_FTR_VSX_COMP 0 244b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_VSX_COMP 0 245b8b572e1SStephen Rothwell #endif 246b8b572e1SStephen Rothwell 247b8b572e1SStephen Rothwell /* We only set the spe features if the kernel was compiled with spe 248b8b572e1SStephen Rothwell * support 249b8b572e1SStephen Rothwell */ 250b8b572e1SStephen Rothwell #ifdef CONFIG_SPE 251b8b572e1SStephen Rothwell #define CPU_FTR_SPE_COMP CPU_FTR_SPE 252b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 253b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 254b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 255b8b572e1SStephen Rothwell #else 256b8b572e1SStephen Rothwell #define CPU_FTR_SPE_COMP 0 257b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_SPE_COMP 0 258b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 259b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 260b8b572e1SStephen Rothwell #endif 261b8b572e1SStephen Rothwell 2626a6d541fSMichael Neuling /* We only set the TM feature if the kernel was compiled with TM supprt */ 2636a6d541fSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 2646a6d541fSMichael Neuling #define CPU_FTR_TM_COMP CPU_FTR_TM 265cbbc6f1bSNishanth Aravamudan #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 266b4b56f9eSSam bobroff #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC 2676a6d541fSMichael Neuling #else 2686a6d541fSMichael Neuling #define CPU_FTR_TM_COMP 0 269cbbc6f1bSNishanth Aravamudan #define PPC_FEATURE2_HTM_COMP 0 270b4b56f9eSSam bobroff #define PPC_FEATURE2_HTM_NOSC_COMP 0 2716a6d541fSMichael Neuling #endif 2726a6d541fSMichael Neuling 273b8b572e1SStephen Rothwell /* We need to mark all pages as being coherent if we're SMP or we have a 274b8b572e1SStephen Rothwell * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 275b8b572e1SStephen Rothwell * require it for PCI "streaming/prefetch" to work properly. 276c9310920SPiotr Ziecik * This is also required by 52xx family. 277b8b572e1SStephen Rothwell */ 278b8b572e1SStephen Rothwell #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 279c9310920SPiotr Ziecik || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 280c9310920SPiotr Ziecik || defined(CONFIG_PPC_MPC52xx) 281b8b572e1SStephen Rothwell #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 282b8b572e1SStephen Rothwell #else 283b8b572e1SStephen Rothwell #define CPU_FTR_COMMON 0 284b8b572e1SStephen Rothwell #endif 285b8b572e1SStephen Rothwell 286b8b572e1SStephen Rothwell /* The powersave features NAP & DOZE seems to confuse BDI when 287b8b572e1SStephen Rothwell debugging. So if a BDI is used, disable theses 288b8b572e1SStephen Rothwell */ 289b8b572e1SStephen Rothwell #ifndef CONFIG_BDI_SWITCH 290b8b572e1SStephen Rothwell #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 291b8b572e1SStephen Rothwell #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 292b8b572e1SStephen Rothwell #else 293b8b572e1SStephen Rothwell #define CPU_FTR_MAYBE_CAN_DOZE 0 294b8b572e1SStephen Rothwell #define CPU_FTR_MAYBE_CAN_NAP 0 295b8b572e1SStephen Rothwell #endif 296b8b572e1SStephen Rothwell 2977c03d653SBenjamin Herrenschmidt #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ 298b8b572e1SStephen Rothwell CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) 299b8b572e1SStephen Rothwell #define CPU_FTRS_603 (CPU_FTR_COMMON | \ 300b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 301b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 302b8b572e1SStephen Rothwell #define CPU_FTRS_604 (CPU_FTR_COMMON | \ 3037c03d653SBenjamin Herrenschmidt CPU_FTR_USE_TB | CPU_FTR_PPC_LE) 304b8b572e1SStephen Rothwell #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 305b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 3067c03d653SBenjamin Herrenschmidt CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 307b8b572e1SStephen Rothwell #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 308b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 3097c03d653SBenjamin Herrenschmidt CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 310b8b572e1SStephen Rothwell CPU_FTR_PPC_LE) 311b8b572e1SStephen Rothwell #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 312b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 3137c03d653SBenjamin Herrenschmidt CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 314b8b572e1SStephen Rothwell CPU_FTR_PPC_LE) 3157c03d653SBenjamin Herrenschmidt #define CPU_FTRS_750CL (CPU_FTRS_750) 316b8b572e1SStephen Rothwell #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 317b8b572e1SStephen Rothwell #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 3187c03d653SBenjamin Herrenschmidt #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 319b8b572e1SStephen Rothwell #define CPU_FTRS_750GX (CPU_FTRS_750FX) 320b8b572e1SStephen Rothwell #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 321b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 3227c03d653SBenjamin Herrenschmidt CPU_FTR_ALTIVEC_COMP | \ 323b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 324b8b572e1SStephen Rothwell #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 325b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ 3267c03d653SBenjamin Herrenschmidt CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 327b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 328b8b572e1SStephen Rothwell #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 329b8b572e1SStephen Rothwell CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3307c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 331b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 332b8b572e1SStephen Rothwell #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 333b8b572e1SStephen Rothwell CPU_FTR_USE_TB | \ 334b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3357c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 336b8b572e1SStephen Rothwell CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 337b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 338b8b572e1SStephen Rothwell #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 339b8b572e1SStephen Rothwell CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 340b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3417c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 342b8b572e1SStephen Rothwell CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 343b8b572e1SStephen Rothwell #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 344b8b572e1SStephen Rothwell CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 345b8b572e1SStephen Rothwell CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 3467c03d653SBenjamin Herrenschmidt CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 347b8b572e1SStephen Rothwell #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 348b8b572e1SStephen Rothwell CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ 349b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3507c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 351b8b572e1SStephen Rothwell CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 3527c03d653SBenjamin Herrenschmidt CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 353b8b572e1SStephen Rothwell #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 354b8b572e1SStephen Rothwell CPU_FTR_USE_TB | \ 355b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3567c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 357b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 358b8b572e1SStephen Rothwell #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 359b8b572e1SStephen Rothwell CPU_FTR_USE_TB | \ 360b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3617c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 362b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 363b8b572e1SStephen Rothwell CPU_FTR_NEED_PAIRED_STWCX) 364b8b572e1SStephen Rothwell #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 365b8b572e1SStephen Rothwell CPU_FTR_USE_TB | \ 366b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3677c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 368b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 369b8b572e1SStephen Rothwell #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 370b8b572e1SStephen Rothwell CPU_FTR_USE_TB | \ 371b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3727c03d653SBenjamin Herrenschmidt CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 373b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 374b8b572e1SStephen Rothwell #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 375b8b572e1SStephen Rothwell CPU_FTR_USE_TB | \ 376b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3777c03d653SBenjamin Herrenschmidt CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 378b8b572e1SStephen Rothwell CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 379b8b572e1SStephen Rothwell #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ 380b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) 381b8b572e1SStephen Rothwell #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 3827c03d653SBenjamin Herrenschmidt CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) 383b8b572e1SStephen Rothwell #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 3847c03d653SBenjamin Herrenschmidt CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 385b8b572e1SStephen Rothwell CPU_FTR_COMMON) 386b8b572e1SStephen Rothwell #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 3877c03d653SBenjamin Herrenschmidt CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ 388b8b572e1SStephen Rothwell CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) 3897c03d653SBenjamin Herrenschmidt #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) 3905b2753fcSLEROY Christophe #define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE) 3918309ce72SBenjamin Herrenschmidt #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 3928309ce72SBenjamin Herrenschmidt #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 3936d2170beSBenjamin Herrenschmidt #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 3946d2170beSBenjamin Herrenschmidt CPU_FTR_INDEXED_DCR) 395e7f75ad0SDave Kleikamp #define CPU_FTRS_47X (CPU_FTRS_440x6) 396b8b572e1SStephen Rothwell #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \ 397b8b572e1SStephen Rothwell CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 39852b066faSScott Wood CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \ 39952b066faSScott Wood CPU_FTR_DEBUG_LVL_EXC) 400b8b572e1SStephen Rothwell #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 4018309ce72SBenjamin Herrenschmidt CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 4028309ce72SBenjamin Herrenschmidt CPU_FTR_NOEXECUTE) 403b8b572e1SStephen Rothwell #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ 4047c03d653SBenjamin Herrenschmidt CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 4058309ce72SBenjamin Herrenschmidt CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 406d51ad915SScott Wood #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 407620165f9SKumar Gala CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 40873196cd3SScott Wood CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 409d52459caSScott Wood /* 410d52459caSScott Wood * e5500/e6500 erratum A-006958 is a timebase bug that can use the 411d52459caSScott Wood * same workaround as CPU_FTR_CELL_TB_BUG. 412d52459caSScott Wood */ 41311ed0db9SKumar Gala #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 41411ed0db9SKumar Gala CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 415d36b4c4fSKumar Gala CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 416d52459caSScott Wood CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 41710241842SKumar Gala #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 41810241842SKumar Gala CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 41910241842SKumar Gala CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 420d52459caSScott Wood CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 421e16c8765SAndy Fleming CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) 422b8b572e1SStephen Rothwell #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 423b8b572e1SStephen Rothwell 424b8b572e1SStephen Rothwell /* 64-bit CPUs */ 425b8b572e1SStephen Rothwell #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 4267c03d653SBenjamin Herrenschmidt CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 427f89451fbSAnton Blanchard CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \ 428f89451fbSAnton Blanchard CPU_FTR_STCX_CHECKS_ADDRESS) 429b8b572e1SStephen Rothwell #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 430969391c5SPaul Mackerras CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ 4312a929436SMark Nelson CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 432969391c5SPaul Mackerras CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 43382a9f16aSMichael Neuling CPU_FTR_HVMODE | CPU_FTR_DABRX) 434b8b572e1SStephen Rothwell #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 4357c03d653SBenjamin Herrenschmidt CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 436b8b572e1SStephen Rothwell CPU_FTR_MMCRA | CPU_FTR_SMT | \ 43744ae3ab3SMatt Evans CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 43882a9f16aSMichael Neuling CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 439b8b572e1SStephen Rothwell #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 4407c03d653SBenjamin Herrenschmidt CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 441b8b572e1SStephen Rothwell CPU_FTR_MMCRA | CPU_FTR_SMT | \ 44244ae3ab3SMatt Evans CPU_FTR_COHERENT_ICACHE | \ 443b8b572e1SStephen Rothwell CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 444f89451fbSAnton Blanchard CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 44582a9f16aSMichael Neuling CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 44682a9f16aSMichael Neuling CPU_FTR_DABRX) 447b8b572e1SStephen Rothwell #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 448969391c5SPaul Mackerras CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 449b8b572e1SStephen Rothwell CPU_FTR_MMCRA | CPU_FTR_SMT | \ 45044ae3ab3SMatt Evans CPU_FTR_COHERENT_ICACHE | \ 451b8b572e1SStephen Rothwell CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 452f89451fbSAnton Blanchard CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 453851d2e2fSTseng-Hui (Frank) Lin CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 454d2613868SHaren Myneni CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 45582a9f16aSMichael Neuling CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX) 45671e18497SMichael Neuling #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 45771e18497SMichael Neuling CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 45871e18497SMichael Neuling CPU_FTR_MMCRA | CPU_FTR_SMT | \ 45971e18497SMichael Neuling CPU_FTR_COHERENT_ICACHE | \ 46071e18497SMichael Neuling CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 46171e18497SMichael Neuling CPU_FTR_DSCR | CPU_FTR_SAO | \ 46271e18497SMichael Neuling CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 463e5e84f0aSIan Munsie CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 4641de2bd4eSMichael Ellerman CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 4650e5e7f5eSMichael Ellerman CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP) 46668f2f0d4SMichael Ellerman #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) 467bd6ba351SJoel Stanley #define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL) 468c3ab300eSMichael Neuling #define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 469c3ab300eSMichael Neuling CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 470c3ab300eSMichael Neuling CPU_FTR_MMCRA | CPU_FTR_SMT | \ 471c3ab300eSMichael Neuling CPU_FTR_COHERENT_ICACHE | \ 472c3ab300eSMichael Neuling CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 473c3ab300eSMichael Neuling CPU_FTR_DSCR | CPU_FTR_SAO | \ 474c3ab300eSMichael Neuling CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 4752384d2d7SNicholas Piggin CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 476c3ab300eSMichael Neuling CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 477c3ab300eSMichael Neuling CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300) 478ca80d5d0SNicholas Piggin #define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \ 479ca80d5d0SNicholas Piggin (~CPU_FTR_SAO)) 480b8b572e1SStephen Rothwell #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 4817c03d653SBenjamin Herrenschmidt CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 482b8b572e1SStephen Rothwell CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 48344ae3ab3SMatt Evans CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 48482a9f16aSMichael Neuling CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 485b8b572e1SStephen Rothwell #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 48644ae3ab3SMatt Evans CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 48782a9f16aSMichael Neuling CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 4887c03d653SBenjamin Herrenschmidt #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 489b8b572e1SStephen Rothwell 490b8b572e1SStephen Rothwell #ifdef __powerpc64__ 49111ed0db9SKumar Gala #ifdef CONFIG_PPC_BOOK3E 49290029640SMichael Ellerman #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) 49311ed0db9SKumar Gala #else 494b8b572e1SStephen Rothwell #define CPU_FTRS_POSSIBLE \ 495468a3302SMichael Ellerman (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \ 496468a3302SMichael Ellerman CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \ 4973609e09fSMichael Ellerman CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \ 4987dccfbc3SAneesh Kumar K.V CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD1) 49911ed0db9SKumar Gala #endif 500b8b572e1SStephen Rothwell #else 501b8b572e1SStephen Rothwell enum { 502b8b572e1SStephen Rothwell CPU_FTRS_POSSIBLE = 5031e07a0a0SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_32 504b8b572e1SStephen Rothwell CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 505b8b572e1SStephen Rothwell CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 506b8b572e1SStephen Rothwell CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 507b8b572e1SStephen Rothwell CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 508b8b572e1SStephen Rothwell CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 509b8b572e1SStephen Rothwell CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 510b8b572e1SStephen Rothwell CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 511b8b572e1SStephen Rothwell CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 512b8b572e1SStephen Rothwell CPU_FTRS_CLASSIC32 | 513b8b572e1SStephen Rothwell #else 514b8b572e1SStephen Rothwell CPU_FTRS_GENERIC_32 | 515b8b572e1SStephen Rothwell #endif 516*968159c0SChristophe Leroy #ifdef CONFIG_PPC_8xx 517b8b572e1SStephen Rothwell CPU_FTRS_8XX | 518b8b572e1SStephen Rothwell #endif 519b8b572e1SStephen Rothwell #ifdef CONFIG_40x 520b8b572e1SStephen Rothwell CPU_FTRS_40X | 521b8b572e1SStephen Rothwell #endif 522b8b572e1SStephen Rothwell #ifdef CONFIG_44x 5236d2170beSBenjamin Herrenschmidt CPU_FTRS_44X | CPU_FTRS_440x6 | 524b8b572e1SStephen Rothwell #endif 525e7f75ad0SDave Kleikamp #ifdef CONFIG_PPC_47x 526c48d0dbaSDave Kleikamp CPU_FTRS_47X | CPU_FTR_476_DD2 | 527e7f75ad0SDave Kleikamp #endif 528b8b572e1SStephen Rothwell #ifdef CONFIG_E200 529b8b572e1SStephen Rothwell CPU_FTRS_E200 | 530b8b572e1SStephen Rothwell #endif 531b8b572e1SStephen Rothwell #ifdef CONFIG_E500 53206aae867SScott Wood CPU_FTRS_E500 | CPU_FTRS_E500_2 | 53306aae867SScott Wood #endif 53406aae867SScott Wood #ifdef CONFIG_PPC_E500MC 53506aae867SScott Wood CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 536b8b572e1SStephen Rothwell #endif 537b8b572e1SStephen Rothwell 0, 538b8b572e1SStephen Rothwell }; 539b8b572e1SStephen Rothwell #endif /* __powerpc64__ */ 540b8b572e1SStephen Rothwell 541b8b572e1SStephen Rothwell #ifdef __powerpc64__ 54211ed0db9SKumar Gala #ifdef CONFIG_PPC_BOOK3E 54390029640SMichael Ellerman #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) 54411ed0db9SKumar Gala #else 545b8b572e1SStephen Rothwell #define CPU_FTRS_ALWAYS \ 546468a3302SMichael Ellerman (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \ 547468a3302SMichael Ellerman CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \ 5483609e09fSMichael Ellerman CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \ 549c3ab300eSMichael Neuling CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \ 550c3ab300eSMichael Neuling CPU_FTRS_POWER9) 55111ed0db9SKumar Gala #endif 552b8b572e1SStephen Rothwell #else 553b8b572e1SStephen Rothwell enum { 554b8b572e1SStephen Rothwell CPU_FTRS_ALWAYS = 5551e07a0a0SMichael Ellerman #ifdef CONFIG_PPC_BOOK3S_32 556b8b572e1SStephen Rothwell CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 557b8b572e1SStephen Rothwell CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 558b8b572e1SStephen Rothwell CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 559b8b572e1SStephen Rothwell CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 560b8b572e1SStephen Rothwell CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 561b8b572e1SStephen Rothwell CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 562b8b572e1SStephen Rothwell CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 563b8b572e1SStephen Rothwell CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 564b8b572e1SStephen Rothwell CPU_FTRS_CLASSIC32 & 565b8b572e1SStephen Rothwell #else 566b8b572e1SStephen Rothwell CPU_FTRS_GENERIC_32 & 567b8b572e1SStephen Rothwell #endif 568*968159c0SChristophe Leroy #ifdef CONFIG_PPC_8xx 569b8b572e1SStephen Rothwell CPU_FTRS_8XX & 570b8b572e1SStephen Rothwell #endif 571b8b572e1SStephen Rothwell #ifdef CONFIG_40x 572b8b572e1SStephen Rothwell CPU_FTRS_40X & 573b8b572e1SStephen Rothwell #endif 574b8b572e1SStephen Rothwell #ifdef CONFIG_44x 5756d2170beSBenjamin Herrenschmidt CPU_FTRS_44X & CPU_FTRS_440x6 & 576b8b572e1SStephen Rothwell #endif 577b8b572e1SStephen Rothwell #ifdef CONFIG_E200 578b8b572e1SStephen Rothwell CPU_FTRS_E200 & 579b8b572e1SStephen Rothwell #endif 580b8b572e1SStephen Rothwell #ifdef CONFIG_E500 58106aae867SScott Wood CPU_FTRS_E500 & CPU_FTRS_E500_2 & 58206aae867SScott Wood #endif 58306aae867SScott Wood #ifdef CONFIG_PPC_E500MC 58406aae867SScott Wood CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 585b8b572e1SStephen Rothwell #endif 58673196cd3SScott Wood ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 587b8b572e1SStephen Rothwell CPU_FTRS_POSSIBLE, 588b8b572e1SStephen Rothwell }; 589b8b572e1SStephen Rothwell #endif /* __powerpc64__ */ 590b8b572e1SStephen Rothwell 5915aae8a53SK.Prasad #define HBP_NUM 1 5925aae8a53SK.Prasad 593b8b572e1SStephen Rothwell #endif /* !__ASSEMBLY__ */ 594b8b572e1SStephen Rothwell 595b8b572e1SStephen Rothwell #endif /* __ASM_POWERPC_CPUTABLE_H */ 596