1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2b8b572e1SStephen Rothwell #ifndef __ASM_POWERPC_CPUTABLE_H 3b8b572e1SStephen Rothwell #define __ASM_POWERPC_CPUTABLE_H 4b8b572e1SStephen Rothwell 5b8b572e1SStephen Rothwell 66574ba95SMichael Ellerman #include <linux/types.h> 7c3617f72SDavid Howells #include <uapi/asm/cputable.h> 8ec0c464cSChristophe Leroy #include <asm/asm-const.h> 9b8b572e1SStephen Rothwell 10b8b572e1SStephen Rothwell #ifndef __ASSEMBLY__ 11b8b572e1SStephen Rothwell 12388692e9SMadhavan Srinivasan /* 13388692e9SMadhavan Srinivasan * Added to include __machine_check_early_realmode_* functions 14388692e9SMadhavan Srinivasan */ 15388692e9SMadhavan Srinivasan #include <asm/mce.h> 16388692e9SMadhavan Srinivasan 17b8b572e1SStephen Rothwell /* This structure can grow, it's real size is used by head.S code 18b8b572e1SStephen Rothwell * via the mkdefs mechanism. 19b8b572e1SStephen Rothwell */ 20b8b572e1SStephen Rothwell struct cpu_spec; 21b8b572e1SStephen Rothwell 22b8b572e1SStephen Rothwell typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 23b8b572e1SStephen Rothwell typedef void (*cpu_restore_t)(void); 24b8b572e1SStephen Rothwell 25b8b572e1SStephen Rothwell enum powerpc_oprofile_type { 26b8b572e1SStephen Rothwell PPC_OPROFILE_INVALID = 0, 27b8b572e1SStephen Rothwell PPC_OPROFILE_RS64 = 1, 28b8b572e1SStephen Rothwell PPC_OPROFILE_POWER4 = 2, 29b8b572e1SStephen Rothwell PPC_OPROFILE_G4 = 3, 30b8b572e1SStephen Rothwell PPC_OPROFILE_FSL_EMB = 4, 31b8b572e1SStephen Rothwell PPC_OPROFILE_CELL = 5, 32b8b572e1SStephen Rothwell PPC_OPROFILE_PA6T = 6, 33b8b572e1SStephen Rothwell }; 34b8b572e1SStephen Rothwell 35b8b572e1SStephen Rothwell enum powerpc_pmc_type { 36b8b572e1SStephen Rothwell PPC_PMC_DEFAULT = 0, 37b8b572e1SStephen Rothwell PPC_PMC_IBM = 1, 38b8b572e1SStephen Rothwell PPC_PMC_PA6T = 2, 39b950bdd0SBenjamin Herrenschmidt PPC_PMC_G4 = 3, 40b8b572e1SStephen Rothwell }; 41b8b572e1SStephen Rothwell 42b8b572e1SStephen Rothwell struct pt_regs; 43b8b572e1SStephen Rothwell 44b8b572e1SStephen Rothwell extern int machine_check_generic(struct pt_regs *regs); 45b8b572e1SStephen Rothwell extern int machine_check_4xx(struct pt_regs *regs); 46b8b572e1SStephen Rothwell extern int machine_check_440A(struct pt_regs *regs); 47fe04b112SScott Wood extern int machine_check_e500mc(struct pt_regs *regs); 48b8b572e1SStephen Rothwell extern int machine_check_e500(struct pt_regs *regs); 49b8b572e1SStephen Rothwell extern int machine_check_e200(struct pt_regs *regs); 50fc5e7097SDave Kleikamp extern int machine_check_47x(struct pt_regs *regs); 51e627f8dcSChristophe Leroy int machine_check_8xx(struct pt_regs *regs); 520deae39cSChristophe Leroy int machine_check_83xx(struct pt_regs *regs); 53b8b572e1SStephen Rothwell 54e7affb1dSchenhui zhao extern void cpu_down_flush_e500v2(void); 55e7affb1dSchenhui zhao extern void cpu_down_flush_e500mc(void); 56e7affb1dSchenhui zhao extern void cpu_down_flush_e5500(void); 57e7affb1dSchenhui zhao extern void cpu_down_flush_e6500(void); 58e7affb1dSchenhui zhao 59b8b572e1SStephen Rothwell /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 60b8b572e1SStephen Rothwell struct cpu_spec { 61b8b572e1SStephen Rothwell /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 62b8b572e1SStephen Rothwell unsigned int pvr_mask; 63b8b572e1SStephen Rothwell unsigned int pvr_value; 64b8b572e1SStephen Rothwell 65b8b572e1SStephen Rothwell char *cpu_name; 66b8b572e1SStephen Rothwell unsigned long cpu_features; /* Kernel features */ 67b8b572e1SStephen Rothwell unsigned int cpu_user_features; /* Userland features */ 682171364dSMichael Neuling unsigned int cpu_user_features2; /* Userland features v2 */ 697c03d653SBenjamin Herrenschmidt unsigned int mmu_features; /* MMU features */ 70b8b572e1SStephen Rothwell 71b8b572e1SStephen Rothwell /* cache line sizes */ 72b8b572e1SStephen Rothwell unsigned int icache_bsize; 73b8b572e1SStephen Rothwell unsigned int dcache_bsize; 74b8b572e1SStephen Rothwell 75e7affb1dSchenhui zhao /* flush caches inside the current cpu */ 76e7affb1dSchenhui zhao void (*cpu_down_flush)(void); 77e7affb1dSchenhui zhao 78b8b572e1SStephen Rothwell /* number of performance monitor counters */ 79b8b572e1SStephen Rothwell unsigned int num_pmcs; 80b8b572e1SStephen Rothwell enum powerpc_pmc_type pmc_type; 81b8b572e1SStephen Rothwell 82b8b572e1SStephen Rothwell /* this is called to initialize various CPU bits like L1 cache, 83b8b572e1SStephen Rothwell * BHT, SPD, etc... from head.S before branching to identify_machine 84b8b572e1SStephen Rothwell */ 85b8b572e1SStephen Rothwell cpu_setup_t cpu_setup; 86b8b572e1SStephen Rothwell /* Used to restore cpu setup on secondary processors and at resume */ 87b8b572e1SStephen Rothwell cpu_restore_t cpu_restore; 88b8b572e1SStephen Rothwell 89b8b572e1SStephen Rothwell /* Used by oprofile userspace to select the right counters */ 90b8b572e1SStephen Rothwell char *oprofile_cpu_type; 91b8b572e1SStephen Rothwell 92b8b572e1SStephen Rothwell /* Processor specific oprofile operations */ 93b8b572e1SStephen Rothwell enum powerpc_oprofile_type oprofile_type; 94b8b572e1SStephen Rothwell 95b8b572e1SStephen Rothwell /* Bit locations inside the mmcra change */ 96b8b572e1SStephen Rothwell unsigned long oprofile_mmcra_sihv; 97b8b572e1SStephen Rothwell unsigned long oprofile_mmcra_sipr; 98b8b572e1SStephen Rothwell 99b8b572e1SStephen Rothwell /* Bits to clear during an oprofile exception */ 100b8b572e1SStephen Rothwell unsigned long oprofile_mmcra_clear; 101b8b572e1SStephen Rothwell 102b8b572e1SStephen Rothwell /* Name of processor class, for the ELF AT_PLATFORM entry */ 103b8b572e1SStephen Rothwell char *platform; 104b8b572e1SStephen Rothwell 105b8b572e1SStephen Rothwell /* Processor specific machine check handling. Return negative 106b8b572e1SStephen Rothwell * if the error is fatal, 1 if it was fully recovered and 0 to 107b8b572e1SStephen Rothwell * pass up (not CPU originated) */ 108b8b572e1SStephen Rothwell int (*machine_check)(struct pt_regs *regs); 1094c703416SMahesh Salgaonkar 1104c703416SMahesh Salgaonkar /* 1114c703416SMahesh Salgaonkar * Processor specific early machine check handler which is 1124c703416SMahesh Salgaonkar * called in real mode to handle SLB and TLB errors. 1134c703416SMahesh Salgaonkar */ 1144c703416SMahesh Salgaonkar long (*machine_check_early)(struct pt_regs *regs); 115b8b572e1SStephen Rothwell }; 116b8b572e1SStephen Rothwell 117b8b572e1SStephen Rothwell extern struct cpu_spec *cur_cpu_spec; 118b8b572e1SStephen Rothwell 119b8b572e1SStephen Rothwell extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 120b8b572e1SStephen Rothwell 1215a61ef74SNicholas Piggin extern void set_cur_cpu_spec(struct cpu_spec *s); 122b8b572e1SStephen Rothwell extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 1235a61ef74SNicholas Piggin extern void identify_cpu_name(unsigned int pvr); 124b8b572e1SStephen Rothwell extern void do_feature_fixups(unsigned long value, void *fixup_start, 125b8b572e1SStephen Rothwell void *fixup_end); 126b8b572e1SStephen Rothwell 127b8b572e1SStephen Rothwell extern const char *powerpc_base_platform; 128b8b572e1SStephen Rothwell 1294db73271SKevin Hao #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 1304db73271SKevin Hao extern void cpu_feature_keys_init(void); 1314db73271SKevin Hao #else 1324db73271SKevin Hao static inline void cpu_feature_keys_init(void) { } 1334db73271SKevin Hao #endif 1344db73271SKevin Hao 135b8b572e1SStephen Rothwell #endif /* __ASSEMBLY__ */ 136b8b572e1SStephen Rothwell 137b8b572e1SStephen Rothwell /* CPU kernel features */ 138b8b572e1SStephen Rothwell 1399bbf0b57SPaul Mackerras /* Definitions for features that we have on both 32-bit and 64-bit chips */ 140cde4d494SMichael Neuling #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 1419bbf0b57SPaul Mackerras #define CPU_FTR_ALTIVEC ASM_CONST(0x00000002) 1429bbf0b57SPaul Mackerras #define CPU_FTR_DBELL ASM_CONST(0x00000004) 1439bbf0b57SPaul Mackerras #define CPU_FTR_CAN_NAP ASM_CONST(0x00000008) 1449bbf0b57SPaul Mackerras #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010) 1459bbf0b57SPaul Mackerras #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020) 1469bbf0b57SPaul Mackerras #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040) 1479bbf0b57SPaul Mackerras #define CPU_FTR_LWSYNC ASM_CONST(0x00000080) 1489bbf0b57SPaul Mackerras #define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100) 1499bbf0b57SPaul Mackerras #define CPU_FTR_EMB_HV ASM_CONST(0x00000200) 1509bbf0b57SPaul Mackerras 1519bbf0b57SPaul Mackerras /* Definitions for features that only exist on 32-bit chips */ 1529bbf0b57SPaul Mackerras #ifdef CONFIG_PPC32 1539bbf0b57SPaul Mackerras #define CPU_FTR_L2CR ASM_CONST(0x00002000) 1549bbf0b57SPaul Mackerras #define CPU_FTR_SPEC7450 ASM_CONST(0x00004000) 1559bbf0b57SPaul Mackerras #define CPU_FTR_TAU ASM_CONST(0x00008000) 1569bbf0b57SPaul Mackerras #define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000) 1579bbf0b57SPaul Mackerras #define CPU_FTR_L3CR ASM_CONST(0x00040000) 1589bbf0b57SPaul Mackerras #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000) 1599bbf0b57SPaul Mackerras #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000) 1609bbf0b57SPaul Mackerras #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000) 1619bbf0b57SPaul Mackerras #define CPU_FTR_NO_DPM ASM_CONST(0x00400000) 1629bbf0b57SPaul Mackerras #define CPU_FTR_476_DD2 ASM_CONST(0x00800000) 1639bbf0b57SPaul Mackerras #define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000) 1649bbf0b57SPaul Mackerras #define CPU_FTR_NO_BTIC ASM_CONST(0x02000000) 1659bbf0b57SPaul Mackerras #define CPU_FTR_PPC_LE ASM_CONST(0x04000000) 1669bbf0b57SPaul Mackerras #define CPU_FTR_SPE ASM_CONST(0x10000000) 1679bbf0b57SPaul Mackerras #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000) 1689bbf0b57SPaul Mackerras #define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000) 1699bbf0b57SPaul Mackerras 1709bbf0b57SPaul Mackerras #else /* CONFIG_PPC32 */ 1719bbf0b57SPaul Mackerras /* Define these to 0 for the sake of tests in common code */ 1729bbf0b57SPaul Mackerras #define CPU_FTR_PPC_LE (0) 1739bbf0b57SPaul Mackerras #endif 174b8b572e1SStephen Rothwell 175b8b572e1SStephen Rothwell /* 1769bbf0b57SPaul Mackerras * Definitions for the 64-bit processor unique features; 177b8b572e1SStephen Rothwell * on 32-bit, make the names available but defined to be 0. 178b8b572e1SStephen Rothwell */ 179b8b572e1SStephen Rothwell #ifdef __powerpc64__ 180b8b572e1SStephen Rothwell #define LONG_ASM_CONST(x) ASM_CONST(x) 181b8b572e1SStephen Rothwell #else 182b8b572e1SStephen Rothwell #define LONG_ASM_CONST(x) 0 183b8b572e1SStephen Rothwell #endif 184b8b572e1SStephen Rothwell 1859bbf0b57SPaul Mackerras #define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000) 1869bbf0b57SPaul Mackerras #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000) 1879bbf0b57SPaul Mackerras #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000) 1889bbf0b57SPaul Mackerras #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000) 1899bbf0b57SPaul Mackerras #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000) 1909bbf0b57SPaul Mackerras #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000) 1919bbf0b57SPaul Mackerras #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000) 1929bbf0b57SPaul Mackerras #define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000) 1939bbf0b57SPaul Mackerras #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000) 1949bbf0b57SPaul Mackerras #define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000) 1959bbf0b57SPaul Mackerras #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000) 1969bbf0b57SPaul Mackerras #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000) 1979bbf0b57SPaul Mackerras #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000) 1989bbf0b57SPaul Mackerras #define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000) 199*12564485SShawn Anastasio #define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000) 2009bbf0b57SPaul Mackerras #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000) 2019bbf0b57SPaul Mackerras #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000) 2029bbf0b57SPaul Mackerras #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000) 2039bbf0b57SPaul Mackerras #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000) 2049bbf0b57SPaul Mackerras #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000) 2059bbf0b57SPaul Mackerras #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000) 206a24204c3SAneesh Kumar K.V /* LONG_ASM_CONST(0x0000000400000000) Free */ 2079bbf0b57SPaul Mackerras #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000) 2089bbf0b57SPaul Mackerras #define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000) 2099bbf0b57SPaul Mackerras #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000) 2109bbf0b57SPaul Mackerras #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000) 2119bbf0b57SPaul Mackerras #define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000) 2129bbf0b57SPaul Mackerras #define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000) 2139bbf0b57SPaul Mackerras #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000) 2149bbf0b57SPaul Mackerras #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000) 215b5af4f27SPaul Mackerras #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000) 216b5af4f27SPaul Mackerras #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000) 21709ce98caSAneesh Kumar K.V #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000) 21881984428SAlastair D'Silva #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000) 219047e6575SAneesh Kumar K.V #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000) 220736bcdd3SJordan Niethe #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000) 2213fd5836eSAlistair Popple #define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000) 222dc1cedcaSRavi Bangoria #define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000) 223b8b572e1SStephen Rothwell 224b8b572e1SStephen Rothwell #ifndef __ASSEMBLY__ 225b8b572e1SStephen Rothwell 22644ae3ab3SMatt Evans #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 22744ae3ab3SMatt Evans 22813b3d13bSMichael Ellerman #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) 229b8b572e1SStephen Rothwell 230b8b572e1SStephen Rothwell /* We only set the altivec features if the kernel was compiled with altivec 231b8b572e1SStephen Rothwell * support 232b8b572e1SStephen Rothwell */ 233b8b572e1SStephen Rothwell #ifdef CONFIG_ALTIVEC 234b8b572e1SStephen Rothwell #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 235b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 236b8b572e1SStephen Rothwell #else 237b8b572e1SStephen Rothwell #define CPU_FTR_ALTIVEC_COMP 0 238b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 239b8b572e1SStephen Rothwell #endif 240b8b572e1SStephen Rothwell 241b8b572e1SStephen Rothwell /* We only set the VSX features if the kernel was compiled with VSX 242b8b572e1SStephen Rothwell * support 243b8b572e1SStephen Rothwell */ 244b8b572e1SStephen Rothwell #ifdef CONFIG_VSX 245b8b572e1SStephen Rothwell #define CPU_FTR_VSX_COMP CPU_FTR_VSX 246b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 247b8b572e1SStephen Rothwell #else 248b8b572e1SStephen Rothwell #define CPU_FTR_VSX_COMP 0 249b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_VSX_COMP 0 250b8b572e1SStephen Rothwell #endif 251b8b572e1SStephen Rothwell 252b8b572e1SStephen Rothwell /* We only set the spe features if the kernel was compiled with spe 253b8b572e1SStephen Rothwell * support 254b8b572e1SStephen Rothwell */ 255b8b572e1SStephen Rothwell #ifdef CONFIG_SPE 256b8b572e1SStephen Rothwell #define CPU_FTR_SPE_COMP CPU_FTR_SPE 257b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 258b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 259b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 260b8b572e1SStephen Rothwell #else 261b8b572e1SStephen Rothwell #define CPU_FTR_SPE_COMP 0 262b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_SPE_COMP 0 263b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 264b8b572e1SStephen Rothwell #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 265b8b572e1SStephen Rothwell #endif 266b8b572e1SStephen Rothwell 2676a6d541fSMichael Neuling /* We only set the TM feature if the kernel was compiled with TM supprt */ 2686a6d541fSMichael Neuling #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 2696a6d541fSMichael Neuling #define CPU_FTR_TM_COMP CPU_FTR_TM 270cbbc6f1bSNishanth Aravamudan #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 271b4b56f9eSSam bobroff #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC 2726a6d541fSMichael Neuling #else 2736a6d541fSMichael Neuling #define CPU_FTR_TM_COMP 0 274cbbc6f1bSNishanth Aravamudan #define PPC_FEATURE2_HTM_COMP 0 275b4b56f9eSSam bobroff #define PPC_FEATURE2_HTM_NOSC_COMP 0 2766a6d541fSMichael Neuling #endif 2776a6d541fSMichael Neuling 278b8b572e1SStephen Rothwell /* We need to mark all pages as being coherent if we're SMP or we have a 279b8b572e1SStephen Rothwell * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 280b8b572e1SStephen Rothwell * require it for PCI "streaming/prefetch" to work properly. 281c9310920SPiotr Ziecik * This is also required by 52xx family. 282b8b572e1SStephen Rothwell */ 283b8b572e1SStephen Rothwell #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 284c9310920SPiotr Ziecik || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 285c9310920SPiotr Ziecik || defined(CONFIG_PPC_MPC52xx) 286b8b572e1SStephen Rothwell #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 287b8b572e1SStephen Rothwell #else 288b8b572e1SStephen Rothwell #define CPU_FTR_COMMON 0 289b8b572e1SStephen Rothwell #endif 290b8b572e1SStephen Rothwell 291b8b572e1SStephen Rothwell /* The powersave features NAP & DOZE seems to confuse BDI when 292b8b572e1SStephen Rothwell debugging. So if a BDI is used, disable theses 293b8b572e1SStephen Rothwell */ 294b8b572e1SStephen Rothwell #ifndef CONFIG_BDI_SWITCH 295b8b572e1SStephen Rothwell #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 296b8b572e1SStephen Rothwell #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 297b8b572e1SStephen Rothwell #else 298b8b572e1SStephen Rothwell #define CPU_FTR_MAYBE_CAN_DOZE 0 299b8b572e1SStephen Rothwell #define CPU_FTR_MAYBE_CAN_NAP 0 300b8b572e1SStephen Rothwell #endif 301b8b572e1SStephen Rothwell 30212c3f1fdSChristophe Leroy #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | \ 303e0291f1dSChristophe Leroy CPU_FTR_COHERENT_ICACHE) 304c0d64cf9SPaul Mackerras #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 305385e89d5SChristophe Leroy CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE) 306c0d64cf9SPaul Mackerras #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE) 307b8b572e1SStephen Rothwell #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 308c0d64cf9SPaul Mackerras CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 3097c03d653SBenjamin Herrenschmidt CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 310b8b572e1SStephen Rothwell #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 311c0d64cf9SPaul Mackerras CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 3127c03d653SBenjamin Herrenschmidt CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 313b8b572e1SStephen Rothwell CPU_FTR_PPC_LE) 314b8b572e1SStephen Rothwell #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 315c0d64cf9SPaul Mackerras CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 3167c03d653SBenjamin Herrenschmidt CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 317b8b572e1SStephen Rothwell CPU_FTR_PPC_LE) 3187c03d653SBenjamin Herrenschmidt #define CPU_FTRS_750CL (CPU_FTRS_750) 319b8b572e1SStephen Rothwell #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 320b8b572e1SStephen Rothwell #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 3217c03d653SBenjamin Herrenschmidt #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 322b8b572e1SStephen Rothwell #define CPU_FTRS_750GX (CPU_FTRS_750FX) 323b8b572e1SStephen Rothwell #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 324c0d64cf9SPaul Mackerras CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 3257c03d653SBenjamin Herrenschmidt CPU_FTR_ALTIVEC_COMP | \ 326b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 327b8b572e1SStephen Rothwell #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 328c0d64cf9SPaul Mackerras CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 3297c03d653SBenjamin Herrenschmidt CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 330b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 331b8b572e1SStephen Rothwell #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 332c0d64cf9SPaul Mackerras CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3337c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 334b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 335b8b572e1SStephen Rothwell #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 336b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3377c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 338b8b572e1SStephen Rothwell CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 339b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 340b8b572e1SStephen Rothwell #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 341c0d64cf9SPaul Mackerras CPU_FTR_NEED_PAIRED_STWCX | \ 342b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3437c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 344b8b572e1SStephen Rothwell CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 345b8b572e1SStephen Rothwell #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 346c0d64cf9SPaul Mackerras CPU_FTR_NEED_PAIRED_STWCX | \ 347b8b572e1SStephen Rothwell CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 3487c03d653SBenjamin Herrenschmidt CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 349b8b572e1SStephen Rothwell #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 350c0d64cf9SPaul Mackerras CPU_FTR_NEED_PAIRED_STWCX | \ 351b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3527c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 353b8b572e1SStephen Rothwell CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 3547c03d653SBenjamin Herrenschmidt CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 355b8b572e1SStephen Rothwell #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 356b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3577c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 358b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 359b8b572e1SStephen Rothwell #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 360b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3617c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 362b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 363b8b572e1SStephen Rothwell CPU_FTR_NEED_PAIRED_STWCX) 364b8b572e1SStephen Rothwell #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 365b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3667c03d653SBenjamin Herrenschmidt CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 367b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 368b8b572e1SStephen Rothwell #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 369b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3707c03d653SBenjamin Herrenschmidt CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 371b8b572e1SStephen Rothwell CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 372b8b572e1SStephen Rothwell #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 373b8b572e1SStephen Rothwell CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 3747c03d653SBenjamin Herrenschmidt CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 375b8b572e1SStephen Rothwell CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 376385e89d5SChristophe Leroy #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE) 377b8b572e1SStephen Rothwell #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 378c0d64cf9SPaul Mackerras CPU_FTR_MAYBE_CAN_NAP) 379b8b572e1SStephen Rothwell #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 380c0d64cf9SPaul Mackerras CPU_FTR_MAYBE_CAN_NAP | \ 381385e89d5SChristophe Leroy CPU_FTR_COMMON | CPU_FTR_NOEXECUTE) 382b8b572e1SStephen Rothwell #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 383c0d64cf9SPaul Mackerras CPU_FTR_MAYBE_CAN_NAP | \ 384385e89d5SChristophe Leroy CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE) 385c0d64cf9SPaul Mackerras #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON) 386c0d64cf9SPaul Mackerras #define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE) 387c0d64cf9SPaul Mackerras #define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 388c0d64cf9SPaul Mackerras #define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 389c0d64cf9SPaul Mackerras #define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 3906d2170beSBenjamin Herrenschmidt CPU_FTR_INDEXED_DCR) 391e7f75ad0SDave Kleikamp #define CPU_FTRS_47X (CPU_FTRS_440x6) 392c0d64cf9SPaul Mackerras #define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \ 393b8b572e1SStephen Rothwell CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 394e0291f1dSChristophe Leroy CPU_FTR_NOEXECUTE | \ 39552b066faSScott Wood CPU_FTR_DEBUG_LVL_EXC) 396c0d64cf9SPaul Mackerras #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \ 3978309ce72SBenjamin Herrenschmidt CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 3988309ce72SBenjamin Herrenschmidt CPU_FTR_NOEXECUTE) 399c0d64cf9SPaul Mackerras #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \ 4007c03d653SBenjamin Herrenschmidt CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 4018309ce72SBenjamin Herrenschmidt CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 402c0d64cf9SPaul Mackerras #define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \ 403dd0efb3fSPaul Mackerras CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 40473196cd3SScott Wood CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 405d52459caSScott Wood /* 406d52459caSScott Wood * e5500/e6500 erratum A-006958 is a timebase bug that can use the 407d52459caSScott Wood * same workaround as CPU_FTR_CELL_TB_BUG. 408d52459caSScott Wood */ 409c0d64cf9SPaul Mackerras #define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \ 410dd0efb3fSPaul Mackerras CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 411d36b4c4fSKumar Gala CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 412d52459caSScott Wood CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 413c0d64cf9SPaul Mackerras #define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \ 414dd0efb3fSPaul Mackerras CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 41510241842SKumar Gala CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 416d52459caSScott Wood CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 417e16c8765SAndy Fleming CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) 418b8b572e1SStephen Rothwell #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 419b8b572e1SStephen Rothwell 420b8b572e1SStephen Rothwell /* 64-bit CPUs */ 421c0d64cf9SPaul Mackerras #define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \ 4223735eb85SNicholas Piggin CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 4232a929436SMark Nelson CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 424969391c5SPaul Mackerras CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 42582a9f16aSMichael Neuling CPU_FTR_HVMODE | CPU_FTR_DABRX) 426c0d64cf9SPaul Mackerras #define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \ 4277c03d653SBenjamin Herrenschmidt CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 428b8b572e1SStephen Rothwell CPU_FTR_MMCRA | CPU_FTR_SMT | \ 42944ae3ab3SMatt Evans CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 43082a9f16aSMichael Neuling CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 431c0d64cf9SPaul Mackerras #define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \ 4327c03d653SBenjamin Herrenschmidt CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 433b8b572e1SStephen Rothwell CPU_FTR_MMCRA | CPU_FTR_SMT | \ 43444ae3ab3SMatt Evans CPU_FTR_COHERENT_ICACHE | \ 435b8b572e1SStephen Rothwell CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 436f89451fbSAnton Blanchard CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 43782a9f16aSMichael Neuling CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 43882a9f16aSMichael Neuling CPU_FTR_DABRX) 439c0d64cf9SPaul Mackerras #define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \ 440969391c5SPaul Mackerras CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 441b8b572e1SStephen Rothwell CPU_FTR_MMCRA | CPU_FTR_SMT | \ 44244ae3ab3SMatt Evans CPU_FTR_COHERENT_ICACHE | \ 443b8b572e1SStephen Rothwell CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 444*12564485SShawn Anastasio CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 445851d2e2fSTseng-Hui (Frank) Lin CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 446c1807e3fSMichael Ellerman CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 447a24204c3SAneesh Kumar K.V CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX ) 448c0d64cf9SPaul Mackerras #define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \ 44971e18497SMichael Neuling CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 45071e18497SMichael Neuling CPU_FTR_MMCRA | CPU_FTR_SMT | \ 45171e18497SMichael Neuling CPU_FTR_COHERENT_ICACHE | \ 45271e18497SMichael Neuling CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 453*12564485SShawn Anastasio CPU_FTR_DSCR | CPU_FTR_SAO | \ 45471e18497SMichael Neuling CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 455c1807e3fSMichael Ellerman CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 4561de2bd4eSMichael Ellerman CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 457a24204c3SAneesh Kumar K.V CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP ) 45868f2f0d4SMichael Ellerman #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) 459c0d64cf9SPaul Mackerras #define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \ 460c3ab300eSMichael Neuling CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 461c3ab300eSMichael Neuling CPU_FTR_MMCRA | CPU_FTR_SMT | \ 462c3ab300eSMichael Neuling CPU_FTR_COHERENT_ICACHE | \ 463c3ab300eSMichael Neuling CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 464*12564485SShawn Anastasio CPU_FTR_DSCR | CPU_FTR_SAO | \ 465c3ab300eSMichael Neuling CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 4662384d2d7SNicholas Piggin CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 46796541531SMichael Neuling CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ 468a24204c3SAneesh Kumar K.V CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \ 469a24204c3SAneesh Kumar K.V CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR) 470736bcdd3SJordan Niethe #define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG) 471736bcdd3SJordan Niethe #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \ 472736bcdd3SJordan Niethe CPU_FTR_P9_RADIX_PREFETCH_BUG | \ 473736bcdd3SJordan Niethe CPU_FTR_POWER9_DD2_1) 4743a52f601SNicholas Piggin #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \ 4753a52f601SNicholas Piggin CPU_FTR_P9_TM_HV_ASSIST | \ 476b5af4f27SPaul Mackerras CPU_FTR_P9_TM_XER_SO_BUG) 477a3ea40d5SAlistair Popple #define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \ 478a3ea40d5SAlistair Popple CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 479a3ea40d5SAlistair Popple CPU_FTR_MMCRA | CPU_FTR_SMT | \ 480a3ea40d5SAlistair Popple CPU_FTR_COHERENT_ICACHE | \ 481a3ea40d5SAlistair Popple CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 482*12564485SShawn Anastasio CPU_FTR_DSCR | CPU_FTR_SAO | \ 483a3ea40d5SAlistair Popple CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 484a3ea40d5SAlistair Popple CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 485a3ea40d5SAlistair Popple CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ 4868f460a81SRavi Bangoria CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \ 487dc1cedcaSRavi Bangoria CPU_FTR_DAWR | CPU_FTR_DAWR1) 488c0d64cf9SPaul Mackerras #define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \ 4897c03d653SBenjamin Herrenschmidt CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 490b8b572e1SStephen Rothwell CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 49144ae3ab3SMatt Evans CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 49282a9f16aSMichael Neuling CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 493c0d64cf9SPaul Mackerras #define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \ 49444ae3ab3SMatt Evans CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 49582a9f16aSMichael Neuling CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 496c0d64cf9SPaul Mackerras #define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2) 497b8b572e1SStephen Rothwell 498b8b572e1SStephen Rothwell #ifdef __powerpc64__ 49911ed0db9SKumar Gala #ifdef CONFIG_PPC_BOOK3E 50090029640SMichael Ellerman #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) 50111ed0db9SKumar Gala #else 502db5ae1c1SNicholas Piggin #ifdef CONFIG_CPU_LITTLE_ENDIAN 503db5ae1c1SNicholas Piggin #define CPU_FTRS_POSSIBLE \ 504db5ae1c1SNicholas Piggin (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \ 505e11b64b1SJoel Stanley CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \ 506a3ea40d5SAlistair Popple CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10) 507db5ae1c1SNicholas Piggin #else 508b8b572e1SStephen Rothwell #define CPU_FTRS_POSSIBLE \ 509471d7ff8SNicholas Piggin (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \ 510468a3302SMichael Ellerman CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \ 511e11b64b1SJoel Stanley CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 512e11b64b1SJoel Stanley CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \ 513a3ea40d5SAlistair Popple CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10) 514db5ae1c1SNicholas Piggin #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 51511ed0db9SKumar Gala #endif 516b8b572e1SStephen Rothwell #else 517b8b572e1SStephen Rothwell enum { 518b8b572e1SStephen Rothwell CPU_FTRS_POSSIBLE = 51912c3f1fdSChristophe Leroy #ifdef CONFIG_PPC_BOOK3S_601 52012c3f1fdSChristophe Leroy CPU_FTRS_PPC601 | 52112c3f1fdSChristophe Leroy #elif defined(CONFIG_PPC_BOOK3S_32) 522b8b572e1SStephen Rothwell CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 523b8b572e1SStephen Rothwell CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 524b8b572e1SStephen Rothwell CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 525b8b572e1SStephen Rothwell CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 526b8b572e1SStephen Rothwell CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 527b8b572e1SStephen Rothwell CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 528b8b572e1SStephen Rothwell CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 529b8b572e1SStephen Rothwell CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 530b8b572e1SStephen Rothwell CPU_FTRS_CLASSIC32 | 531b8b572e1SStephen Rothwell #else 532b8b572e1SStephen Rothwell CPU_FTRS_GENERIC_32 | 533b8b572e1SStephen Rothwell #endif 534968159c0SChristophe Leroy #ifdef CONFIG_PPC_8xx 535b8b572e1SStephen Rothwell CPU_FTRS_8XX | 536b8b572e1SStephen Rothwell #endif 537b8b572e1SStephen Rothwell #ifdef CONFIG_40x 538b8b572e1SStephen Rothwell CPU_FTRS_40X | 539b8b572e1SStephen Rothwell #endif 540b8b572e1SStephen Rothwell #ifdef CONFIG_44x 5416d2170beSBenjamin Herrenschmidt CPU_FTRS_44X | CPU_FTRS_440x6 | 542b8b572e1SStephen Rothwell #endif 543e7f75ad0SDave Kleikamp #ifdef CONFIG_PPC_47x 544c48d0dbaSDave Kleikamp CPU_FTRS_47X | CPU_FTR_476_DD2 | 545e7f75ad0SDave Kleikamp #endif 546b8b572e1SStephen Rothwell #ifdef CONFIG_E200 547b8b572e1SStephen Rothwell CPU_FTRS_E200 | 548b8b572e1SStephen Rothwell #endif 549b8b572e1SStephen Rothwell #ifdef CONFIG_E500 55006aae867SScott Wood CPU_FTRS_E500 | CPU_FTRS_E500_2 | 55106aae867SScott Wood #endif 55206aae867SScott Wood #ifdef CONFIG_PPC_E500MC 55306aae867SScott Wood CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 554b8b572e1SStephen Rothwell #endif 555b8b572e1SStephen Rothwell 0, 556b8b572e1SStephen Rothwell }; 557b8b572e1SStephen Rothwell #endif /* __powerpc64__ */ 558b8b572e1SStephen Rothwell 559b8b572e1SStephen Rothwell #ifdef __powerpc64__ 56011ed0db9SKumar Gala #ifdef CONFIG_PPC_BOOK3E 56190029640SMichael Ellerman #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) 56211ed0db9SKumar Gala #else 56381b654c2SMichael Ellerman 56481b654c2SMichael Ellerman #ifdef CONFIG_PPC_DT_CPU_FTRS 56581b654c2SMichael Ellerman #define CPU_FTRS_DT_CPU_BASE \ 56681b654c2SMichael Ellerman (CPU_FTR_LWSYNC | \ 56781b654c2SMichael Ellerman CPU_FTR_FPU_UNAVAILABLE | \ 56881b654c2SMichael Ellerman CPU_FTR_NODSISRALIGN | \ 56981b654c2SMichael Ellerman CPU_FTR_NOEXECUTE | \ 57081b654c2SMichael Ellerman CPU_FTR_COHERENT_ICACHE | \ 57181b654c2SMichael Ellerman CPU_FTR_STCX_CHECKS_ADDRESS | \ 57281b654c2SMichael Ellerman CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 57381b654c2SMichael Ellerman CPU_FTR_DAWR | \ 57481b654c2SMichael Ellerman CPU_FTR_ARCH_206 | \ 57581b654c2SMichael Ellerman CPU_FTR_ARCH_207S) 57681b654c2SMichael Ellerman #else 57781b654c2SMichael Ellerman #define CPU_FTRS_DT_CPU_BASE (~0ul) 57881b654c2SMichael Ellerman #endif 57981b654c2SMichael Ellerman 580db5ae1c1SNicholas Piggin #ifdef CONFIG_CPU_LITTLE_ENDIAN 581db5ae1c1SNicholas Piggin #define CPU_FTRS_ALWAYS \ 582db5ae1c1SNicholas Piggin (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \ 583ce57c661SMichael Ellerman CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \ 584ce57c661SMichael Ellerman CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE) 585db5ae1c1SNicholas Piggin #else 586b8b572e1SStephen Rothwell #define CPU_FTRS_ALWAYS \ 587471d7ff8SNicholas Piggin (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \ 588468a3302SMichael Ellerman CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \ 5893609e09fSMichael Ellerman CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \ 590ce57c661SMichael Ellerman ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \ 591ce57c661SMichael Ellerman CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE) 592db5ae1c1SNicholas Piggin #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 59311ed0db9SKumar Gala #endif 594b8b572e1SStephen Rothwell #else 595b8b572e1SStephen Rothwell enum { 596b8b572e1SStephen Rothwell CPU_FTRS_ALWAYS = 59712c3f1fdSChristophe Leroy #ifdef CONFIG_PPC_BOOK3S_601 59812c3f1fdSChristophe Leroy CPU_FTRS_PPC601 & 59912c3f1fdSChristophe Leroy #elif defined(CONFIG_PPC_BOOK3S_32) 60012c3f1fdSChristophe Leroy CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 601b8b572e1SStephen Rothwell CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 602b8b572e1SStephen Rothwell CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 603b8b572e1SStephen Rothwell CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 604b8b572e1SStephen Rothwell CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 605b8b572e1SStephen Rothwell CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 606b8b572e1SStephen Rothwell CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 607b8b572e1SStephen Rothwell CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 608b8b572e1SStephen Rothwell CPU_FTRS_CLASSIC32 & 609b8b572e1SStephen Rothwell #else 610b8b572e1SStephen Rothwell CPU_FTRS_GENERIC_32 & 611b8b572e1SStephen Rothwell #endif 612968159c0SChristophe Leroy #ifdef CONFIG_PPC_8xx 613b8b572e1SStephen Rothwell CPU_FTRS_8XX & 614b8b572e1SStephen Rothwell #endif 615b8b572e1SStephen Rothwell #ifdef CONFIG_40x 616b8b572e1SStephen Rothwell CPU_FTRS_40X & 617b8b572e1SStephen Rothwell #endif 618b8b572e1SStephen Rothwell #ifdef CONFIG_44x 6196d2170beSBenjamin Herrenschmidt CPU_FTRS_44X & CPU_FTRS_440x6 & 620b8b572e1SStephen Rothwell #endif 621b8b572e1SStephen Rothwell #ifdef CONFIG_E200 622b8b572e1SStephen Rothwell CPU_FTRS_E200 & 623b8b572e1SStephen Rothwell #endif 624b8b572e1SStephen Rothwell #ifdef CONFIG_E500 62506aae867SScott Wood CPU_FTRS_E500 & CPU_FTRS_E500_2 & 62606aae867SScott Wood #endif 62706aae867SScott Wood #ifdef CONFIG_PPC_E500MC 62806aae867SScott Wood CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 629b8b572e1SStephen Rothwell #endif 63073196cd3SScott Wood ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 631b8b572e1SStephen Rothwell CPU_FTRS_POSSIBLE, 632b8b572e1SStephen Rothwell }; 633b8b572e1SStephen Rothwell #endif /* __powerpc64__ */ 634b8b572e1SStephen Rothwell 635a6ba44e8SRavi Bangoria /* 636a6ba44e8SRavi Bangoria * Maximum number of hw breakpoint supported on powerpc. Number of 637deb2bd9bSRavi Bangoria * breakpoints supported by actual hw might be less than this, which 638deb2bd9bSRavi Bangoria * is decided at run time in nr_wp_slots(). 639a6ba44e8SRavi Bangoria */ 640deb2bd9bSRavi Bangoria #define HBP_NUM_MAX 2 6415aae8a53SK.Prasad 642b8b572e1SStephen Rothwell #endif /* !__ASSEMBLY__ */ 643b8b572e1SStephen Rothwell 644b8b572e1SStephen Rothwell #endif /* __ASM_POWERPC_CPUTABLE_H */ 645