1 /* 2 * Communication Processor Module v2. 3 * 4 * This file contains structures and information for the communication 5 * processor channels found in the dual port RAM or parameter RAM. 6 * All CPM control and status is available through the CPM2 internal 7 * memory map. See immap_cpm2.h for details. 8 */ 9 #ifdef __KERNEL__ 10 #ifndef __CPM2__ 11 #define __CPM2__ 12 13 #include <asm/immap_cpm2.h> 14 #include <asm/cpm.h> 15 #include <sysdev/fsl_soc.h> 16 17 #ifdef CONFIG_PPC_85xx 18 #define CPM_MAP_ADDR (get_immrbase() + 0x80000) 19 #endif 20 21 /* CPM Command register. 22 */ 23 #define CPM_CR_RST ((uint)0x80000000) 24 #define CPM_CR_PAGE ((uint)0x7c000000) 25 #define CPM_CR_SBLOCK ((uint)0x03e00000) 26 #define CPM_CR_FLG ((uint)0x00010000) 27 #define CPM_CR_MCN ((uint)0x00003fc0) 28 #define CPM_CR_OPCODE ((uint)0x0000000f) 29 30 /* Device sub-block and page codes. 31 */ 32 #define CPM_CR_SCC1_SBLOCK (0x04) 33 #define CPM_CR_SCC2_SBLOCK (0x05) 34 #define CPM_CR_SCC3_SBLOCK (0x06) 35 #define CPM_CR_SCC4_SBLOCK (0x07) 36 #define CPM_CR_SMC1_SBLOCK (0x08) 37 #define CPM_CR_SMC2_SBLOCK (0x09) 38 #define CPM_CR_SPI_SBLOCK (0x0a) 39 #define CPM_CR_I2C_SBLOCK (0x0b) 40 #define CPM_CR_TIMER_SBLOCK (0x0f) 41 #define CPM_CR_RAND_SBLOCK (0x0e) 42 #define CPM_CR_FCC1_SBLOCK (0x10) 43 #define CPM_CR_FCC2_SBLOCK (0x11) 44 #define CPM_CR_FCC3_SBLOCK (0x12) 45 #define CPM_CR_IDMA1_SBLOCK (0x14) 46 #define CPM_CR_IDMA2_SBLOCK (0x15) 47 #define CPM_CR_IDMA3_SBLOCK (0x16) 48 #define CPM_CR_IDMA4_SBLOCK (0x17) 49 #define CPM_CR_MCC1_SBLOCK (0x1c) 50 51 #define CPM_CR_FCC_SBLOCK(x) (x + 0x10) 52 53 #define CPM_CR_SCC1_PAGE (0x00) 54 #define CPM_CR_SCC2_PAGE (0x01) 55 #define CPM_CR_SCC3_PAGE (0x02) 56 #define CPM_CR_SCC4_PAGE (0x03) 57 #define CPM_CR_SMC1_PAGE (0x07) 58 #define CPM_CR_SMC2_PAGE (0x08) 59 #define CPM_CR_SPI_PAGE (0x09) 60 #define CPM_CR_I2C_PAGE (0x0a) 61 #define CPM_CR_TIMER_PAGE (0x0a) 62 #define CPM_CR_RAND_PAGE (0x0a) 63 #define CPM_CR_FCC1_PAGE (0x04) 64 #define CPM_CR_FCC2_PAGE (0x05) 65 #define CPM_CR_FCC3_PAGE (0x06) 66 #define CPM_CR_IDMA1_PAGE (0x07) 67 #define CPM_CR_IDMA2_PAGE (0x08) 68 #define CPM_CR_IDMA3_PAGE (0x09) 69 #define CPM_CR_IDMA4_PAGE (0x0a) 70 #define CPM_CR_MCC1_PAGE (0x07) 71 #define CPM_CR_MCC2_PAGE (0x08) 72 73 #define CPM_CR_FCC_PAGE(x) (x + 0x04) 74 75 /* CPM2-specific opcodes (see cpm.h for common opcodes) 76 */ 77 #define CPM_CR_START_IDMA ((ushort)0x0009) 78 79 #define mk_cr_cmd(PG, SBC, MCN, OP) \ 80 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) 81 82 /* The number of pages of host memory we allocate for CPM. This is 83 * done early in kernel initialization to get physically contiguous 84 * pages. 85 */ 86 #define NUM_CPM_HOST_PAGES 2 87 88 /* Export the base address of the communication processor registers 89 * and dual port ram. 90 */ 91 extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */ 92 93 #define cpm_dpalloc cpm_muram_alloc 94 #define cpm_dpfree cpm_muram_free 95 #define cpm_dpram_addr cpm_muram_addr 96 97 extern void cpm2_reset(void); 98 99 /* Baud rate generators. 100 */ 101 #define CPM_BRG_RST ((uint)0x00020000) 102 #define CPM_BRG_EN ((uint)0x00010000) 103 #define CPM_BRG_EXTC_INT ((uint)0x00000000) 104 #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) 105 #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) 106 #define CPM_BRG_ATB ((uint)0x00002000) 107 #define CPM_BRG_CD_MASK ((uint)0x00001ffe) 108 #define CPM_BRG_DIV16 ((uint)0x00000001) 109 110 #define CPM2_BRG_INT_CLK (get_brgfreq()) 111 #define CPM2_BRG_UART_CLK (CPM2_BRG_INT_CLK/16) 112 113 extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src); 114 115 /* This function is used by UARTS, or anything else that uses a 16x 116 * oversampled clock. 117 */ 118 static inline void cpm_setbrg(uint brg, uint rate) 119 { 120 __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT); 121 } 122 123 /* This function is used to set high speed synchronous baud rate 124 * clocks. 125 */ 126 static inline void cpm2_fastbrg(uint brg, uint rate, int div16) 127 { 128 __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT); 129 } 130 131 /* Function code bits, usually generic to devices. 132 */ 133 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ 134 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ 135 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ 136 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ 137 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ 138 139 /* Parameter RAM offsets from the base. 140 */ 141 #define PROFF_SCC1 ((uint)0x8000) 142 #define PROFF_SCC2 ((uint)0x8100) 143 #define PROFF_SCC3 ((uint)0x8200) 144 #define PROFF_SCC4 ((uint)0x8300) 145 #define PROFF_FCC1 ((uint)0x8400) 146 #define PROFF_FCC2 ((uint)0x8500) 147 #define PROFF_FCC3 ((uint)0x8600) 148 #define PROFF_MCC1 ((uint)0x8700) 149 #define PROFF_SMC1_BASE ((uint)0x87fc) 150 #define PROFF_IDMA1_BASE ((uint)0x87fe) 151 #define PROFF_MCC2 ((uint)0x8800) 152 #define PROFF_SMC2_BASE ((uint)0x88fc) 153 #define PROFF_IDMA2_BASE ((uint)0x88fe) 154 #define PROFF_SPI_BASE ((uint)0x89fc) 155 #define PROFF_IDMA3_BASE ((uint)0x89fe) 156 #define PROFF_TIMERS ((uint)0x8ae0) 157 #define PROFF_REVNUM ((uint)0x8af0) 158 #define PROFF_RAND ((uint)0x8af8) 159 #define PROFF_I2C_BASE ((uint)0x8afc) 160 #define PROFF_IDMA4_BASE ((uint)0x8afe) 161 162 #define PROFF_SCC_SIZE ((uint)0x100) 163 #define PROFF_FCC_SIZE ((uint)0x100) 164 #define PROFF_SMC_SIZE ((uint)64) 165 166 /* The SMCs are relocated to any of the first eight DPRAM pages. 167 * We will fix these at the first locations of DPRAM, until we 168 * get some microcode patches :-). 169 * The parameter ram space for the SMCs is fifty-some bytes, and 170 * they are required to start on a 64 byte boundary. 171 */ 172 #define PROFF_SMC1 (0) 173 #define PROFF_SMC2 (64) 174 175 176 /* Define enough so I can at least use the serial port as a UART. 177 */ 178 typedef struct smc_uart { 179 ushort smc_rbase; /* Rx Buffer descriptor base address */ 180 ushort smc_tbase; /* Tx Buffer descriptor base address */ 181 u_char smc_rfcr; /* Rx function code */ 182 u_char smc_tfcr; /* Tx function code */ 183 ushort smc_mrblr; /* Max receive buffer length */ 184 uint smc_rstate; /* Internal */ 185 uint smc_idp; /* Internal */ 186 ushort smc_rbptr; /* Internal */ 187 ushort smc_ibc; /* Internal */ 188 uint smc_rxtmp; /* Internal */ 189 uint smc_tstate; /* Internal */ 190 uint smc_tdp; /* Internal */ 191 ushort smc_tbptr; /* Internal */ 192 ushort smc_tbc; /* Internal */ 193 uint smc_txtmp; /* Internal */ 194 ushort smc_maxidl; /* Maximum idle characters */ 195 ushort smc_tmpidl; /* Temporary idle counter */ 196 ushort smc_brklen; /* Last received break length */ 197 ushort smc_brkec; /* rcv'd break condition counter */ 198 ushort smc_brkcr; /* xmt break count register */ 199 ushort smc_rmask; /* Temporary bit mask */ 200 uint smc_stmp; /* SDMA Temp */ 201 } smc_uart_t; 202 203 /* SMC uart mode register (Internal memory map). 204 */ 205 #define SMCMR_REN ((ushort)0x0001) 206 #define SMCMR_TEN ((ushort)0x0002) 207 #define SMCMR_DM ((ushort)0x000c) 208 #define SMCMR_SM_GCI ((ushort)0x0000) 209 #define SMCMR_SM_UART ((ushort)0x0020) 210 #define SMCMR_SM_TRANS ((ushort)0x0030) 211 #define SMCMR_SM_MASK ((ushort)0x0030) 212 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 213 #define SMCMR_REVD SMCMR_PM_EVEN 214 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 215 #define SMCMR_BS SMCMR_PEN 216 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 217 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 218 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 219 220 /* SMC Event and Mask register. 221 */ 222 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 223 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 224 #define SMCM_TXE ((unsigned char)0x10) 225 #define SMCM_BSY ((unsigned char)0x04) 226 #define SMCM_TX ((unsigned char)0x02) 227 #define SMCM_RX ((unsigned char)0x01) 228 229 /* SCCs. 230 */ 231 #define SCC_GSMRH_IRP ((uint)0x00040000) 232 #define SCC_GSMRH_GDE ((uint)0x00010000) 233 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 234 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 235 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 236 #define SCC_GSMRH_REVD ((uint)0x00002000) 237 #define SCC_GSMRH_TRX ((uint)0x00001000) 238 #define SCC_GSMRH_TTX ((uint)0x00000800) 239 #define SCC_GSMRH_CDP ((uint)0x00000400) 240 #define SCC_GSMRH_CTSP ((uint)0x00000200) 241 #define SCC_GSMRH_CDS ((uint)0x00000100) 242 #define SCC_GSMRH_CTSS ((uint)0x00000080) 243 #define SCC_GSMRH_TFL ((uint)0x00000040) 244 #define SCC_GSMRH_RFW ((uint)0x00000020) 245 #define SCC_GSMRH_TXSY ((uint)0x00000010) 246 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 247 #define SCC_GSMRH_SYNL8 ((uint)0x00000008) 248 #define SCC_GSMRH_SYNL4 ((uint)0x00000004) 249 #define SCC_GSMRH_RTSM ((uint)0x00000002) 250 #define SCC_GSMRH_RSYN ((uint)0x00000001) 251 252 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 253 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 254 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 255 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 256 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 257 #define SCC_GSMRL_TCI ((uint)0x10000000) 258 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 259 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 260 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 261 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 262 #define SCC_GSMRL_RINV ((uint)0x02000000) 263 #define SCC_GSMRL_TINV ((uint)0x01000000) 264 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 265 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 266 #define SCC_GSMRL_TPL_48 ((uint)0x00800000) 267 #define SCC_GSMRL_TPL_32 ((uint)0x00600000) 268 #define SCC_GSMRL_TPL_16 ((uint)0x00400000) 269 #define SCC_GSMRL_TPL_8 ((uint)0x00200000) 270 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 271 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 272 #define SCC_GSMRL_TPP_01 ((uint)0x00100000) 273 #define SCC_GSMRL_TPP_10 ((uint)0x00080000) 274 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 275 #define SCC_GSMRL_TEND ((uint)0x00040000) 276 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 277 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 278 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 279 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 280 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 281 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 282 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 283 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 284 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 285 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 286 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 287 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 288 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 289 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 290 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 291 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 292 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 293 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 294 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 295 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 296 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 297 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 298 #define SCC_GSMRL_ENR ((uint)0x00000020) 299 #define SCC_GSMRL_ENT ((uint)0x00000010) 300 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 301 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 302 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 303 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 304 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 305 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 306 #define SCC_GSMRL_MODE_UART ((uint)0x00000004) 307 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 308 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 309 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 310 311 #define SCC_TODR_TOD ((ushort)0x8000) 312 313 /* SCC Event and Mask register. 314 */ 315 #define SCCM_TXE ((unsigned char)0x10) 316 #define SCCM_BSY ((unsigned char)0x04) 317 #define SCCM_TX ((unsigned char)0x02) 318 #define SCCM_RX ((unsigned char)0x01) 319 320 typedef struct scc_param { 321 ushort scc_rbase; /* Rx Buffer descriptor base address */ 322 ushort scc_tbase; /* Tx Buffer descriptor base address */ 323 u_char scc_rfcr; /* Rx function code */ 324 u_char scc_tfcr; /* Tx function code */ 325 ushort scc_mrblr; /* Max receive buffer length */ 326 uint scc_rstate; /* Internal */ 327 uint scc_idp; /* Internal */ 328 ushort scc_rbptr; /* Internal */ 329 ushort scc_ibc; /* Internal */ 330 uint scc_rxtmp; /* Internal */ 331 uint scc_tstate; /* Internal */ 332 uint scc_tdp; /* Internal */ 333 ushort scc_tbptr; /* Internal */ 334 ushort scc_tbc; /* Internal */ 335 uint scc_txtmp; /* Internal */ 336 uint scc_rcrc; /* Internal */ 337 uint scc_tcrc; /* Internal */ 338 } sccp_t; 339 340 /* CPM Ethernet through SCC1. 341 */ 342 typedef struct scc_enet { 343 sccp_t sen_genscc; 344 uint sen_cpres; /* Preset CRC */ 345 uint sen_cmask; /* Constant mask for CRC */ 346 uint sen_crcec; /* CRC Error counter */ 347 uint sen_alec; /* alignment error counter */ 348 uint sen_disfc; /* discard frame counter */ 349 ushort sen_pads; /* Tx short frame pad character */ 350 ushort sen_retlim; /* Retry limit threshold */ 351 ushort sen_retcnt; /* Retry limit counter */ 352 ushort sen_maxflr; /* maximum frame length register */ 353 ushort sen_minflr; /* minimum frame length register */ 354 ushort sen_maxd1; /* maximum DMA1 length */ 355 ushort sen_maxd2; /* maximum DMA2 length */ 356 ushort sen_maxd; /* Rx max DMA */ 357 ushort sen_dmacnt; /* Rx DMA counter */ 358 ushort sen_maxb; /* Max BD byte count */ 359 ushort sen_gaddr1; /* Group address filter */ 360 ushort sen_gaddr2; 361 ushort sen_gaddr3; 362 ushort sen_gaddr4; 363 uint sen_tbuf0data0; /* Save area 0 - current frame */ 364 uint sen_tbuf0data1; /* Save area 1 - current frame */ 365 uint sen_tbuf0rba; /* Internal */ 366 uint sen_tbuf0crc; /* Internal */ 367 ushort sen_tbuf0bcnt; /* Internal */ 368 ushort sen_paddrh; /* physical address (MSB) */ 369 ushort sen_paddrm; 370 ushort sen_paddrl; /* physical address (LSB) */ 371 ushort sen_pper; /* persistence */ 372 ushort sen_rfbdptr; /* Rx first BD pointer */ 373 ushort sen_tfbdptr; /* Tx first BD pointer */ 374 ushort sen_tlbdptr; /* Tx last BD pointer */ 375 uint sen_tbuf1data0; /* Save area 0 - current frame */ 376 uint sen_tbuf1data1; /* Save area 1 - current frame */ 377 uint sen_tbuf1rba; /* Internal */ 378 uint sen_tbuf1crc; /* Internal */ 379 ushort sen_tbuf1bcnt; /* Internal */ 380 ushort sen_txlen; /* Tx Frame length counter */ 381 ushort sen_iaddr1; /* Individual address filter */ 382 ushort sen_iaddr2; 383 ushort sen_iaddr3; 384 ushort sen_iaddr4; 385 ushort sen_boffcnt; /* Backoff counter */ 386 387 /* NOTE: Some versions of the manual have the following items 388 * incorrectly documented. Below is the proper order. 389 */ 390 ushort sen_taddrh; /* temp address (MSB) */ 391 ushort sen_taddrm; 392 ushort sen_taddrl; /* temp address (LSB) */ 393 } scc_enet_t; 394 395 396 /* SCC Event register as used by Ethernet. 397 */ 398 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 399 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 400 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 401 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 402 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 403 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 404 405 /* SCC Mode Register (PSMR) as used by Ethernet. 406 */ 407 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 408 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 409 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 410 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 411 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 412 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 413 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 414 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 415 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 416 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 417 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 418 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 419 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 420 421 /* SCC as UART 422 */ 423 typedef struct scc_uart { 424 sccp_t scc_genscc; 425 uint scc_res1; /* Reserved */ 426 uint scc_res2; /* Reserved */ 427 ushort scc_maxidl; /* Maximum idle chars */ 428 ushort scc_idlc; /* temp idle counter */ 429 ushort scc_brkcr; /* Break count register */ 430 ushort scc_parec; /* receive parity error counter */ 431 ushort scc_frmec; /* receive framing error counter */ 432 ushort scc_nosec; /* receive noise counter */ 433 ushort scc_brkec; /* receive break condition counter */ 434 ushort scc_brkln; /* last received break length */ 435 ushort scc_uaddr1; /* UART address character 1 */ 436 ushort scc_uaddr2; /* UART address character 2 */ 437 ushort scc_rtemp; /* Temp storage */ 438 ushort scc_toseq; /* Transmit out of sequence char */ 439 ushort scc_char1; /* control character 1 */ 440 ushort scc_char2; /* control character 2 */ 441 ushort scc_char3; /* control character 3 */ 442 ushort scc_char4; /* control character 4 */ 443 ushort scc_char5; /* control character 5 */ 444 ushort scc_char6; /* control character 6 */ 445 ushort scc_char7; /* control character 7 */ 446 ushort scc_char8; /* control character 8 */ 447 ushort scc_rccm; /* receive control character mask */ 448 ushort scc_rccr; /* receive control character register */ 449 ushort scc_rlbc; /* receive last break character */ 450 } scc_uart_t; 451 452 /* SCC Event and Mask registers when it is used as a UART. 453 */ 454 #define UART_SCCM_GLR ((ushort)0x1000) 455 #define UART_SCCM_GLT ((ushort)0x0800) 456 #define UART_SCCM_AB ((ushort)0x0200) 457 #define UART_SCCM_IDL ((ushort)0x0100) 458 #define UART_SCCM_GRA ((ushort)0x0080) 459 #define UART_SCCM_BRKE ((ushort)0x0040) 460 #define UART_SCCM_BRKS ((ushort)0x0020) 461 #define UART_SCCM_CCR ((ushort)0x0008) 462 #define UART_SCCM_BSY ((ushort)0x0004) 463 #define UART_SCCM_TX ((ushort)0x0002) 464 #define UART_SCCM_RX ((ushort)0x0001) 465 466 /* The SCC PSMR when used as a UART. 467 */ 468 #define SCU_PSMR_FLC ((ushort)0x8000) 469 #define SCU_PSMR_SL ((ushort)0x4000) 470 #define SCU_PSMR_CL ((ushort)0x3000) 471 #define SCU_PSMR_UM ((ushort)0x0c00) 472 #define SCU_PSMR_FRZ ((ushort)0x0200) 473 #define SCU_PSMR_RZS ((ushort)0x0100) 474 #define SCU_PSMR_SYN ((ushort)0x0080) 475 #define SCU_PSMR_DRT ((ushort)0x0040) 476 #define SCU_PSMR_PEN ((ushort)0x0010) 477 #define SCU_PSMR_RPM ((ushort)0x000c) 478 #define SCU_PSMR_REVP ((ushort)0x0008) 479 #define SCU_PSMR_TPM ((ushort)0x0003) 480 #define SCU_PSMR_TEVP ((ushort)0x0002) 481 482 /* CPM Transparent mode SCC. 483 */ 484 typedef struct scc_trans { 485 sccp_t st_genscc; 486 uint st_cpres; /* Preset CRC */ 487 uint st_cmask; /* Constant mask for CRC */ 488 } scc_trans_t; 489 490 /* How about some FCCs..... 491 */ 492 #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) 493 #define FCC_GFMR_DIAG_LE ((uint)0x40000000) 494 #define FCC_GFMR_DIAG_AE ((uint)0x80000000) 495 #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) 496 #define FCC_GFMR_TCI ((uint)0x20000000) 497 #define FCC_GFMR_TRX ((uint)0x10000000) 498 #define FCC_GFMR_TTX ((uint)0x08000000) 499 #define FCC_GFMR_TTX ((uint)0x08000000) 500 #define FCC_GFMR_CDP ((uint)0x04000000) 501 #define FCC_GFMR_CTSP ((uint)0x02000000) 502 #define FCC_GFMR_CDS ((uint)0x01000000) 503 #define FCC_GFMR_CTSS ((uint)0x00800000) 504 #define FCC_GFMR_SYNL_NONE ((uint)0x00000000) 505 #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) 506 #define FCC_GFMR_SYNL_8 ((uint)0x00008000) 507 #define FCC_GFMR_SYNL_16 ((uint)0x0000c000) 508 #define FCC_GFMR_RTSM ((uint)0x00002000) 509 #define FCC_GFMR_RENC_NRZ ((uint)0x00000000) 510 #define FCC_GFMR_RENC_NRZI ((uint)0x00000800) 511 #define FCC_GFMR_REVD ((uint)0x00000400) 512 #define FCC_GFMR_TENC_NRZ ((uint)0x00000000) 513 #define FCC_GFMR_TENC_NRZI ((uint)0x00000100) 514 #define FCC_GFMR_TCRC_16 ((uint)0x00000000) 515 #define FCC_GFMR_TCRC_32 ((uint)0x00000080) 516 #define FCC_GFMR_ENR ((uint)0x00000020) 517 #define FCC_GFMR_ENT ((uint)0x00000010) 518 #define FCC_GFMR_MODE_ENET ((uint)0x0000000c) 519 #define FCC_GFMR_MODE_ATM ((uint)0x0000000a) 520 #define FCC_GFMR_MODE_HDLC ((uint)0x00000000) 521 522 /* Generic FCC parameter ram. 523 */ 524 typedef struct fcc_param { 525 ushort fcc_riptr; /* Rx Internal temp pointer */ 526 ushort fcc_tiptr; /* Tx Internal temp pointer */ 527 ushort fcc_res1; 528 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ 529 uint fcc_rstate; /* Upper byte is Func code, must be set */ 530 uint fcc_rbase; /* Receive BD base */ 531 ushort fcc_rbdstat; /* RxBD status */ 532 ushort fcc_rbdlen; /* RxBD down counter */ 533 uint fcc_rdptr; /* RxBD internal data pointer */ 534 uint fcc_tstate; /* Upper byte is Func code, must be set */ 535 uint fcc_tbase; /* Transmit BD base */ 536 ushort fcc_tbdstat; /* TxBD status */ 537 ushort fcc_tbdlen; /* TxBD down counter */ 538 uint fcc_tdptr; /* TxBD internal data pointer */ 539 uint fcc_rbptr; /* Rx BD Internal buf pointer */ 540 uint fcc_tbptr; /* Tx BD Internal buf pointer */ 541 uint fcc_rcrc; /* Rx temp CRC */ 542 uint fcc_res2; 543 uint fcc_tcrc; /* Tx temp CRC */ 544 } fccp_t; 545 546 547 /* Ethernet controller through FCC. 548 */ 549 typedef struct fcc_enet { 550 fccp_t fen_genfcc; 551 uint fen_statbuf; /* Internal status buffer */ 552 uint fen_camptr; /* CAM address */ 553 uint fen_cmask; /* Constant mask for CRC */ 554 uint fen_cpres; /* Preset CRC */ 555 uint fen_crcec; /* CRC Error counter */ 556 uint fen_alec; /* alignment error counter */ 557 uint fen_disfc; /* discard frame counter */ 558 ushort fen_retlim; /* Retry limit */ 559 ushort fen_retcnt; /* Retry counter */ 560 ushort fen_pper; /* Persistence */ 561 ushort fen_boffcnt; /* backoff counter */ 562 uint fen_gaddrh; /* Group address filter, high 32-bits */ 563 uint fen_gaddrl; /* Group address filter, low 32-bits */ 564 ushort fen_tfcstat; /* out of sequence TxBD */ 565 ushort fen_tfclen; 566 uint fen_tfcptr; 567 ushort fen_mflr; /* Maximum frame length (1518) */ 568 ushort fen_paddrh; /* MAC address */ 569 ushort fen_paddrm; 570 ushort fen_paddrl; 571 ushort fen_ibdcount; /* Internal BD counter */ 572 ushort fen_ibdstart; /* Internal BD start pointer */ 573 ushort fen_ibdend; /* Internal BD end pointer */ 574 ushort fen_txlen; /* Internal Tx frame length counter */ 575 uint fen_ibdbase[8]; /* Internal use */ 576 uint fen_iaddrh; /* Individual address filter */ 577 uint fen_iaddrl; 578 ushort fen_minflr; /* Minimum frame length (64) */ 579 ushort fen_taddrh; /* Filter transfer MAC address */ 580 ushort fen_taddrm; 581 ushort fen_taddrl; 582 ushort fen_padptr; /* Pointer to pad byte buffer */ 583 ushort fen_cftype; /* control frame type */ 584 ushort fen_cfrange; /* control frame range */ 585 ushort fen_maxb; /* maximum BD count */ 586 ushort fen_maxd1; /* Max DMA1 length (1520) */ 587 ushort fen_maxd2; /* Max DMA2 length (1520) */ 588 ushort fen_maxd; /* internal max DMA count */ 589 ushort fen_dmacnt; /* internal DMA counter */ 590 uint fen_octc; /* Total octect counter */ 591 uint fen_colc; /* Total collision counter */ 592 uint fen_broc; /* Total broadcast packet counter */ 593 uint fen_mulc; /* Total multicast packet count */ 594 uint fen_uspc; /* Total packets < 64 bytes */ 595 uint fen_frgc; /* Total packets < 64 bytes with errors */ 596 uint fen_ospc; /* Total packets > 1518 */ 597 uint fen_jbrc; /* Total packets > 1518 with errors */ 598 uint fen_p64c; /* Total packets == 64 bytes */ 599 uint fen_p65c; /* Total packets 64 < bytes <= 127 */ 600 uint fen_p128c; /* Total packets 127 < bytes <= 255 */ 601 uint fen_p256c; /* Total packets 256 < bytes <= 511 */ 602 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ 603 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ 604 uint fen_cambuf; /* Internal CAM buffer poiner */ 605 ushort fen_rfthr; /* Received frames threshold */ 606 ushort fen_rfcnt; /* Received frames count */ 607 } fcc_enet_t; 608 609 /* FCC Event/Mask register as used by Ethernet. 610 */ 611 #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 612 #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ 613 #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ 614 #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 615 #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ 616 #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ 617 #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 618 #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 619 620 /* FCC Mode Register (FPSMR) as used by Ethernet. 621 */ 622 #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ 623 #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ 624 #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ 625 #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ 626 #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ 627 #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ 628 #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ 629 #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ 630 #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ 631 #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ 632 #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ 633 #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ 634 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ 635 636 /* IIC parameter RAM. 637 */ 638 typedef struct iic { 639 ushort iic_rbase; /* Rx Buffer descriptor base address */ 640 ushort iic_tbase; /* Tx Buffer descriptor base address */ 641 u_char iic_rfcr; /* Rx function code */ 642 u_char iic_tfcr; /* Tx function code */ 643 ushort iic_mrblr; /* Max receive buffer length */ 644 uint iic_rstate; /* Internal */ 645 uint iic_rdp; /* Internal */ 646 ushort iic_rbptr; /* Internal */ 647 ushort iic_rbc; /* Internal */ 648 uint iic_rxtmp; /* Internal */ 649 uint iic_tstate; /* Internal */ 650 uint iic_tdp; /* Internal */ 651 ushort iic_tbptr; /* Internal */ 652 ushort iic_tbc; /* Internal */ 653 uint iic_txtmp; /* Internal */ 654 } iic_t; 655 656 /* SPI parameter RAM. 657 */ 658 typedef struct spi { 659 ushort spi_rbase; /* Rx Buffer descriptor base address */ 660 ushort spi_tbase; /* Tx Buffer descriptor base address */ 661 u_char spi_rfcr; /* Rx function code */ 662 u_char spi_tfcr; /* Tx function code */ 663 ushort spi_mrblr; /* Max receive buffer length */ 664 uint spi_rstate; /* Internal */ 665 uint spi_rdp; /* Internal */ 666 ushort spi_rbptr; /* Internal */ 667 ushort spi_rbc; /* Internal */ 668 uint spi_rxtmp; /* Internal */ 669 uint spi_tstate; /* Internal */ 670 uint spi_tdp; /* Internal */ 671 ushort spi_tbptr; /* Internal */ 672 ushort spi_tbc; /* Internal */ 673 uint spi_txtmp; /* Internal */ 674 uint spi_res; /* Tx temp. */ 675 uint spi_res1[4]; /* SDMA temp. */ 676 } spi_t; 677 678 /* SPI Mode register. 679 */ 680 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ 681 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ 682 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ 683 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ 684 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ 685 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ 686 #define SPMODE_EN ((ushort)0x0100) /* Enable */ 687 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ 688 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ 689 690 #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) 691 #define SPMODE_PM(x) ((x) &0xF) 692 693 #define SPI_EB ((u_char)0x10) /* big endian byte order */ 694 695 /* IDMA parameter RAM 696 */ 697 typedef struct idma { 698 ushort ibase; /* IDMA buffer descriptor table base address */ 699 ushort dcm; /* DMA channel mode */ 700 ushort ibdptr; /* IDMA current buffer descriptor pointer */ 701 ushort dpr_buf; /* IDMA transfer buffer base address */ 702 ushort buf_inv; /* internal buffer inventory */ 703 ushort ss_max; /* steady-state maximum transfer size */ 704 ushort dpr_in_ptr; /* write pointer inside the internal buffer */ 705 ushort sts; /* source transfer size */ 706 ushort dpr_out_ptr; /* read pointer inside the internal buffer */ 707 ushort seob; /* source end of burst */ 708 ushort deob; /* destination end of burst */ 709 ushort dts; /* destination transfer size */ 710 ushort ret_add; /* return address when working in ERM=1 mode */ 711 ushort res0; /* reserved */ 712 uint bd_cnt; /* internal byte count */ 713 uint s_ptr; /* source internal data pointer */ 714 uint d_ptr; /* destination internal data pointer */ 715 uint istate; /* internal state */ 716 u_char res1[20]; /* pad to 64-byte length */ 717 } idma_t; 718 719 /* DMA channel mode bit fields 720 */ 721 #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ 722 #define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ 723 #define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ 724 #define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ 725 #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ 726 #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ 727 #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ 728 #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ 729 #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ 730 #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ 731 #define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ 732 #define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ 733 #define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ 734 #define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ 735 #define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ 736 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ 737 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ 738 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ 739 740 /* IDMA Buffer Descriptors 741 */ 742 typedef struct idma_bd { 743 uint flags; 744 uint len; /* data length */ 745 uint src; /* source data buffer pointer */ 746 uint dst; /* destination data buffer pointer */ 747 } idma_bd_t; 748 749 /* IDMA buffer descriptor flag bit fields 750 */ 751 #define IDMA_BD_V ((uint)0x80000000) /* valid */ 752 #define IDMA_BD_W ((uint)0x20000000) /* wrap */ 753 #define IDMA_BD_I ((uint)0x10000000) /* interrupt */ 754 #define IDMA_BD_L ((uint)0x08000000) /* last */ 755 #define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ 756 #define IDMA_BD_SDN ((uint)0x00400000) /* source done */ 757 #define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ 758 #define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ 759 #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ 760 #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ 761 #define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ 762 #define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ 763 #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ 764 #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ 765 #define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ 766 767 /* per-channel IDMA registers 768 */ 769 typedef struct im_idma { 770 u_char idsr; /* IDMAn event status register */ 771 u_char res0[3]; 772 u_char idmr; /* IDMAn event mask register */ 773 u_char res1[3]; 774 } im_idma_t; 775 776 /* IDMA event register bit fields 777 */ 778 #define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ 779 #define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ 780 #define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ 781 #define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ 782 783 /* RISC Controller Configuration Register (RCCR) bit fields 784 */ 785 #define RCCR_TIME ((uint)0x80000000) /* timer enable */ 786 #define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ 787 #define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ 788 #define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ 789 #define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ 790 #define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ 791 #define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ 792 #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ 793 #define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ 794 #define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ 795 #define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ 796 #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ 797 #define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ 798 #define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ 799 #define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ 800 #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ 801 #define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ 802 #define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ 803 #define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ 804 #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ 805 #define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ 806 #define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ 807 #define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ 808 #define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ 809 #define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ 810 #define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ 811 #define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ 812 #define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ 813 #define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ 814 #define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ 815 #define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ 816 #define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ 817 #define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ 818 #define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ 819 #define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ 820 #define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ 821 #define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ 822 #define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ 823 824 /*----------------------------------------------------------------------- 825 * CMXFCR - CMX FCC Clock Route Register 826 */ 827 #define CMXFCR_FC1 0x40000000 /* FCC1 connection */ 828 #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ 829 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ 830 #define CMXFCR_FC2 0x00400000 /* FCC2 connection */ 831 #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ 832 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ 833 #define CMXFCR_FC3 0x00004000 /* FCC3 connection */ 834 #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ 835 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ 836 837 #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ 838 #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ 839 #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ 840 #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ 841 #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ 842 #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ 843 #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ 844 #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ 845 846 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ 847 #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ 848 #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ 849 #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ 850 #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ 851 #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ 852 #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ 853 #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ 854 855 #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ 856 #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ 857 #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ 858 #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ 859 #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ 860 #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ 861 #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ 862 #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ 863 864 #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ 865 #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ 866 #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ 867 #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ 868 #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ 869 #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ 870 #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ 871 #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ 872 873 #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ 874 #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ 875 #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ 876 #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ 877 #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ 878 #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ 879 #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ 880 #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ 881 882 #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ 883 #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ 884 #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ 885 #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ 886 #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ 887 #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ 888 #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ 889 #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ 890 891 /*----------------------------------------------------------------------- 892 * CMXSCR - CMX SCC Clock Route Register 893 */ 894 #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ 895 #define CMXSCR_SC1 0x40000000 /* SCC1 connection */ 896 #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ 897 #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ 898 #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ 899 #define CMXSCR_SC2 0x00400000 /* SCC2 connection */ 900 #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ 901 #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ 902 #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ 903 #define CMXSCR_SC3 0x00004000 /* SCC3 connection */ 904 #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ 905 #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ 906 #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ 907 #define CMXSCR_SC4 0x00000040 /* SCC4 connection */ 908 #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ 909 #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ 910 911 #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ 912 #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ 913 #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ 914 #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ 915 #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ 916 #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ 917 #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ 918 #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ 919 920 #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ 921 #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ 922 #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ 923 #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ 924 #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ 925 #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ 926 #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ 927 #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ 928 929 #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ 930 #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ 931 #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ 932 #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ 933 #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ 934 #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ 935 #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ 936 #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ 937 938 #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ 939 #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ 940 #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ 941 #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ 942 #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ 943 #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ 944 #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ 945 #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ 946 947 #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ 948 #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ 949 #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ 950 #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ 951 #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ 952 #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ 953 #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ 954 #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ 955 956 #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ 957 #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ 958 #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ 959 #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ 960 #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ 961 #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ 962 #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ 963 #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ 964 965 #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ 966 #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ 967 #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ 968 #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ 969 #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ 970 #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ 971 #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ 972 #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ 973 974 #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ 975 #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ 976 #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ 977 #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ 978 #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ 979 #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ 980 #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ 981 #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ 982 983 /*----------------------------------------------------------------------- 984 * SIUMCR - SIU Module Configuration Register 4-31 985 */ 986 #define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ 987 #define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ 988 #define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ 989 #define SIUMCR_CDIS 0x10000000 /* Core Disable */ 990 #define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ 991 #define SIUMCR_DPPC01 0x04000000 /* - " - */ 992 #define SIUMCR_DPPC10 0x08000000 /* - " - */ 993 #define SIUMCR_DPPC11 0x0c000000 /* - " - */ 994 #define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ 995 #define SIUMCR_L2CPC01 0x01000000 /* - " - */ 996 #define SIUMCR_L2CPC10 0x02000000 /* - " - */ 997 #define SIUMCR_L2CPC11 0x03000000 /* - " - */ 998 #define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ 999 #define SIUMCR_LBPC01 0x00400000 /* - " - */ 1000 #define SIUMCR_LBPC10 0x00800000 /* - " - */ 1001 #define SIUMCR_LBPC11 0x00c00000 /* - " - */ 1002 #define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ 1003 #define SIUMCR_APPC01 0x00100000 /* - " - */ 1004 #define SIUMCR_APPC10 0x00200000 /* - " - */ 1005 #define SIUMCR_APPC11 0x00300000 /* - " - */ 1006 #define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ 1007 #define SIUMCR_CS10PC01 0x00040000 /* - " - */ 1008 #define SIUMCR_CS10PC10 0x00080000 /* - " - */ 1009 #define SIUMCR_CS10PC11 0x000c0000 /* - " - */ 1010 #define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ 1011 #define SIUMCR_BCTLC01 0x00010000 /* - " - */ 1012 #define SIUMCR_BCTLC10 0x00020000 /* - " - */ 1013 #define SIUMCR_BCTLC11 0x00030000 /* - " - */ 1014 #define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ 1015 #define SIUMCR_MMR01 0x00004000 /* - " - */ 1016 #define SIUMCR_MMR10 0x00008000 /* - " - */ 1017 #define SIUMCR_MMR11 0x0000c000 /* - " - */ 1018 #define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ 1019 1020 /*----------------------------------------------------------------------- 1021 * SCCR - System Clock Control Register 9-8 1022 */ 1023 #define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ 1024 #define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ 1025 #define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ 1026 #define SCCR_PCIDF_SHIFT 3 1027 1028 #ifndef CPM_IMMR_OFFSET 1029 #define CPM_IMMR_OFFSET 0x101a8 1030 #endif 1031 1032 #define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ 1033 1034 /* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK 1035 * in order to use clock-computing stuff below for the FCC x 1036 */ 1037 1038 /* Automatically generates register configurations */ 1039 #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ 1040 1041 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ 1042 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ 1043 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ 1044 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ 1045 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ 1046 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ 1047 1048 #define PC_F1RXCLK PC_CLK(F1_RXCLK) 1049 #define PC_F1TXCLK PC_CLK(F1_TXCLK) 1050 #define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) 1051 #define CMX1_CLK_MASK ((uint)0xff000000) 1052 1053 #define PC_F2RXCLK PC_CLK(F2_RXCLK) 1054 #define PC_F2TXCLK PC_CLK(F2_TXCLK) 1055 #define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) 1056 #define CMX2_CLK_MASK ((uint)0x00ff0000) 1057 1058 #define PC_F3RXCLK PC_CLK(F3_RXCLK) 1059 #define PC_F3TXCLK PC_CLK(F3_TXCLK) 1060 #define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) 1061 #define CMX3_CLK_MASK ((uint)0x0000ff00) 1062 1063 #define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK) 1064 #define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE) 1065 1066 #define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK) 1067 1068 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this, 1069 * but there is little variation among the choices. 1070 */ 1071 #define PA1_COL 0x00000001U 1072 #define PA1_CRS 0x00000002U 1073 #define PA1_TXER 0x00000004U 1074 #define PA1_TXEN 0x00000008U 1075 #define PA1_RXDV 0x00000010U 1076 #define PA1_RXER 0x00000020U 1077 #define PA1_TXDAT 0x00003c00U 1078 #define PA1_RXDAT 0x0003c000U 1079 #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) 1080 #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ 1081 PA1_RXDV | PA1_RXER) 1082 #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) 1083 #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) 1084 1085 1086 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this, 1087 * but there is little variation among the choices. 1088 */ 1089 #define PB2_TXER 0x00000001U 1090 #define PB2_RXDV 0x00000002U 1091 #define PB2_TXEN 0x00000004U 1092 #define PB2_RXER 0x00000008U 1093 #define PB2_COL 0x00000010U 1094 #define PB2_CRS 0x00000020U 1095 #define PB2_TXDAT 0x000003c0U 1096 #define PB2_RXDAT 0x00003c00U 1097 #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ 1098 PB2_RXER | PB2_RXDV | PB2_TXER) 1099 #define PB2_PSORB1 (PB2_TXEN) 1100 #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) 1101 #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) 1102 1103 1104 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this, 1105 * but there is little variation among the choices. 1106 */ 1107 #define PB3_RXDV 0x00004000U 1108 #define PB3_RXER 0x00008000U 1109 #define PB3_TXER 0x00010000U 1110 #define PB3_TXEN 0x00020000U 1111 #define PB3_COL 0x00040000U 1112 #define PB3_CRS 0x00080000U 1113 #define PB3_TXDAT 0x0f000000U 1114 #define PC3_TXDAT 0x00000010U 1115 #define PB3_RXDAT 0x00f00000U 1116 #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ 1117 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) 1118 #define PB3_PSORB1 0 1119 #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) 1120 #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) 1121 #define PC3_DIRC1 (PC3_TXDAT) 1122 1123 /* Handy macro to specify mem for FCCs*/ 1124 #define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) 1125 #define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) 1126 #define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) 1127 #define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2) 1128 1129 /* Clocks and GRG's */ 1130 1131 enum cpm_clk_dir { 1132 CPM_CLK_RX, 1133 CPM_CLK_TX, 1134 CPM_CLK_RTX 1135 }; 1136 1137 enum cpm_clk_target { 1138 CPM_CLK_SCC1, 1139 CPM_CLK_SCC2, 1140 CPM_CLK_SCC3, 1141 CPM_CLK_SCC4, 1142 CPM_CLK_FCC1, 1143 CPM_CLK_FCC2, 1144 CPM_CLK_FCC3, 1145 CPM_CLK_SMC1, 1146 CPM_CLK_SMC2, 1147 }; 1148 1149 enum cpm_clk { 1150 CPM_CLK_NONE = 0, 1151 CPM_BRG1, /* Baud Rate Generator 1 */ 1152 CPM_BRG2, /* Baud Rate Generator 2 */ 1153 CPM_BRG3, /* Baud Rate Generator 3 */ 1154 CPM_BRG4, /* Baud Rate Generator 4 */ 1155 CPM_BRG5, /* Baud Rate Generator 5 */ 1156 CPM_BRG6, /* Baud Rate Generator 6 */ 1157 CPM_BRG7, /* Baud Rate Generator 7 */ 1158 CPM_BRG8, /* Baud Rate Generator 8 */ 1159 CPM_CLK1, /* Clock 1 */ 1160 CPM_CLK2, /* Clock 2 */ 1161 CPM_CLK3, /* Clock 3 */ 1162 CPM_CLK4, /* Clock 4 */ 1163 CPM_CLK5, /* Clock 5 */ 1164 CPM_CLK6, /* Clock 6 */ 1165 CPM_CLK7, /* Clock 7 */ 1166 CPM_CLK8, /* Clock 8 */ 1167 CPM_CLK9, /* Clock 9 */ 1168 CPM_CLK10, /* Clock 10 */ 1169 CPM_CLK11, /* Clock 11 */ 1170 CPM_CLK12, /* Clock 12 */ 1171 CPM_CLK13, /* Clock 13 */ 1172 CPM_CLK14, /* Clock 14 */ 1173 CPM_CLK15, /* Clock 15 */ 1174 CPM_CLK16, /* Clock 16 */ 1175 CPM_CLK17, /* Clock 17 */ 1176 CPM_CLK18, /* Clock 18 */ 1177 CPM_CLK19, /* Clock 19 */ 1178 CPM_CLK20, /* Clock 20 */ 1179 CPM_CLK_DUMMY 1180 }; 1181 1182 extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode); 1183 extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock); 1184 1185 #define CPM_PIN_INPUT 0 1186 #define CPM_PIN_OUTPUT 1 1187 #define CPM_PIN_PRIMARY 0 1188 #define CPM_PIN_SECONDARY 2 1189 #define CPM_PIN_GPIO 4 1190 #define CPM_PIN_OPENDRAIN 8 1191 1192 void cpm2_set_pin(int port, int pin, int flags); 1193 1194 #endif /* __CPM2__ */ 1195 #endif /* __KERNEL__ */ 1196