1 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H 2 #define _ASM_POWERPC_PGTABLE_RADIX_H 3 4 #ifndef __ASSEMBLY__ 5 #include <asm/cmpxchg.h> 6 #endif 7 8 #ifdef CONFIG_PPC_64K_PAGES 9 #include <asm/book3s/64/radix-64k.h> 10 #else 11 #include <asm/book3s/64/radix-4k.h> 12 #endif 13 14 #ifndef __ASSEMBLY__ 15 #include <asm/book3s/64/tlbflush-radix.h> 16 #include <asm/cpu_has_feature.h> 17 #endif 18 19 /* An empty PTE can still have a R or C writeback */ 20 #define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED) 21 22 /* Bits to set in a RPMD/RPUD/RPGD */ 23 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE) 24 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE) 25 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE) 26 27 /* Don't have anything in the reserved bits and leaf bits */ 28 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL 29 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL 30 #define RADIX_PGD_BAD_BITS 0x60000000000000e0UL 31 32 /* 33 * Size of EA range mapped by our pagetables. 34 */ 35 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \ 36 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT) 37 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE) 38 39 /* 40 * We support 52 bit address space, Use top bit for kernel 41 * virtual mapping. Also make sure kernel fit in the top 42 * quadrant. 43 * 44 * +------------------+ 45 * +------------------+ Kernel virtual map (0xc008000000000000) 46 * | | 47 * | | 48 * | | 49 * 0b11......+------------------+ Kernel linear map (0xc....) 50 * | | 51 * | 2 quadrant | 52 * | | 53 * 0b10......+------------------+ 54 * | | 55 * | 1 quadrant | 56 * | | 57 * 0b01......+------------------+ 58 * | | 59 * | 0 quadrant | 60 * | | 61 * 0b00......+------------------+ 62 * 63 * 64 * 3rd quadrant expanded: 65 * +------------------------------+ 66 * | | 67 * | | 68 * | | 69 * +------------------------------+ Kernel IO map end (0xc010000000000000) 70 * | | 71 * | | 72 * | 1/2 of virtual map | 73 * | | 74 * | | 75 * +------------------------------+ Kernel IO map start 76 * | | 77 * | 1/4 of virtual map | 78 * | | 79 * +------------------------------+ Kernel vmemap start 80 * | | 81 * | 1/4 of virtual map | 82 * | | 83 * +------------------------------+ Kernel virt start (0xc008000000000000) 84 * | | 85 * | | 86 * | | 87 * +------------------------------+ Kernel linear (0xc.....) 88 */ 89 90 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000) 91 #define RADIX_KERN_VIRT_SIZE ASM_CONST(0x0008000000000000) 92 93 /* 94 * The vmalloc space starts at the beginning of that region, and 95 * occupies a quarter of it on radix config. 96 * (we keep a quarter for the virtual memmap) 97 */ 98 #define RADIX_VMALLOC_START RADIX_KERN_VIRT_START 99 #define RADIX_VMALLOC_SIZE (RADIX_KERN_VIRT_SIZE >> 2) 100 #define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE) 101 /* 102 * Defines the address of the vmemap area, in its own region on 103 * hash table CPUs. 104 */ 105 #define RADIX_VMEMMAP_BASE (RADIX_VMALLOC_END) 106 107 #ifndef __ASSEMBLY__ 108 #define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE) 109 #define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE) 110 #define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE) 111 #define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE) 112 113 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr, 114 unsigned long set) 115 { 116 pte_t pte; 117 unsigned long old_pte, new_pte; 118 119 do { 120 pte = READ_ONCE(*ptep); 121 old_pte = pte_val(pte); 122 new_pte = (old_pte | set) & ~clr; 123 124 } while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte))); 125 126 return old_pte; 127 } 128 129 130 static inline unsigned long radix__pte_update(struct mm_struct *mm, 131 unsigned long addr, 132 pte_t *ptep, unsigned long clr, 133 unsigned long set, 134 int huge) 135 { 136 unsigned long old_pte; 137 138 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 139 140 unsigned long new_pte; 141 142 old_pte = __radix_pte_update(ptep, ~0ul, 0); 143 /* 144 * new value of pte 145 */ 146 new_pte = (old_pte | set) & ~clr; 147 radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); 148 if (new_pte) 149 __radix_pte_update(ptep, 0, new_pte); 150 } else 151 old_pte = __radix_pte_update(ptep, clr, set); 152 if (!huge) 153 assert_pte_locked(mm, addr); 154 155 return old_pte; 156 } 157 158 static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm, 159 unsigned long addr, 160 pte_t *ptep, int full) 161 { 162 unsigned long old_pte; 163 164 if (full) { 165 /* 166 * If we are trying to clear the pte, we can skip 167 * the DD1 pte update sequence and batch the tlb flush. The 168 * tlb flush batching is done by mmu gather code. We 169 * still keep the cmp_xchg update to make sure we get 170 * correct R/C bit which might be updated via Nest MMU. 171 */ 172 old_pte = __radix_pte_update(ptep, ~0ul, 0); 173 } else 174 old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0); 175 176 return __pte(old_pte); 177 } 178 179 /* 180 * Set the dirty and/or accessed bits atomically in a linux PTE, this 181 * function doesn't need to invalidate tlb. 182 */ 183 static inline void radix__ptep_set_access_flags(struct mm_struct *mm, 184 pte_t *ptep, pte_t entry, 185 unsigned long address) 186 { 187 188 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | 189 _PAGE_RW | _PAGE_EXEC); 190 191 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 192 193 unsigned long old_pte, new_pte; 194 195 old_pte = __radix_pte_update(ptep, ~0, 0); 196 /* 197 * new value of pte 198 */ 199 new_pte = old_pte | set; 200 radix__flush_tlb_pte_p9_dd1(old_pte, mm, address); 201 __radix_pte_update(ptep, 0, new_pte); 202 } else 203 __radix_pte_update(ptep, 0, set); 204 asm volatile("ptesync" : : : "memory"); 205 } 206 207 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b) 208 { 209 return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0); 210 } 211 212 static inline int radix__pte_none(pte_t pte) 213 { 214 return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0; 215 } 216 217 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr, 218 pte_t *ptep, pte_t pte, int percpu) 219 { 220 *ptep = pte; 221 asm volatile("ptesync" : : : "memory"); 222 } 223 224 static inline int radix__pmd_bad(pmd_t pmd) 225 { 226 return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS); 227 } 228 229 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b) 230 { 231 return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0); 232 } 233 234 static inline int radix__pud_bad(pud_t pud) 235 { 236 return !!(pud_val(pud) & RADIX_PUD_BAD_BITS); 237 } 238 239 240 static inline int radix__pgd_bad(pgd_t pgd) 241 { 242 return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS); 243 } 244 245 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 246 247 static inline int radix__pmd_trans_huge(pmd_t pmd) 248 { 249 return !!(pmd_val(pmd) & _PAGE_PTE); 250 } 251 252 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd) 253 { 254 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) 255 return __pmd(pmd_val(pmd) | _PAGE_PTE | _PAGE_LARGE); 256 return __pmd(pmd_val(pmd) | _PAGE_PTE); 257 } 258 static inline void radix__pmdp_huge_split_prepare(struct vm_area_struct *vma, 259 unsigned long address, pmd_t *pmdp) 260 { 261 /* Nothing to do for radix. */ 262 return; 263 } 264 265 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, 266 pmd_t *pmdp, unsigned long clr, 267 unsigned long set); 268 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, 269 unsigned long address, pmd_t *pmdp); 270 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 271 pgtable_t pgtable); 272 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 273 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm, 274 unsigned long addr, pmd_t *pmdp); 275 extern int radix__has_transparent_hugepage(void); 276 #endif 277 278 extern int __meminit radix__vmemmap_create_mapping(unsigned long start, 279 unsigned long page_size, 280 unsigned long phys); 281 extern void radix__vmemmap_remove_mapping(unsigned long start, 282 unsigned long page_size); 283 284 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa, 285 pgprot_t flags, unsigned int psz); 286 287 static inline unsigned long radix__get_tree_size(void) 288 { 289 unsigned long rts_field; 290 /* 291 * We support 52 bits, hence: 292 * DD1 52-28 = 24, 0b11000 293 * Others 52-31 = 21, 0b10101 294 * RTS encoding details 295 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long 296 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long 297 */ 298 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) 299 rts_field = (0x3UL << 61); 300 else { 301 rts_field = (0x5UL << 5); /* 6 - 8 bits */ 302 rts_field |= (0x2UL << 61); 303 } 304 return rts_field; 305 } 306 307 #ifdef CONFIG_MEMORY_HOTPLUG 308 int radix__create_section_mapping(unsigned long start, unsigned long end); 309 int radix__remove_section_mapping(unsigned long start, unsigned long end); 310 #endif /* CONFIG_MEMORY_HOTPLUG */ 311 #endif /* __ASSEMBLY__ */ 312 #endif 313