1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #include <linux/sizes.h> 11 #endif 12 13 /* 14 * Common bits between hash and Radix page table 15 */ 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x00040UL 36 37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 /* 46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 48 * differentiate between two use a SW field when invalidating. 49 * 50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 51 * 52 * This is used only when _PAGE_PRESENT is cleared. 53 */ 54 #define _PAGE_INVALID _RPAGE_SW0 55 56 /* 57 * Top and bottom bits of RPN which can be used by hash 58 * translation mode, because we expect them to be zero 59 * otherwise. 60 */ 61 #define _RPAGE_RPN0 0x01000 62 #define _RPAGE_RPN1 0x02000 63 #define _RPAGE_RPN43 0x0080000000000000UL 64 #define _RPAGE_RPN42 0x0040000000000000UL 65 #define _RPAGE_RPN41 0x0020000000000000UL 66 67 /* Max physical address bit as per radix table */ 68 #define _RPAGE_PA_MAX 56 69 70 /* 71 * Max physical address bit we will use for now. 72 * 73 * This is mostly a hardware limitation and for now Power9 has 74 * a 51 bit limit. 75 * 76 * This is different from the number of physical bit required to address 77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 79 * number of sections we can support (SECTIONS_SHIFT). 80 * 81 * This is different from Radix page table limitation above and 82 * should always be less than that. The limit is done such that 83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 84 * for hash linux page table specific bits. 85 * 86 * In order to be compatible with future hardware generations we keep 87 * some offsets and limit this for now to 53 88 */ 89 #define _PAGE_PA_MAX 53 90 91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 120 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 121 _PAGE_RW | _PAGE_EXEC) 122 /* 123 * _PAGE_CHG_MASK masks of bits that are to be preserved across 124 * pgprot changes 125 */ 126 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 127 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 128 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 129 130 /* 131 * We define 2 sets of base prot bits, one for basic pages (ie, 132 * cacheable kernel and user pages) and one for non cacheable 133 * pages. We always set _PAGE_COHERENT when SMP is enabled or 134 * the processor might need it for DMA coherency. 135 */ 136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 137 #define _PAGE_BASE (_PAGE_BASE_NC) 138 139 /* Permission masks used to generate the __P and __S table, 140 * 141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 142 * 143 * Write permissions imply read permissions for now (we could make write-only 144 * pages on BookE but we don't bother for now). Execute permission control is 145 * possible on platforms that define _PAGE_EXEC 146 */ 147 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 148 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 149 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 150 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 151 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 152 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 153 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 /* Radix only, Hash uses PAGE_READONLY_X + execute-only pkey instead */ 155 #define PAGE_EXECONLY __pgprot(_PAGE_BASE | _PAGE_EXEC) 156 157 /* Permission masks used for kernel mappings */ 158 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 159 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 160 _PAGE_TOLERANT) 161 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 162 _PAGE_NON_IDEMPOTENT) 163 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 164 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 165 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 166 167 /* 168 * Protection used for kernel text. We want the debuggers to be able to 169 * set breakpoints anywhere, so don't write protect the kernel text 170 * on platforms where such control is possible. 171 */ 172 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 173 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 174 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 175 #else 176 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 177 #endif 178 179 /* Make modules code happy. We don't set RO yet */ 180 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 181 #define PAGE_AGP (PAGE_KERNEL_NC) 182 183 #ifndef __ASSEMBLY__ 184 /* 185 * page table defines 186 */ 187 extern unsigned long __pte_index_size; 188 extern unsigned long __pmd_index_size; 189 extern unsigned long __pud_index_size; 190 extern unsigned long __pgd_index_size; 191 extern unsigned long __pud_cache_index; 192 #define PTE_INDEX_SIZE __pte_index_size 193 #define PMD_INDEX_SIZE __pmd_index_size 194 #define PUD_INDEX_SIZE __pud_index_size 195 #define PGD_INDEX_SIZE __pgd_index_size 196 /* pmd table use page table fragments */ 197 #define PMD_CACHE_INDEX 0 198 #define PUD_CACHE_INDEX __pud_cache_index 199 /* 200 * Because of use of pte fragments and THP, size of page table 201 * are not always derived out of index size above. 202 */ 203 extern unsigned long __pte_table_size; 204 extern unsigned long __pmd_table_size; 205 extern unsigned long __pud_table_size; 206 extern unsigned long __pgd_table_size; 207 #define PTE_TABLE_SIZE __pte_table_size 208 #define PMD_TABLE_SIZE __pmd_table_size 209 #define PUD_TABLE_SIZE __pud_table_size 210 #define PGD_TABLE_SIZE __pgd_table_size 211 212 extern unsigned long __pmd_val_bits; 213 extern unsigned long __pud_val_bits; 214 extern unsigned long __pgd_val_bits; 215 #define PMD_VAL_BITS __pmd_val_bits 216 #define PUD_VAL_BITS __pud_val_bits 217 #define PGD_VAL_BITS __pgd_val_bits 218 219 extern unsigned long __pte_frag_nr; 220 #define PTE_FRAG_NR __pte_frag_nr 221 extern unsigned long __pte_frag_size_shift; 222 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 223 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 224 225 extern unsigned long __pmd_frag_nr; 226 #define PMD_FRAG_NR __pmd_frag_nr 227 extern unsigned long __pmd_frag_size_shift; 228 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 229 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 230 231 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 232 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 233 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 234 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 235 236 #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) 237 #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) 238 #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) 239 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ 240 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) 241 242 /* PMD_SHIFT determines what a second-level page table entry can map */ 243 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 244 #define PMD_SIZE (1UL << PMD_SHIFT) 245 #define PMD_MASK (~(PMD_SIZE-1)) 246 247 /* PUD_SHIFT determines what a third-level page table entry can map */ 248 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 249 #define PUD_SIZE (1UL << PUD_SHIFT) 250 #define PUD_MASK (~(PUD_SIZE-1)) 251 252 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 253 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 254 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 255 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 256 257 /* Bits to mask out from a PMD to get to the PTE page */ 258 #define PMD_MASKED_BITS 0xc0000000000000ffUL 259 /* Bits to mask out from a PUD to get to the PMD page */ 260 #define PUD_MASKED_BITS 0xc0000000000000ffUL 261 /* Bits to mask out from a PGD to get to the PUD page */ 262 #define P4D_MASKED_BITS 0xc0000000000000ffUL 263 264 /* 265 * Used as an indicator for rcu callback functions 266 */ 267 enum pgtable_index { 268 PTE_INDEX = 0, 269 PMD_INDEX, 270 PUD_INDEX, 271 PGD_INDEX, 272 /* 273 * Below are used with 4k page size and hugetlb 274 */ 275 HTLB_16M_INDEX, 276 HTLB_16G_INDEX, 277 }; 278 279 extern unsigned long __vmalloc_start; 280 extern unsigned long __vmalloc_end; 281 #define VMALLOC_START __vmalloc_start 282 #define VMALLOC_END __vmalloc_end 283 284 static inline unsigned int ioremap_max_order(void) 285 { 286 if (radix_enabled()) 287 return PUD_SHIFT; 288 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 289 } 290 #define IOREMAP_MAX_ORDER ioremap_max_order() 291 292 extern unsigned long __kernel_virt_start; 293 extern unsigned long __kernel_io_start; 294 extern unsigned long __kernel_io_end; 295 #define KERN_VIRT_START __kernel_virt_start 296 #define KERN_IO_START __kernel_io_start 297 #define KERN_IO_END __kernel_io_end 298 299 extern struct page *vmemmap; 300 extern unsigned long pci_io_base; 301 #endif /* __ASSEMBLY__ */ 302 303 #include <asm/book3s/64/hash.h> 304 #include <asm/book3s/64/radix.h> 305 306 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 307 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 308 #else 309 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 310 #endif 311 312 313 #ifdef CONFIG_PPC_64K_PAGES 314 #include <asm/book3s/64/pgtable-64k.h> 315 #else 316 #include <asm/book3s/64/pgtable-4k.h> 317 #endif 318 319 #include <asm/barrier.h> 320 /* 321 * IO space itself carved into the PIO region (ISA and PHB IO space) and 322 * the ioremap space 323 * 324 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 325 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 326 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 327 */ 328 #define FULL_IO_SIZE 0x80000000ul 329 #define ISA_IO_BASE (KERN_IO_START) 330 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 331 #define PHB_IO_BASE (ISA_IO_END) 332 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 333 #define IOREMAP_BASE (PHB_IO_END) 334 #define IOREMAP_START (ioremap_bot) 335 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 336 #define FIXADDR_SIZE SZ_32M 337 338 /* Advertise special mapping type for AGP */ 339 #define HAVE_PAGE_AGP 340 341 #ifndef __ASSEMBLY__ 342 343 /* 344 * This is the default implementation of various PTE accessors, it's 345 * used in all cases except Book3S with 64K pages where we have a 346 * concept of sub-pages 347 */ 348 #ifndef __real_pte 349 350 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 351 #define __rpte_to_pte(r) ((r).pte) 352 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 353 354 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 355 do { \ 356 index = 0; \ 357 shift = mmu_psize_defs[psize].shift; \ 358 359 #define pte_iterate_hashed_end() } while(0) 360 361 /* 362 * We expect this to be called only for user addresses or kernel virtual 363 * addresses other than the linear mapping. 364 */ 365 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 366 367 #endif /* __real_pte */ 368 369 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 370 pte_t *ptep, unsigned long clr, 371 unsigned long set, int huge) 372 { 373 if (radix_enabled()) 374 return radix__pte_update(mm, addr, ptep, clr, set, huge); 375 return hash__pte_update(mm, addr, ptep, clr, set, huge); 376 } 377 /* 378 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 379 * We currently remove entries from the hashtable regardless of whether 380 * the entry was young or dirty. 381 * 382 * We should be more intelligent about this but for the moment we override 383 * these functions and force a tlb flush unconditionally 384 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 385 * function for both hash and radix. 386 */ 387 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 388 unsigned long addr, pte_t *ptep) 389 { 390 unsigned long old; 391 392 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 393 return 0; 394 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 395 return (old & _PAGE_ACCESSED) != 0; 396 } 397 398 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 399 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 400 ({ \ 401 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 402 }) 403 404 /* 405 * On Book3S CPUs, clearing the accessed bit without a TLB flush 406 * doesn't cause data corruption. [ It could cause incorrect 407 * page aging and the (mistaken) reclaim of hot pages, but the 408 * chance of that should be relatively low. ] 409 * 410 * So as a performance optimization don't flush the TLB when 411 * clearing the accessed bit, it will eventually be flushed by 412 * a context switch or a VM operation anyway. [ In the rare 413 * event of it not getting flushed for a long time the delay 414 * shouldn't really matter because there's no real memory 415 * pressure for swapout to react to. ] 416 * 417 * Note: this optimisation also exists in pte_needs_flush() and 418 * huge_pmd_needs_flush(). 419 */ 420 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 421 #define ptep_clear_flush_young ptep_test_and_clear_young 422 423 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 424 #define pmdp_clear_flush_young pmdp_test_and_clear_young 425 426 static inline int __pte_write(pte_t pte) 427 { 428 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 429 } 430 431 #ifdef CONFIG_NUMA_BALANCING 432 #define pte_savedwrite pte_savedwrite 433 static inline bool pte_savedwrite(pte_t pte) 434 { 435 /* 436 * Saved write ptes are prot none ptes that doesn't have 437 * privileged bit sit. We mark prot none as one which has 438 * present and pviliged bit set and RWX cleared. To mark 439 * protnone which used to have _PAGE_WRITE set we clear 440 * the privileged bit. 441 */ 442 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 443 } 444 #else 445 #define pte_savedwrite pte_savedwrite 446 static inline bool pte_savedwrite(pte_t pte) 447 { 448 return false; 449 } 450 #endif 451 452 static inline int pte_write(pte_t pte) 453 { 454 return __pte_write(pte) || pte_savedwrite(pte); 455 } 456 457 static inline int pte_read(pte_t pte) 458 { 459 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 460 } 461 462 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 463 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 464 pte_t *ptep) 465 { 466 if (__pte_write(*ptep)) 467 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 468 else if (unlikely(pte_savedwrite(*ptep))) 469 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 470 } 471 472 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 473 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 474 unsigned long addr, pte_t *ptep) 475 { 476 /* 477 * We should not find protnone for hugetlb, but this complete the 478 * interface. 479 */ 480 if (__pte_write(*ptep)) 481 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 482 else if (unlikely(pte_savedwrite(*ptep))) 483 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 484 } 485 486 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 487 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 488 unsigned long addr, pte_t *ptep) 489 { 490 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 491 return __pte(old); 492 } 493 494 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 495 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 496 unsigned long addr, 497 pte_t *ptep, int full) 498 { 499 if (full && radix_enabled()) { 500 /* 501 * We know that this is a full mm pte clear and 502 * hence can be sure there is no parallel set_pte. 503 */ 504 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 505 } 506 return ptep_get_and_clear(mm, addr, ptep); 507 } 508 509 510 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 511 pte_t * ptep) 512 { 513 pte_update(mm, addr, ptep, ~0UL, 0, 0); 514 } 515 516 static inline int pte_dirty(pte_t pte) 517 { 518 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 519 } 520 521 static inline int pte_young(pte_t pte) 522 { 523 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 524 } 525 526 static inline int pte_special(pte_t pte) 527 { 528 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 529 } 530 531 static inline bool pte_exec(pte_t pte) 532 { 533 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 534 } 535 536 537 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 538 static inline bool pte_soft_dirty(pte_t pte) 539 { 540 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 541 } 542 543 static inline pte_t pte_mksoft_dirty(pte_t pte) 544 { 545 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 546 } 547 548 static inline pte_t pte_clear_soft_dirty(pte_t pte) 549 { 550 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 551 } 552 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 553 554 #ifdef CONFIG_NUMA_BALANCING 555 static inline int pte_protnone(pte_t pte) 556 { 557 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 558 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 559 } 560 561 #define pte_mk_savedwrite pte_mk_savedwrite 562 static inline pte_t pte_mk_savedwrite(pte_t pte) 563 { 564 /* 565 * Used by Autonuma subsystem to preserve the write bit 566 * while marking the pte PROT_NONE. Only allow this 567 * on PROT_NONE pte 568 */ 569 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 570 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 571 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 572 } 573 574 #define pte_clear_savedwrite pte_clear_savedwrite 575 static inline pte_t pte_clear_savedwrite(pte_t pte) 576 { 577 /* 578 * Used by KSM subsystem to make a protnone pte readonly. 579 */ 580 VM_BUG_ON(!pte_protnone(pte)); 581 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 582 } 583 #else 584 #define pte_clear_savedwrite pte_clear_savedwrite 585 static inline pte_t pte_clear_savedwrite(pte_t pte) 586 { 587 VM_WARN_ON(1); 588 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 589 } 590 #endif /* CONFIG_NUMA_BALANCING */ 591 592 static inline bool pte_hw_valid(pte_t pte) 593 { 594 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 595 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 596 } 597 598 static inline int pte_present(pte_t pte) 599 { 600 /* 601 * A pte is considerent present if _PAGE_PRESENT is set. 602 * We also need to consider the pte present which is marked 603 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 604 * if we find _PAGE_PRESENT cleared. 605 */ 606 607 if (pte_hw_valid(pte)) 608 return true; 609 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 610 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 611 } 612 613 #ifdef CONFIG_PPC_MEM_KEYS 614 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 615 #else 616 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 617 { 618 return true; 619 } 620 #endif /* CONFIG_PPC_MEM_KEYS */ 621 622 static inline bool pte_user(pte_t pte) 623 { 624 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 625 } 626 627 #define pte_access_permitted pte_access_permitted 628 static inline bool pte_access_permitted(pte_t pte, bool write) 629 { 630 /* 631 * _PAGE_READ is needed for any access and will be 632 * cleared for PROT_NONE 633 */ 634 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 635 return false; 636 637 if (write && !pte_write(pte)) 638 return false; 639 640 return arch_pte_access_permitted(pte_val(pte), write, 0); 641 } 642 643 /* 644 * Conversion functions: convert a page and protection to a page entry, 645 * and a page entry and page directory to the page they refer to. 646 * 647 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 648 * long for now. 649 */ 650 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 651 { 652 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 653 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 654 655 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 656 } 657 658 static inline unsigned long pte_pfn(pte_t pte) 659 { 660 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 661 } 662 663 /* Generic modifiers for PTE bits */ 664 static inline pte_t pte_wrprotect(pte_t pte) 665 { 666 if (unlikely(pte_savedwrite(pte))) 667 return pte_clear_savedwrite(pte); 668 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 669 } 670 671 static inline pte_t pte_exprotect(pte_t pte) 672 { 673 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 674 } 675 676 static inline pte_t pte_mkclean(pte_t pte) 677 { 678 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 679 } 680 681 static inline pte_t pte_mkold(pte_t pte) 682 { 683 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 684 } 685 686 static inline pte_t pte_mkexec(pte_t pte) 687 { 688 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 689 } 690 691 static inline pte_t pte_mkwrite(pte_t pte) 692 { 693 /* 694 * write implies read, hence set both 695 */ 696 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 697 } 698 699 static inline pte_t pte_mkdirty(pte_t pte) 700 { 701 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 702 } 703 704 static inline pte_t pte_mkyoung(pte_t pte) 705 { 706 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 707 } 708 709 static inline pte_t pte_mkspecial(pte_t pte) 710 { 711 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 712 } 713 714 static inline pte_t pte_mkhuge(pte_t pte) 715 { 716 return pte; 717 } 718 719 static inline pte_t pte_mkdevmap(pte_t pte) 720 { 721 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 722 } 723 724 static inline pte_t pte_mkprivileged(pte_t pte) 725 { 726 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 727 } 728 729 static inline pte_t pte_mkuser(pte_t pte) 730 { 731 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 732 } 733 734 /* 735 * This is potentially called with a pmd as the argument, in which case it's not 736 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 737 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 738 * use in page directory entries (ie. non-ptes). 739 */ 740 static inline int pte_devmap(pte_t pte) 741 { 742 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 743 744 return (pte_raw(pte) & mask) == mask; 745 } 746 747 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 748 { 749 /* FIXME!! check whether this need to be a conditional */ 750 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 751 cpu_to_be64(pgprot_val(newprot))); 752 } 753 754 /* Encode and de-code a swap entry */ 755 #define MAX_SWAPFILES_CHECK() do { \ 756 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 757 /* \ 758 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 759 * We filter HPTEFLAGS on set_pte. \ 760 */ \ 761 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ 762 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 763 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ 764 } while (0) 765 766 #define SWP_TYPE_BITS 5 767 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) 768 #define __swp_type(x) ((x).val & SWP_TYPE_MASK) 769 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 770 #define __swp_entry(type, offset) ((swp_entry_t) { \ 771 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 772 /* 773 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 774 * swap type and offset we get from swap and convert that to pte to find a 775 * matching pte in linux page table. 776 * Clear bits not found in swap entries here. 777 */ 778 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 779 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 780 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 781 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 782 783 #ifdef CONFIG_MEM_SOFT_DIRTY 784 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY 785 #else 786 #define _PAGE_SWP_SOFT_DIRTY 0UL 787 #endif /* CONFIG_MEM_SOFT_DIRTY */ 788 789 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT 790 791 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 792 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 793 { 794 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 795 } 796 797 static inline bool pte_swp_soft_dirty(pte_t pte) 798 { 799 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 800 } 801 802 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 803 { 804 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 805 } 806 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 807 808 #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE 809 static inline pte_t pte_swp_mkexclusive(pte_t pte) 810 { 811 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 812 } 813 814 static inline int pte_swp_exclusive(pte_t pte) 815 { 816 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 817 } 818 819 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 820 { 821 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); 822 } 823 824 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 825 { 826 /* 827 * This check for _PAGE_RWX and _PAGE_PRESENT bits 828 */ 829 if (access & ~ptev) 830 return false; 831 /* 832 * This check for access to privilege space 833 */ 834 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 835 return false; 836 837 return true; 838 } 839 /* 840 * Generic functions with hash/radix callbacks 841 */ 842 843 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 844 pte_t *ptep, pte_t entry, 845 unsigned long address, 846 int psize) 847 { 848 if (radix_enabled()) 849 return radix__ptep_set_access_flags(vma, ptep, entry, 850 address, psize); 851 return hash__ptep_set_access_flags(ptep, entry); 852 } 853 854 #define __HAVE_ARCH_PTE_SAME 855 static inline int pte_same(pte_t pte_a, pte_t pte_b) 856 { 857 if (radix_enabled()) 858 return radix__pte_same(pte_a, pte_b); 859 return hash__pte_same(pte_a, pte_b); 860 } 861 862 static inline int pte_none(pte_t pte) 863 { 864 if (radix_enabled()) 865 return radix__pte_none(pte); 866 return hash__pte_none(pte); 867 } 868 869 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 870 pte_t *ptep, pte_t pte, int percpu) 871 { 872 873 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 874 /* 875 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 876 * in all the callers. 877 */ 878 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 879 880 if (radix_enabled()) 881 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 882 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 883 } 884 885 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 886 887 #define pgprot_noncached pgprot_noncached 888 static inline pgprot_t pgprot_noncached(pgprot_t prot) 889 { 890 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 891 _PAGE_NON_IDEMPOTENT); 892 } 893 894 #define pgprot_noncached_wc pgprot_noncached_wc 895 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 896 { 897 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 898 _PAGE_TOLERANT); 899 } 900 901 #define pgprot_cached pgprot_cached 902 static inline pgprot_t pgprot_cached(pgprot_t prot) 903 { 904 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 905 } 906 907 #define pgprot_writecombine pgprot_writecombine 908 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 909 { 910 return pgprot_noncached_wc(prot); 911 } 912 /* 913 * check a pte mapping have cache inhibited property 914 */ 915 static inline bool pte_ci(pte_t pte) 916 { 917 __be64 pte_v = pte_raw(pte); 918 919 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 920 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 921 return true; 922 return false; 923 } 924 925 static inline void pmd_clear(pmd_t *pmdp) 926 { 927 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 928 /* 929 * Don't use this if we can possibly have a hash page table 930 * entry mapping this. 931 */ 932 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 933 } 934 *pmdp = __pmd(0); 935 } 936 937 static inline int pmd_none(pmd_t pmd) 938 { 939 return !pmd_raw(pmd); 940 } 941 942 static inline int pmd_present(pmd_t pmd) 943 { 944 /* 945 * A pmd is considerent present if _PAGE_PRESENT is set. 946 * We also need to consider the pmd present which is marked 947 * invalid during a split. Hence we look for _PAGE_INVALID 948 * if we find _PAGE_PRESENT cleared. 949 */ 950 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 951 return true; 952 953 return false; 954 } 955 956 static inline int pmd_is_serializing(pmd_t pmd) 957 { 958 /* 959 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 960 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 961 * 962 * This condition may also occur when flushing a pmd while flushing 963 * it (see ptep_modify_prot_start), so callers must ensure this 964 * case is fine as well. 965 */ 966 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 967 cpu_to_be64(_PAGE_INVALID)) 968 return true; 969 970 return false; 971 } 972 973 static inline int pmd_bad(pmd_t pmd) 974 { 975 if (radix_enabled()) 976 return radix__pmd_bad(pmd); 977 return hash__pmd_bad(pmd); 978 } 979 980 static inline void pud_clear(pud_t *pudp) 981 { 982 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 983 /* 984 * Don't use this if we can possibly have a hash page table 985 * entry mapping this. 986 */ 987 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 988 } 989 *pudp = __pud(0); 990 } 991 992 static inline int pud_none(pud_t pud) 993 { 994 return !pud_raw(pud); 995 } 996 997 static inline int pud_present(pud_t pud) 998 { 999 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 1000 } 1001 1002 extern struct page *pud_page(pud_t pud); 1003 extern struct page *pmd_page(pmd_t pmd); 1004 static inline pte_t pud_pte(pud_t pud) 1005 { 1006 return __pte_raw(pud_raw(pud)); 1007 } 1008 1009 static inline pud_t pte_pud(pte_t pte) 1010 { 1011 return __pud_raw(pte_raw(pte)); 1012 } 1013 #define pud_write(pud) pte_write(pud_pte(pud)) 1014 1015 static inline int pud_bad(pud_t pud) 1016 { 1017 if (radix_enabled()) 1018 return radix__pud_bad(pud); 1019 return hash__pud_bad(pud); 1020 } 1021 1022 #define pud_access_permitted pud_access_permitted 1023 static inline bool pud_access_permitted(pud_t pud, bool write) 1024 { 1025 return pte_access_permitted(pud_pte(pud), write); 1026 } 1027 1028 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 1029 static inline __be64 p4d_raw(p4d_t x) 1030 { 1031 return pgd_raw(x.pgd); 1032 } 1033 1034 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 1035 1036 static inline void p4d_clear(p4d_t *p4dp) 1037 { 1038 *p4dp = __p4d(0); 1039 } 1040 1041 static inline int p4d_none(p4d_t p4d) 1042 { 1043 return !p4d_raw(p4d); 1044 } 1045 1046 static inline int p4d_present(p4d_t p4d) 1047 { 1048 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 1049 } 1050 1051 static inline pte_t p4d_pte(p4d_t p4d) 1052 { 1053 return __pte_raw(p4d_raw(p4d)); 1054 } 1055 1056 static inline p4d_t pte_p4d(pte_t pte) 1057 { 1058 return __p4d_raw(pte_raw(pte)); 1059 } 1060 1061 static inline int p4d_bad(p4d_t p4d) 1062 { 1063 if (radix_enabled()) 1064 return radix__p4d_bad(p4d); 1065 return hash__p4d_bad(p4d); 1066 } 1067 1068 #define p4d_access_permitted p4d_access_permitted 1069 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1070 { 1071 return pte_access_permitted(p4d_pte(p4d), write); 1072 } 1073 1074 extern struct page *p4d_page(p4d_t p4d); 1075 1076 /* Pointers in the page table tree are physical addresses */ 1077 #define __pgtable_ptr_val(ptr) __pa(ptr) 1078 1079 static inline pud_t *p4d_pgtable(p4d_t p4d) 1080 { 1081 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); 1082 } 1083 1084 static inline pmd_t *pud_pgtable(pud_t pud) 1085 { 1086 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); 1087 } 1088 1089 #define pte_ERROR(e) \ 1090 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1091 #define pmd_ERROR(e) \ 1092 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1093 #define pud_ERROR(e) \ 1094 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1095 #define pgd_ERROR(e) \ 1096 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1097 1098 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1099 { 1100 if (radix_enabled()) { 1101 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1102 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1103 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1104 #endif 1105 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1106 } 1107 return hash__map_kernel_page(ea, pa, prot); 1108 } 1109 1110 void unmap_kernel_page(unsigned long va); 1111 1112 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1113 unsigned long page_size, 1114 unsigned long phys) 1115 { 1116 if (radix_enabled()) 1117 return radix__vmemmap_create_mapping(start, page_size, phys); 1118 return hash__vmemmap_create_mapping(start, page_size, phys); 1119 } 1120 1121 #ifdef CONFIG_MEMORY_HOTPLUG 1122 static inline void vmemmap_remove_mapping(unsigned long start, 1123 unsigned long page_size) 1124 { 1125 if (radix_enabled()) 1126 return radix__vmemmap_remove_mapping(start, page_size); 1127 return hash__vmemmap_remove_mapping(start, page_size); 1128 } 1129 #endif 1130 1131 #ifdef CONFIG_DEBUG_PAGEALLOC 1132 static inline void __kernel_map_pages(struct page *page, int numpages, int enable) 1133 { 1134 if (radix_enabled()) 1135 radix__kernel_map_pages(page, numpages, enable); 1136 else 1137 hash__kernel_map_pages(page, numpages, enable); 1138 } 1139 #endif 1140 1141 static inline pte_t pmd_pte(pmd_t pmd) 1142 { 1143 return __pte_raw(pmd_raw(pmd)); 1144 } 1145 1146 static inline pmd_t pte_pmd(pte_t pte) 1147 { 1148 return __pmd_raw(pte_raw(pte)); 1149 } 1150 1151 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1152 { 1153 return (pte_t *)pmd; 1154 } 1155 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1156 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1157 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1158 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1159 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1160 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1161 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1162 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1163 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1164 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1165 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1166 1167 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1168 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1169 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1170 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1171 1172 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1173 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1174 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1175 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1176 #endif 1177 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1178 1179 #ifdef CONFIG_NUMA_BALANCING 1180 static inline int pmd_protnone(pmd_t pmd) 1181 { 1182 return pte_protnone(pmd_pte(pmd)); 1183 } 1184 #endif /* CONFIG_NUMA_BALANCING */ 1185 1186 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1187 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1188 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1189 1190 #define pmd_access_permitted pmd_access_permitted 1191 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1192 { 1193 /* 1194 * pmdp_invalidate sets this combination (which is not caught by 1195 * !pte_present() check in pte_access_permitted), to prevent 1196 * lock-free lookups, as part of the serialize_against_pte_lookup() 1197 * synchronisation. 1198 * 1199 * This also catches the case where the PTE's hardware PRESENT bit is 1200 * cleared while TLB is flushed, which is suboptimal but should not 1201 * be frequent. 1202 */ 1203 if (pmd_is_serializing(pmd)) 1204 return false; 1205 1206 return pte_access_permitted(pmd_pte(pmd), write); 1207 } 1208 1209 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1210 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1211 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1212 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1213 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1214 pmd_t *pmdp, pmd_t pmd); 1215 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1216 unsigned long addr, pmd_t *pmd) 1217 { 1218 } 1219 1220 extern int hash__has_transparent_hugepage(void); 1221 static inline int has_transparent_hugepage(void) 1222 { 1223 if (radix_enabled()) 1224 return radix__has_transparent_hugepage(); 1225 return hash__has_transparent_hugepage(); 1226 } 1227 #define has_transparent_hugepage has_transparent_hugepage 1228 1229 static inline unsigned long 1230 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1231 unsigned long clr, unsigned long set) 1232 { 1233 if (radix_enabled()) 1234 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1235 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1236 } 1237 1238 /* 1239 * returns true for pmd migration entries, THP, devmap, hugetlb 1240 * But compile time dependent on THP config 1241 */ 1242 static inline int pmd_large(pmd_t pmd) 1243 { 1244 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1245 } 1246 1247 /* 1248 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1249 * the below will work for radix too 1250 */ 1251 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1252 unsigned long addr, pmd_t *pmdp) 1253 { 1254 unsigned long old; 1255 1256 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1257 return 0; 1258 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1259 return ((old & _PAGE_ACCESSED) != 0); 1260 } 1261 1262 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1263 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1264 pmd_t *pmdp) 1265 { 1266 if (__pmd_write((*pmdp))) 1267 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1268 else if (unlikely(pmd_savedwrite(*pmdp))) 1269 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1270 } 1271 1272 /* 1273 * Only returns true for a THP. False for pmd migration entry. 1274 * We also need to return true when we come across a pte that 1275 * in between a thp split. While splitting THP, we mark the pmd 1276 * invalid (pmdp_invalidate()) before we set it with pte page 1277 * address. A pmd_trans_huge() check against a pmd entry during that time 1278 * should return true. 1279 * We should not call this on a hugetlb entry. We should check for HugeTLB 1280 * entry using vma->vm_flags 1281 * The page table walk rule is explained in Documentation/mm/transhuge.rst 1282 */ 1283 static inline int pmd_trans_huge(pmd_t pmd) 1284 { 1285 if (!pmd_present(pmd)) 1286 return false; 1287 1288 if (radix_enabled()) 1289 return radix__pmd_trans_huge(pmd); 1290 return hash__pmd_trans_huge(pmd); 1291 } 1292 1293 #define __HAVE_ARCH_PMD_SAME 1294 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1295 { 1296 if (radix_enabled()) 1297 return radix__pmd_same(pmd_a, pmd_b); 1298 return hash__pmd_same(pmd_a, pmd_b); 1299 } 1300 1301 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1302 { 1303 if (radix_enabled()) 1304 return radix__pmd_mkhuge(pmd); 1305 return hash__pmd_mkhuge(pmd); 1306 } 1307 1308 /* 1309 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1310 */ 1311 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1312 { 1313 #ifdef CONFIG_DEBUG_VM 1314 if (radix_enabled()) 1315 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1316 else 1317 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1318 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1319 #endif 1320 return pmd; 1321 } 1322 1323 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1324 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1325 unsigned long address, pmd_t *pmdp, 1326 pmd_t entry, int dirty); 1327 1328 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1329 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1330 unsigned long address, pmd_t *pmdp); 1331 1332 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1333 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1334 unsigned long addr, pmd_t *pmdp) 1335 { 1336 if (radix_enabled()) 1337 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1338 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1339 } 1340 1341 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1342 unsigned long address, pmd_t *pmdp) 1343 { 1344 if (radix_enabled()) 1345 return radix__pmdp_collapse_flush(vma, address, pmdp); 1346 return hash__pmdp_collapse_flush(vma, address, pmdp); 1347 } 1348 #define pmdp_collapse_flush pmdp_collapse_flush 1349 1350 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1351 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1352 unsigned long addr, 1353 pmd_t *pmdp, int full); 1354 1355 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1356 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1357 pmd_t *pmdp, pgtable_t pgtable) 1358 { 1359 if (radix_enabled()) 1360 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1361 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1362 } 1363 1364 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1365 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1366 pmd_t *pmdp) 1367 { 1368 if (radix_enabled()) 1369 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1370 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1371 } 1372 1373 #define __HAVE_ARCH_PMDP_INVALIDATE 1374 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1375 pmd_t *pmdp); 1376 1377 #define pmd_move_must_withdraw pmd_move_must_withdraw 1378 struct spinlock; 1379 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1380 struct spinlock *old_pmd_ptl, 1381 struct vm_area_struct *vma); 1382 /* 1383 * Hash translation mode use the deposited table to store hash pte 1384 * slot information. 1385 */ 1386 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1387 static inline bool arch_needs_pgtable_deposit(void) 1388 { 1389 if (radix_enabled()) 1390 return false; 1391 return true; 1392 } 1393 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1394 1395 1396 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1397 { 1398 if (radix_enabled()) 1399 return radix__pmd_mkdevmap(pmd); 1400 return hash__pmd_mkdevmap(pmd); 1401 } 1402 1403 static inline int pmd_devmap(pmd_t pmd) 1404 { 1405 return pte_devmap(pmd_pte(pmd)); 1406 } 1407 1408 static inline int pud_devmap(pud_t pud) 1409 { 1410 return 0; 1411 } 1412 1413 static inline int pgd_devmap(pgd_t pgd) 1414 { 1415 return 0; 1416 } 1417 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1418 1419 static inline int pud_pfn(pud_t pud) 1420 { 1421 /* 1422 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1423 * check so this should never be used. If it grows another user we 1424 * want to know about it. 1425 */ 1426 BUILD_BUG(); 1427 return 0; 1428 } 1429 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1430 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1431 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1432 pte_t *, pte_t, pte_t); 1433 1434 /* 1435 * Returns true for a R -> RW upgrade of pte 1436 */ 1437 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1438 { 1439 if (!(old_val & _PAGE_READ)) 1440 return false; 1441 1442 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1443 return true; 1444 1445 return false; 1446 } 1447 1448 /* 1449 * Like pmd_huge() and pmd_large(), but works regardless of config options 1450 */ 1451 #define pmd_is_leaf pmd_is_leaf 1452 #define pmd_leaf pmd_is_leaf 1453 static inline bool pmd_is_leaf(pmd_t pmd) 1454 { 1455 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1456 } 1457 1458 #define pud_is_leaf pud_is_leaf 1459 #define pud_leaf pud_is_leaf 1460 static inline bool pud_is_leaf(pud_t pud) 1461 { 1462 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1463 } 1464 1465 #define p4d_is_leaf p4d_is_leaf 1466 #define p4d_leaf p4d_is_leaf 1467 static inline bool p4d_is_leaf(p4d_t p4d) 1468 { 1469 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1470 } 1471 1472 #endif /* __ASSEMBLY__ */ 1473 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1474