1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x00040UL 36 37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 /* 46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 48 * differentiate between two use a SW field when invalidating. 49 * 50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 51 * 52 * This is used only when _PAGE_PRESENT is cleared. 53 */ 54 #define _PAGE_INVALID _RPAGE_SW0 55 56 /* 57 * Top and bottom bits of RPN which can be used by hash 58 * translation mode, because we expect them to be zero 59 * otherwise. 60 */ 61 #define _RPAGE_RPN0 0x01000 62 #define _RPAGE_RPN1 0x02000 63 #define _RPAGE_RPN43 0x0080000000000000UL 64 #define _RPAGE_RPN42 0x0040000000000000UL 65 #define _RPAGE_RPN41 0x0020000000000000UL 66 67 /* Max physical address bit as per radix table */ 68 #define _RPAGE_PA_MAX 56 69 70 /* 71 * Max physical address bit we will use for now. 72 * 73 * This is mostly a hardware limitation and for now Power9 has 74 * a 51 bit limit. 75 * 76 * This is different from the number of physical bit required to address 77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 79 * number of sections we can support (SECTIONS_SHIFT). 80 * 81 * This is different from Radix page table limitation above and 82 * should always be less than that. The limit is done such that 83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 84 * for hash linux page table specific bits. 85 * 86 * In order to be compatible with future hardware generations we keep 87 * some offsets and limit this for now to 53 88 */ 89 #define _PAGE_PA_MAX 53 90 91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 120 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 121 _PAGE_RW | _PAGE_EXEC) 122 /* 123 * _PAGE_CHG_MASK masks of bits that are to be preserved across 124 * pgprot changes 125 */ 126 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 127 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 128 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 129 130 /* 131 * We define 2 sets of base prot bits, one for basic pages (ie, 132 * cacheable kernel and user pages) and one for non cacheable 133 * pages. We always set _PAGE_COHERENT when SMP is enabled or 134 * the processor might need it for DMA coherency. 135 */ 136 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 137 #define _PAGE_BASE (_PAGE_BASE_NC) 138 139 /* Permission masks used to generate the __P and __S table, 140 * 141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 142 * 143 * Write permissions imply read permissions for now (we could make write-only 144 * pages on BookE but we don't bother for now). Execute permission control is 145 * possible on platforms that define _PAGE_EXEC 146 */ 147 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 148 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 149 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 150 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 151 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 152 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 153 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 154 155 /* Permission masks used for kernel mappings */ 156 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 157 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 158 _PAGE_TOLERANT) 159 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 160 _PAGE_NON_IDEMPOTENT) 161 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 162 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 163 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 164 165 /* 166 * Protection used for kernel text. We want the debuggers to be able to 167 * set breakpoints anywhere, so don't write protect the kernel text 168 * on platforms where such control is possible. 169 */ 170 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 171 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 172 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 173 #else 174 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 175 #endif 176 177 /* Make modules code happy. We don't set RO yet */ 178 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 179 #define PAGE_AGP (PAGE_KERNEL_NC) 180 181 #ifndef __ASSEMBLY__ 182 /* 183 * page table defines 184 */ 185 extern unsigned long __pte_index_size; 186 extern unsigned long __pmd_index_size; 187 extern unsigned long __pud_index_size; 188 extern unsigned long __pgd_index_size; 189 extern unsigned long __pud_cache_index; 190 #define PTE_INDEX_SIZE __pte_index_size 191 #define PMD_INDEX_SIZE __pmd_index_size 192 #define PUD_INDEX_SIZE __pud_index_size 193 #define PGD_INDEX_SIZE __pgd_index_size 194 /* pmd table use page table fragments */ 195 #define PMD_CACHE_INDEX 0 196 #define PUD_CACHE_INDEX __pud_cache_index 197 /* 198 * Because of use of pte fragments and THP, size of page table 199 * are not always derived out of index size above. 200 */ 201 extern unsigned long __pte_table_size; 202 extern unsigned long __pmd_table_size; 203 extern unsigned long __pud_table_size; 204 extern unsigned long __pgd_table_size; 205 #define PTE_TABLE_SIZE __pte_table_size 206 #define PMD_TABLE_SIZE __pmd_table_size 207 #define PUD_TABLE_SIZE __pud_table_size 208 #define PGD_TABLE_SIZE __pgd_table_size 209 210 extern unsigned long __pmd_val_bits; 211 extern unsigned long __pud_val_bits; 212 extern unsigned long __pgd_val_bits; 213 #define PMD_VAL_BITS __pmd_val_bits 214 #define PUD_VAL_BITS __pud_val_bits 215 #define PGD_VAL_BITS __pgd_val_bits 216 217 extern unsigned long __pte_frag_nr; 218 #define PTE_FRAG_NR __pte_frag_nr 219 extern unsigned long __pte_frag_size_shift; 220 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 221 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 222 223 extern unsigned long __pmd_frag_nr; 224 #define PMD_FRAG_NR __pmd_frag_nr 225 extern unsigned long __pmd_frag_size_shift; 226 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 227 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 228 229 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 230 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 231 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 232 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 233 234 /* PMD_SHIFT determines what a second-level page table entry can map */ 235 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 236 #define PMD_SIZE (1UL << PMD_SHIFT) 237 #define PMD_MASK (~(PMD_SIZE-1)) 238 239 /* PUD_SHIFT determines what a third-level page table entry can map */ 240 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 241 #define PUD_SIZE (1UL << PUD_SHIFT) 242 #define PUD_MASK (~(PUD_SIZE-1)) 243 244 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 245 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 246 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 247 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 248 249 /* Bits to mask out from a PMD to get to the PTE page */ 250 #define PMD_MASKED_BITS 0xc0000000000000ffUL 251 /* Bits to mask out from a PUD to get to the PMD page */ 252 #define PUD_MASKED_BITS 0xc0000000000000ffUL 253 /* Bits to mask out from a PGD to get to the PUD page */ 254 #define P4D_MASKED_BITS 0xc0000000000000ffUL 255 256 /* 257 * Used as an indicator for rcu callback functions 258 */ 259 enum pgtable_index { 260 PTE_INDEX = 0, 261 PMD_INDEX, 262 PUD_INDEX, 263 PGD_INDEX, 264 /* 265 * Below are used with 4k page size and hugetlb 266 */ 267 HTLB_16M_INDEX, 268 HTLB_16G_INDEX, 269 }; 270 271 extern unsigned long __vmalloc_start; 272 extern unsigned long __vmalloc_end; 273 #define VMALLOC_START __vmalloc_start 274 #define VMALLOC_END __vmalloc_end 275 276 static inline unsigned int ioremap_max_order(void) 277 { 278 if (radix_enabled()) 279 return PUD_SHIFT; 280 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 281 } 282 #define IOREMAP_MAX_ORDER ioremap_max_order() 283 284 extern unsigned long __kernel_virt_start; 285 extern unsigned long __kernel_io_start; 286 extern unsigned long __kernel_io_end; 287 #define KERN_VIRT_START __kernel_virt_start 288 #define KERN_IO_START __kernel_io_start 289 #define KERN_IO_END __kernel_io_end 290 291 extern struct page *vmemmap; 292 extern unsigned long pci_io_base; 293 #endif /* __ASSEMBLY__ */ 294 295 #include <asm/book3s/64/hash.h> 296 #include <asm/book3s/64/radix.h> 297 298 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 299 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 300 #else 301 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 302 #endif 303 304 305 #ifdef CONFIG_PPC_64K_PAGES 306 #include <asm/book3s/64/pgtable-64k.h> 307 #else 308 #include <asm/book3s/64/pgtable-4k.h> 309 #endif 310 311 #include <asm/barrier.h> 312 /* 313 * IO space itself carved into the PIO region (ISA and PHB IO space) and 314 * the ioremap space 315 * 316 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 317 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 318 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 319 */ 320 #define FULL_IO_SIZE 0x80000000ul 321 #define ISA_IO_BASE (KERN_IO_START) 322 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 323 #define PHB_IO_BASE (ISA_IO_END) 324 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 325 #define IOREMAP_BASE (PHB_IO_END) 326 #define IOREMAP_START (ioremap_bot) 327 #define IOREMAP_END (KERN_IO_END) 328 329 /* Advertise special mapping type for AGP */ 330 #define HAVE_PAGE_AGP 331 332 #ifndef __ASSEMBLY__ 333 334 /* 335 * This is the default implementation of various PTE accessors, it's 336 * used in all cases except Book3S with 64K pages where we have a 337 * concept of sub-pages 338 */ 339 #ifndef __real_pte 340 341 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 342 #define __rpte_to_pte(r) ((r).pte) 343 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 344 345 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 346 do { \ 347 index = 0; \ 348 shift = mmu_psize_defs[psize].shift; \ 349 350 #define pte_iterate_hashed_end() } while(0) 351 352 /* 353 * We expect this to be called only for user addresses or kernel virtual 354 * addresses other than the linear mapping. 355 */ 356 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 357 358 #endif /* __real_pte */ 359 360 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 361 pte_t *ptep, unsigned long clr, 362 unsigned long set, int huge) 363 { 364 if (radix_enabled()) 365 return radix__pte_update(mm, addr, ptep, clr, set, huge); 366 return hash__pte_update(mm, addr, ptep, clr, set, huge); 367 } 368 /* 369 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 370 * We currently remove entries from the hashtable regardless of whether 371 * the entry was young or dirty. 372 * 373 * We should be more intelligent about this but for the moment we override 374 * these functions and force a tlb flush unconditionally 375 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 376 * function for both hash and radix. 377 */ 378 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 379 unsigned long addr, pte_t *ptep) 380 { 381 unsigned long old; 382 383 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 384 return 0; 385 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 386 return (old & _PAGE_ACCESSED) != 0; 387 } 388 389 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 390 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 391 ({ \ 392 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 393 }) 394 395 /* 396 * On Book3S CPUs, clearing the accessed bit without a TLB flush 397 * doesn't cause data corruption. [ It could cause incorrect 398 * page aging and the (mistaken) reclaim of hot pages, but the 399 * chance of that should be relatively low. ] 400 * 401 * So as a performance optimization don't flush the TLB when 402 * clearing the accessed bit, it will eventually be flushed by 403 * a context switch or a VM operation anyway. [ In the rare 404 * event of it not getting flushed for a long time the delay 405 * shouldn't really matter because there's no real memory 406 * pressure for swapout to react to. ] 407 */ 408 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 409 #define ptep_clear_flush_young ptep_test_and_clear_young 410 411 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 412 #define pmdp_clear_flush_young pmdp_test_and_clear_young 413 414 static inline int __pte_write(pte_t pte) 415 { 416 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 417 } 418 419 #ifdef CONFIG_NUMA_BALANCING 420 #define pte_savedwrite pte_savedwrite 421 static inline bool pte_savedwrite(pte_t pte) 422 { 423 /* 424 * Saved write ptes are prot none ptes that doesn't have 425 * privileged bit sit. We mark prot none as one which has 426 * present and pviliged bit set and RWX cleared. To mark 427 * protnone which used to have _PAGE_WRITE set we clear 428 * the privileged bit. 429 */ 430 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 431 } 432 #else 433 #define pte_savedwrite pte_savedwrite 434 static inline bool pte_savedwrite(pte_t pte) 435 { 436 return false; 437 } 438 #endif 439 440 static inline int pte_write(pte_t pte) 441 { 442 return __pte_write(pte) || pte_savedwrite(pte); 443 } 444 445 static inline int pte_read(pte_t pte) 446 { 447 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 448 } 449 450 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 451 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 452 pte_t *ptep) 453 { 454 if (__pte_write(*ptep)) 455 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 456 else if (unlikely(pte_savedwrite(*ptep))) 457 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 458 } 459 460 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 461 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 462 unsigned long addr, pte_t *ptep) 463 { 464 /* 465 * We should not find protnone for hugetlb, but this complete the 466 * interface. 467 */ 468 if (__pte_write(*ptep)) 469 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 470 else if (unlikely(pte_savedwrite(*ptep))) 471 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 472 } 473 474 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 475 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 476 unsigned long addr, pte_t *ptep) 477 { 478 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 479 return __pte(old); 480 } 481 482 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 483 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 484 unsigned long addr, 485 pte_t *ptep, int full) 486 { 487 if (full && radix_enabled()) { 488 /* 489 * We know that this is a full mm pte clear and 490 * hence can be sure there is no parallel set_pte. 491 */ 492 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 493 } 494 return ptep_get_and_clear(mm, addr, ptep); 495 } 496 497 498 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 499 pte_t * ptep) 500 { 501 pte_update(mm, addr, ptep, ~0UL, 0, 0); 502 } 503 504 static inline int pte_dirty(pte_t pte) 505 { 506 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 507 } 508 509 static inline int pte_young(pte_t pte) 510 { 511 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 512 } 513 514 static inline int pte_special(pte_t pte) 515 { 516 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 517 } 518 519 static inline bool pte_exec(pte_t pte) 520 { 521 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 522 } 523 524 525 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 526 static inline bool pte_soft_dirty(pte_t pte) 527 { 528 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 529 } 530 531 static inline pte_t pte_mksoft_dirty(pte_t pte) 532 { 533 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 534 } 535 536 static inline pte_t pte_clear_soft_dirty(pte_t pte) 537 { 538 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 539 } 540 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 541 542 #ifdef CONFIG_NUMA_BALANCING 543 static inline int pte_protnone(pte_t pte) 544 { 545 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 546 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 547 } 548 549 #define pte_mk_savedwrite pte_mk_savedwrite 550 static inline pte_t pte_mk_savedwrite(pte_t pte) 551 { 552 /* 553 * Used by Autonuma subsystem to preserve the write bit 554 * while marking the pte PROT_NONE. Only allow this 555 * on PROT_NONE pte 556 */ 557 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 558 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 559 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 560 } 561 562 #define pte_clear_savedwrite pte_clear_savedwrite 563 static inline pte_t pte_clear_savedwrite(pte_t pte) 564 { 565 /* 566 * Used by KSM subsystem to make a protnone pte readonly. 567 */ 568 VM_BUG_ON(!pte_protnone(pte)); 569 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 570 } 571 #else 572 #define pte_clear_savedwrite pte_clear_savedwrite 573 static inline pte_t pte_clear_savedwrite(pte_t pte) 574 { 575 VM_WARN_ON(1); 576 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 577 } 578 #endif /* CONFIG_NUMA_BALANCING */ 579 580 static inline bool pte_hw_valid(pte_t pte) 581 { 582 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 583 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 584 } 585 586 static inline int pte_present(pte_t pte) 587 { 588 /* 589 * A pte is considerent present if _PAGE_PRESENT is set. 590 * We also need to consider the pte present which is marked 591 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 592 * if we find _PAGE_PRESENT cleared. 593 */ 594 595 if (pte_hw_valid(pte)) 596 return true; 597 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 598 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 599 } 600 601 #ifdef CONFIG_PPC_MEM_KEYS 602 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 603 #else 604 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 605 { 606 return true; 607 } 608 #endif /* CONFIG_PPC_MEM_KEYS */ 609 610 static inline bool pte_user(pte_t pte) 611 { 612 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 613 } 614 615 #define pte_access_permitted pte_access_permitted 616 static inline bool pte_access_permitted(pte_t pte, bool write) 617 { 618 /* 619 * _PAGE_READ is needed for any access and will be 620 * cleared for PROT_NONE 621 */ 622 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 623 return false; 624 625 if (write && !pte_write(pte)) 626 return false; 627 628 return arch_pte_access_permitted(pte_val(pte), write, 0); 629 } 630 631 /* 632 * Conversion functions: convert a page and protection to a page entry, 633 * and a page entry and page directory to the page they refer to. 634 * 635 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 636 * long for now. 637 */ 638 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 639 { 640 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 641 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 642 643 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 644 } 645 646 static inline unsigned long pte_pfn(pte_t pte) 647 { 648 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 649 } 650 651 /* Generic modifiers for PTE bits */ 652 static inline pte_t pte_wrprotect(pte_t pte) 653 { 654 if (unlikely(pte_savedwrite(pte))) 655 return pte_clear_savedwrite(pte); 656 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 657 } 658 659 static inline pte_t pte_exprotect(pte_t pte) 660 { 661 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 662 } 663 664 static inline pte_t pte_mkclean(pte_t pte) 665 { 666 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 667 } 668 669 static inline pte_t pte_mkold(pte_t pte) 670 { 671 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 672 } 673 674 static inline pte_t pte_mkexec(pte_t pte) 675 { 676 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 677 } 678 679 static inline pte_t pte_mkwrite(pte_t pte) 680 { 681 /* 682 * write implies read, hence set both 683 */ 684 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 685 } 686 687 static inline pte_t pte_mkdirty(pte_t pte) 688 { 689 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 690 } 691 692 static inline pte_t pte_mkyoung(pte_t pte) 693 { 694 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 695 } 696 697 static inline pte_t pte_mkspecial(pte_t pte) 698 { 699 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 700 } 701 702 static inline pte_t pte_mkhuge(pte_t pte) 703 { 704 return pte; 705 } 706 707 static inline pte_t pte_mkdevmap(pte_t pte) 708 { 709 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 710 } 711 712 static inline pte_t pte_mkprivileged(pte_t pte) 713 { 714 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 715 } 716 717 static inline pte_t pte_mkuser(pte_t pte) 718 { 719 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 720 } 721 722 /* 723 * This is potentially called with a pmd as the argument, in which case it's not 724 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 725 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 726 * use in page directory entries (ie. non-ptes). 727 */ 728 static inline int pte_devmap(pte_t pte) 729 { 730 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 731 732 return (pte_raw(pte) & mask) == mask; 733 } 734 735 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 736 { 737 /* FIXME!! check whether this need to be a conditional */ 738 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 739 cpu_to_be64(pgprot_val(newprot))); 740 } 741 742 /* Encode and de-code a swap entry */ 743 #define MAX_SWAPFILES_CHECK() do { \ 744 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 745 /* \ 746 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 747 * We filter HPTEFLAGS on set_pte. \ 748 */ \ 749 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 750 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 751 } while (0) 752 753 #define SWP_TYPE_BITS 5 754 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 755 & ((1UL << SWP_TYPE_BITS) - 1)) 756 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 757 #define __swp_entry(type, offset) ((swp_entry_t) { \ 758 ((type) << _PAGE_BIT_SWAP_TYPE) \ 759 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 760 /* 761 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 762 * swap type and offset we get from swap and convert that to pte to find a 763 * matching pte in linux page table. 764 * Clear bits not found in swap entries here. 765 */ 766 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 767 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 768 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 769 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 770 771 #ifdef CONFIG_MEM_SOFT_DIRTY 772 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 773 #else 774 #define _PAGE_SWP_SOFT_DIRTY 0UL 775 #endif /* CONFIG_MEM_SOFT_DIRTY */ 776 777 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 778 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 779 { 780 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 781 } 782 783 static inline bool pte_swp_soft_dirty(pte_t pte) 784 { 785 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 786 } 787 788 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 789 { 790 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 791 } 792 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 793 794 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 795 { 796 /* 797 * This check for _PAGE_RWX and _PAGE_PRESENT bits 798 */ 799 if (access & ~ptev) 800 return false; 801 /* 802 * This check for access to privilege space 803 */ 804 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 805 return false; 806 807 return true; 808 } 809 /* 810 * Generic functions with hash/radix callbacks 811 */ 812 813 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 814 pte_t *ptep, pte_t entry, 815 unsigned long address, 816 int psize) 817 { 818 if (radix_enabled()) 819 return radix__ptep_set_access_flags(vma, ptep, entry, 820 address, psize); 821 return hash__ptep_set_access_flags(ptep, entry); 822 } 823 824 #define __HAVE_ARCH_PTE_SAME 825 static inline int pte_same(pte_t pte_a, pte_t pte_b) 826 { 827 if (radix_enabled()) 828 return radix__pte_same(pte_a, pte_b); 829 return hash__pte_same(pte_a, pte_b); 830 } 831 832 static inline int pte_none(pte_t pte) 833 { 834 if (radix_enabled()) 835 return radix__pte_none(pte); 836 return hash__pte_none(pte); 837 } 838 839 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 840 pte_t *ptep, pte_t pte, int percpu) 841 { 842 843 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 844 /* 845 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 846 * in all the callers. 847 */ 848 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 849 850 if (radix_enabled()) 851 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 852 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 853 } 854 855 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 856 857 #define pgprot_noncached pgprot_noncached 858 static inline pgprot_t pgprot_noncached(pgprot_t prot) 859 { 860 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 861 _PAGE_NON_IDEMPOTENT); 862 } 863 864 #define pgprot_noncached_wc pgprot_noncached_wc 865 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 866 { 867 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 868 _PAGE_TOLERANT); 869 } 870 871 #define pgprot_cached pgprot_cached 872 static inline pgprot_t pgprot_cached(pgprot_t prot) 873 { 874 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 875 } 876 877 #define pgprot_writecombine pgprot_writecombine 878 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 879 { 880 return pgprot_noncached_wc(prot); 881 } 882 /* 883 * check a pte mapping have cache inhibited property 884 */ 885 static inline bool pte_ci(pte_t pte) 886 { 887 __be64 pte_v = pte_raw(pte); 888 889 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 890 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 891 return true; 892 return false; 893 } 894 895 static inline void pmd_clear(pmd_t *pmdp) 896 { 897 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 898 /* 899 * Don't use this if we can possibly have a hash page table 900 * entry mapping this. 901 */ 902 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 903 } 904 *pmdp = __pmd(0); 905 } 906 907 static inline int pmd_none(pmd_t pmd) 908 { 909 return !pmd_raw(pmd); 910 } 911 912 static inline int pmd_present(pmd_t pmd) 913 { 914 /* 915 * A pmd is considerent present if _PAGE_PRESENT is set. 916 * We also need to consider the pmd present which is marked 917 * invalid during a split. Hence we look for _PAGE_INVALID 918 * if we find _PAGE_PRESENT cleared. 919 */ 920 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 921 return true; 922 923 return false; 924 } 925 926 static inline int pmd_is_serializing(pmd_t pmd) 927 { 928 /* 929 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 930 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 931 * 932 * This condition may also occur when flushing a pmd while flushing 933 * it (see ptep_modify_prot_start), so callers must ensure this 934 * case is fine as well. 935 */ 936 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 937 cpu_to_be64(_PAGE_INVALID)) 938 return true; 939 940 return false; 941 } 942 943 static inline int pmd_bad(pmd_t pmd) 944 { 945 if (radix_enabled()) 946 return radix__pmd_bad(pmd); 947 return hash__pmd_bad(pmd); 948 } 949 950 static inline void pud_clear(pud_t *pudp) 951 { 952 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 953 /* 954 * Don't use this if we can possibly have a hash page table 955 * entry mapping this. 956 */ 957 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 958 } 959 *pudp = __pud(0); 960 } 961 962 static inline int pud_none(pud_t pud) 963 { 964 return !pud_raw(pud); 965 } 966 967 static inline int pud_present(pud_t pud) 968 { 969 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 970 } 971 972 extern struct page *pud_page(pud_t pud); 973 extern struct page *pmd_page(pmd_t pmd); 974 static inline pte_t pud_pte(pud_t pud) 975 { 976 return __pte_raw(pud_raw(pud)); 977 } 978 979 static inline pud_t pte_pud(pte_t pte) 980 { 981 return __pud_raw(pte_raw(pte)); 982 } 983 #define pud_write(pud) pte_write(pud_pte(pud)) 984 985 static inline int pud_bad(pud_t pud) 986 { 987 if (radix_enabled()) 988 return radix__pud_bad(pud); 989 return hash__pud_bad(pud); 990 } 991 992 #define pud_access_permitted pud_access_permitted 993 static inline bool pud_access_permitted(pud_t pud, bool write) 994 { 995 return pte_access_permitted(pud_pte(pud), write); 996 } 997 998 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 999 static inline __be64 p4d_raw(p4d_t x) 1000 { 1001 return pgd_raw(x.pgd); 1002 } 1003 1004 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 1005 1006 static inline void p4d_clear(p4d_t *p4dp) 1007 { 1008 *p4dp = __p4d(0); 1009 } 1010 1011 static inline int p4d_none(p4d_t p4d) 1012 { 1013 return !p4d_raw(p4d); 1014 } 1015 1016 static inline int p4d_present(p4d_t p4d) 1017 { 1018 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 1019 } 1020 1021 static inline pte_t p4d_pte(p4d_t p4d) 1022 { 1023 return __pte_raw(p4d_raw(p4d)); 1024 } 1025 1026 static inline p4d_t pte_p4d(pte_t pte) 1027 { 1028 return __p4d_raw(pte_raw(pte)); 1029 } 1030 1031 static inline int p4d_bad(p4d_t p4d) 1032 { 1033 if (radix_enabled()) 1034 return radix__p4d_bad(p4d); 1035 return hash__p4d_bad(p4d); 1036 } 1037 1038 #define p4d_access_permitted p4d_access_permitted 1039 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1040 { 1041 return pte_access_permitted(p4d_pte(p4d), write); 1042 } 1043 1044 extern struct page *p4d_page(p4d_t p4d); 1045 1046 /* Pointers in the page table tree are physical addresses */ 1047 #define __pgtable_ptr_val(ptr) __pa(ptr) 1048 1049 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 1050 #define p4d_page_vaddr(p4d) __va(p4d_val(p4d) & ~P4D_MASKED_BITS) 1051 1052 #define pte_ERROR(e) \ 1053 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1054 #define pmd_ERROR(e) \ 1055 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1056 #define pud_ERROR(e) \ 1057 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1058 #define pgd_ERROR(e) \ 1059 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1060 1061 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1062 { 1063 if (radix_enabled()) { 1064 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1065 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1066 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1067 #endif 1068 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1069 } 1070 return hash__map_kernel_page(ea, pa, prot); 1071 } 1072 1073 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1074 unsigned long page_size, 1075 unsigned long phys) 1076 { 1077 if (radix_enabled()) 1078 return radix__vmemmap_create_mapping(start, page_size, phys); 1079 return hash__vmemmap_create_mapping(start, page_size, phys); 1080 } 1081 1082 #ifdef CONFIG_MEMORY_HOTPLUG 1083 static inline void vmemmap_remove_mapping(unsigned long start, 1084 unsigned long page_size) 1085 { 1086 if (radix_enabled()) 1087 return radix__vmemmap_remove_mapping(start, page_size); 1088 return hash__vmemmap_remove_mapping(start, page_size); 1089 } 1090 #endif 1091 1092 static inline pte_t pmd_pte(pmd_t pmd) 1093 { 1094 return __pte_raw(pmd_raw(pmd)); 1095 } 1096 1097 static inline pmd_t pte_pmd(pte_t pte) 1098 { 1099 return __pmd_raw(pte_raw(pte)); 1100 } 1101 1102 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1103 { 1104 return (pte_t *)pmd; 1105 } 1106 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1107 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1108 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1109 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1110 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1111 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1112 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1113 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1114 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1115 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1116 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1117 1118 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1119 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1120 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1121 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1122 1123 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1124 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1125 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1126 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1127 #endif 1128 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1129 1130 #ifdef CONFIG_NUMA_BALANCING 1131 static inline int pmd_protnone(pmd_t pmd) 1132 { 1133 return pte_protnone(pmd_pte(pmd)); 1134 } 1135 #endif /* CONFIG_NUMA_BALANCING */ 1136 1137 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1138 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1139 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1140 1141 #define pmd_access_permitted pmd_access_permitted 1142 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1143 { 1144 /* 1145 * pmdp_invalidate sets this combination (which is not caught by 1146 * !pte_present() check in pte_access_permitted), to prevent 1147 * lock-free lookups, as part of the serialize_against_pte_lookup() 1148 * synchronisation. 1149 * 1150 * This also catches the case where the PTE's hardware PRESENT bit is 1151 * cleared while TLB is flushed, which is suboptimal but should not 1152 * be frequent. 1153 */ 1154 if (pmd_is_serializing(pmd)) 1155 return false; 1156 1157 return pte_access_permitted(pmd_pte(pmd), write); 1158 } 1159 1160 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1161 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1162 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1163 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1164 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1165 pmd_t *pmdp, pmd_t pmd); 1166 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1167 unsigned long addr, pmd_t *pmd) 1168 { 1169 } 1170 1171 extern int hash__has_transparent_hugepage(void); 1172 static inline int has_transparent_hugepage(void) 1173 { 1174 if (radix_enabled()) 1175 return radix__has_transparent_hugepage(); 1176 return hash__has_transparent_hugepage(); 1177 } 1178 #define has_transparent_hugepage has_transparent_hugepage 1179 1180 static inline unsigned long 1181 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1182 unsigned long clr, unsigned long set) 1183 { 1184 if (radix_enabled()) 1185 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1186 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1187 } 1188 1189 /* 1190 * returns true for pmd migration entries, THP, devmap, hugetlb 1191 * But compile time dependent on THP config 1192 */ 1193 static inline int pmd_large(pmd_t pmd) 1194 { 1195 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1196 } 1197 1198 /* 1199 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1200 * the below will work for radix too 1201 */ 1202 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1203 unsigned long addr, pmd_t *pmdp) 1204 { 1205 unsigned long old; 1206 1207 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1208 return 0; 1209 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1210 return ((old & _PAGE_ACCESSED) != 0); 1211 } 1212 1213 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1214 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1215 pmd_t *pmdp) 1216 { 1217 if (__pmd_write((*pmdp))) 1218 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1219 else if (unlikely(pmd_savedwrite(*pmdp))) 1220 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1221 } 1222 1223 /* 1224 * Only returns true for a THP. False for pmd migration entry. 1225 * We also need to return true when we come across a pte that 1226 * in between a thp split. While splitting THP, we mark the pmd 1227 * invalid (pmdp_invalidate()) before we set it with pte page 1228 * address. A pmd_trans_huge() check against a pmd entry during that time 1229 * should return true. 1230 * We should not call this on a hugetlb entry. We should check for HugeTLB 1231 * entry using vma->vm_flags 1232 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1233 */ 1234 static inline int pmd_trans_huge(pmd_t pmd) 1235 { 1236 if (!pmd_present(pmd)) 1237 return false; 1238 1239 if (radix_enabled()) 1240 return radix__pmd_trans_huge(pmd); 1241 return hash__pmd_trans_huge(pmd); 1242 } 1243 1244 #define __HAVE_ARCH_PMD_SAME 1245 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1246 { 1247 if (radix_enabled()) 1248 return radix__pmd_same(pmd_a, pmd_b); 1249 return hash__pmd_same(pmd_a, pmd_b); 1250 } 1251 1252 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1253 { 1254 if (radix_enabled()) 1255 return radix__pmd_mkhuge(pmd); 1256 return hash__pmd_mkhuge(pmd); 1257 } 1258 1259 /* 1260 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1261 */ 1262 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1263 { 1264 #ifdef CONFIG_DEBUG_VM 1265 if (radix_enabled()) 1266 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1267 else 1268 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1269 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1270 #endif 1271 return pmd; 1272 } 1273 1274 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1275 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1276 unsigned long address, pmd_t *pmdp, 1277 pmd_t entry, int dirty); 1278 1279 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1280 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1281 unsigned long address, pmd_t *pmdp); 1282 1283 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1284 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1285 unsigned long addr, pmd_t *pmdp) 1286 { 1287 if (radix_enabled()) 1288 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1289 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1290 } 1291 1292 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1293 unsigned long address, pmd_t *pmdp) 1294 { 1295 if (radix_enabled()) 1296 return radix__pmdp_collapse_flush(vma, address, pmdp); 1297 return hash__pmdp_collapse_flush(vma, address, pmdp); 1298 } 1299 #define pmdp_collapse_flush pmdp_collapse_flush 1300 1301 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1302 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1303 unsigned long addr, 1304 pmd_t *pmdp, int full); 1305 1306 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1307 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1308 pmd_t *pmdp, pgtable_t pgtable) 1309 { 1310 if (radix_enabled()) 1311 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1312 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1313 } 1314 1315 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1316 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1317 pmd_t *pmdp) 1318 { 1319 if (radix_enabled()) 1320 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1321 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1322 } 1323 1324 #define __HAVE_ARCH_PMDP_INVALIDATE 1325 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1326 pmd_t *pmdp); 1327 1328 #define pmd_move_must_withdraw pmd_move_must_withdraw 1329 struct spinlock; 1330 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1331 struct spinlock *old_pmd_ptl, 1332 struct vm_area_struct *vma); 1333 /* 1334 * Hash translation mode use the deposited table to store hash pte 1335 * slot information. 1336 */ 1337 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1338 static inline bool arch_needs_pgtable_deposit(void) 1339 { 1340 if (radix_enabled()) 1341 return false; 1342 return true; 1343 } 1344 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1345 1346 1347 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1348 { 1349 if (radix_enabled()) 1350 return radix__pmd_mkdevmap(pmd); 1351 return hash__pmd_mkdevmap(pmd); 1352 } 1353 1354 static inline int pmd_devmap(pmd_t pmd) 1355 { 1356 return pte_devmap(pmd_pte(pmd)); 1357 } 1358 1359 static inline int pud_devmap(pud_t pud) 1360 { 1361 return 0; 1362 } 1363 1364 static inline int pgd_devmap(pgd_t pgd) 1365 { 1366 return 0; 1367 } 1368 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1369 1370 static inline int pud_pfn(pud_t pud) 1371 { 1372 /* 1373 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1374 * check so this should never be used. If it grows another user we 1375 * want to know about it. 1376 */ 1377 BUILD_BUG(); 1378 return 0; 1379 } 1380 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1381 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1382 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1383 pte_t *, pte_t, pte_t); 1384 1385 /* 1386 * Returns true for a R -> RW upgrade of pte 1387 */ 1388 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1389 { 1390 if (!(old_val & _PAGE_READ)) 1391 return false; 1392 1393 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1394 return true; 1395 1396 return false; 1397 } 1398 1399 /* 1400 * Like pmd_huge() and pmd_large(), but works regardless of config options 1401 */ 1402 #define pmd_is_leaf pmd_is_leaf 1403 #define pmd_leaf pmd_is_leaf 1404 static inline bool pmd_is_leaf(pmd_t pmd) 1405 { 1406 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1407 } 1408 1409 #define pud_is_leaf pud_is_leaf 1410 #define pud_leaf pud_is_leaf 1411 static inline bool pud_is_leaf(pud_t pud) 1412 { 1413 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1414 } 1415 1416 #define p4d_is_leaf p4d_is_leaf 1417 #define p4d_leaf p4d_is_leaf 1418 static inline bool p4d_is_leaf(p4d_t p4d) 1419 { 1420 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1421 } 1422 1423 #endif /* __ASSEMBLY__ */ 1424 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1425