1 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 2 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 /* 4 * This file contains the functions and defines necessary to modify and use 5 * the ppc64 hashed page table. 6 */ 7 8 #include <asm/book3s/64/hash.h> 9 #include <asm/barrier.h> 10 11 12 /* 13 * Size of EA range mapped by our pagetables. 14 */ 15 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ 16 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) 17 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE) 18 19 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 20 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1) 21 #else 22 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 23 #endif 24 /* 25 * Define the address range of the kernel non-linear virtual area 26 */ 27 #define KERN_VIRT_START ASM_CONST(0xD000000000000000) 28 #define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000) 29 /* 30 * The vmalloc space starts at the beginning of that region, and 31 * occupies half of it on hash CPUs and a quarter of it on Book3E 32 * (we keep a quarter for the virtual memmap) 33 */ 34 #define VMALLOC_START KERN_VIRT_START 35 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 36 #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE) 37 /* 38 * The second half of the kernel virtual space is used for IO mappings, 39 * it's itself carved into the PIO region (ISA and PHB IO space) and 40 * the ioremap space 41 * 42 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 43 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 44 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 45 */ 46 #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1)) 47 #define FULL_IO_SIZE 0x80000000ul 48 #define ISA_IO_BASE (KERN_IO_START) 49 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 50 #define PHB_IO_BASE (ISA_IO_END) 51 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 52 #define IOREMAP_BASE (PHB_IO_END) 53 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 54 55 /* 56 * Region IDs 57 */ 58 #define REGION_SHIFT 60UL 59 #define REGION_MASK (0xfUL << REGION_SHIFT) 60 #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT) 61 62 #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START)) 63 #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET)) 64 #define VMEMMAP_REGION_ID (0xfUL) /* Server only */ 65 #define USER_REGION_ID (0UL) 66 67 /* 68 * Defines the address of the vmemap area, in its own region on 69 * hash table CPUs. 70 */ 71 #define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT) 72 #define vmemmap ((struct page *)VMEMMAP_BASE) 73 74 75 #ifdef CONFIG_PPC_MM_SLICES 76 #define HAVE_ARCH_UNMAPPED_AREA 77 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 78 #endif /* CONFIG_PPC_MM_SLICES */ 79 80 /* 81 * THP pages can't be special. So use the _PAGE_SPECIAL 82 */ 83 #define _PAGE_SPLITTING _PAGE_SPECIAL 84 85 /* 86 * We need to differentiate between explicit huge page and THP huge 87 * page, since THP huge page also need to track real subpage details 88 */ 89 #define _PAGE_THP_HUGE _PAGE_4K_PFN 90 91 /* 92 * set of bits not changed in pmd_modify. 93 */ 94 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | \ 95 _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \ 96 _PAGE_THP_HUGE) 97 #define _PTE_NONE_MASK _PAGE_HPTEFLAGS 98 /* 99 * The mask convered by the RPN must be a ULL on 32-bit platforms with 100 * 64-bit PTEs 101 */ 102 #define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1)) 103 /* 104 * _PAGE_CHG_MASK masks of bits that are to be preserved across 105 * pgprot changes 106 */ 107 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 108 _PAGE_ACCESSED | _PAGE_SPECIAL) 109 /* 110 * Mask of bits returned by pte_pgprot() 111 */ 112 #define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \ 113 _PAGE_WRITETHRU | _PAGE_4K_PFN | \ 114 _PAGE_USER | _PAGE_ACCESSED | \ 115 _PAGE_RW | _PAGE_DIRTY | _PAGE_EXEC) 116 /* 117 * We define 2 sets of base prot bits, one for basic pages (ie, 118 * cacheable kernel and user pages) and one for non cacheable 119 * pages. We always set _PAGE_COHERENT when SMP is enabled or 120 * the processor might need it for DMA coherency. 121 */ 122 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 123 #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 124 125 /* Permission masks used to generate the __P and __S table, 126 * 127 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 128 * 129 * Write permissions imply read permissions for now (we could make write-only 130 * pages on BookE but we don't bother for now). Execute permission control is 131 * possible on platforms that define _PAGE_EXEC 132 * 133 * Note due to the way vm flags are laid out, the bits are XWR 134 */ 135 #define PAGE_NONE __pgprot(_PAGE_BASE) 136 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) 137 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | \ 138 _PAGE_EXEC) 139 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER ) 140 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 141 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER ) 142 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) 143 144 #define __P000 PAGE_NONE 145 #define __P001 PAGE_READONLY 146 #define __P010 PAGE_COPY 147 #define __P011 PAGE_COPY 148 #define __P100 PAGE_READONLY_X 149 #define __P101 PAGE_READONLY_X 150 #define __P110 PAGE_COPY_X 151 #define __P111 PAGE_COPY_X 152 153 #define __S000 PAGE_NONE 154 #define __S001 PAGE_READONLY 155 #define __S010 PAGE_SHARED 156 #define __S011 PAGE_SHARED 157 #define __S100 PAGE_READONLY_X 158 #define __S101 PAGE_READONLY_X 159 #define __S110 PAGE_SHARED_X 160 #define __S111 PAGE_SHARED_X 161 162 /* Permission masks used for kernel mappings */ 163 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 164 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 165 _PAGE_NO_CACHE) 166 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 167 _PAGE_NO_CACHE | _PAGE_GUARDED) 168 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 169 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 170 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 171 172 /* Protection used for kernel text. We want the debuggers to be able to 173 * set breakpoints anywhere, so don't write protect the kernel text 174 * on platforms where such control is possible. 175 */ 176 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\ 177 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 178 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 179 #else 180 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 181 #endif 182 183 /* Make modules code happy. We don't set RO yet */ 184 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 185 186 /* 187 * Don't just check for any non zero bits in __PAGE_USER, since for book3e 188 * and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in 189 * _PAGE_USER. Need to explicitly match _PAGE_BAP_UR bit in that case too. 190 */ 191 #define pte_user(val) ((val & _PAGE_USER) == _PAGE_USER) 192 193 /* Advertise special mapping type for AGP */ 194 #define PAGE_AGP (PAGE_KERNEL_NC) 195 #define HAVE_PAGE_AGP 196 197 /* Advertise support for _PAGE_SPECIAL */ 198 #define __HAVE_ARCH_PTE_SPECIAL 199 200 #ifndef __ASSEMBLY__ 201 202 /* 203 * This is the default implementation of various PTE accessors, it's 204 * used in all cases except Book3S with 64K pages where we have a 205 * concept of sub-pages 206 */ 207 #ifndef __real_pte 208 209 #ifdef CONFIG_STRICT_MM_TYPECHECKS 210 #define __real_pte(e,p) ((real_pte_t){(e)}) 211 #define __rpte_to_pte(r) ((r).pte) 212 #else 213 #define __real_pte(e,p) (e) 214 #define __rpte_to_pte(r) (__pte(r)) 215 #endif 216 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12) 217 218 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 219 do { \ 220 index = 0; \ 221 shift = mmu_psize_defs[psize].shift; \ 222 223 #define pte_iterate_hashed_end() } while(0) 224 225 /* 226 * We expect this to be called only for user addresses or kernel virtual 227 * addresses other than the linear mapping. 228 */ 229 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 230 231 #endif /* __real_pte */ 232 233 234 /* pte_clear moved to later in this file */ 235 236 #define PMD_BAD_BITS (PTE_TABLE_SIZE-1) 237 #define PUD_BAD_BITS (PMD_TABLE_SIZE-1) 238 239 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 240 { 241 *pmdp = __pmd(val); 242 } 243 244 static inline void pmd_clear(pmd_t *pmdp) 245 { 246 *pmdp = __pmd(0); 247 } 248 249 250 #define pmd_none(pmd) (!pmd_val(pmd)) 251 #define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \ 252 || (pmd_val(pmd) & PMD_BAD_BITS)) 253 #define pmd_present(pmd) (!pmd_none(pmd)) 254 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS) 255 extern struct page *pmd_page(pmd_t pmd); 256 257 static inline void pud_set(pud_t *pudp, unsigned long val) 258 { 259 *pudp = __pud(val); 260 } 261 262 static inline void pud_clear(pud_t *pudp) 263 { 264 *pudp = __pud(0); 265 } 266 267 #define pud_none(pud) (!pud_val(pud)) 268 #define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \ 269 || (pud_val(pud) & PUD_BAD_BITS)) 270 #define pud_present(pud) (pud_val(pud) != 0) 271 #define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS) 272 273 extern struct page *pud_page(pud_t pud); 274 275 static inline pte_t pud_pte(pud_t pud) 276 { 277 return __pte(pud_val(pud)); 278 } 279 280 static inline pud_t pte_pud(pte_t pte) 281 { 282 return __pud(pte_val(pte)); 283 } 284 #define pud_write(pud) pte_write(pud_pte(pud)) 285 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 286 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 287 { 288 *pgdp = __pgd(val); 289 } 290 291 /* 292 * Find an entry in a page-table-directory. We combine the address region 293 * (the high order N bits) and the pgd portion of the address. 294 */ 295 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 296 297 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 298 299 #define pmd_offset(pudp,addr) \ 300 (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) 301 302 #define pte_offset_kernel(dir,addr) \ 303 (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 304 305 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 306 #define pte_unmap(pte) do { } while(0) 307 308 /* to find an entry in a kernel page-table-directory */ 309 /* This now only contains the vmalloc pages */ 310 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 311 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr, 312 pte_t *ptep, unsigned long pte, int huge); 313 314 /* Atomic PTE updates */ 315 static inline unsigned long pte_update(struct mm_struct *mm, 316 unsigned long addr, 317 pte_t *ptep, unsigned long clr, 318 unsigned long set, 319 int huge) 320 { 321 unsigned long old, tmp; 322 323 __asm__ __volatile__( 324 "1: ldarx %0,0,%3 # pte_update\n\ 325 andi. %1,%0,%6\n\ 326 bne- 1b \n\ 327 andc %1,%0,%4 \n\ 328 or %1,%1,%7\n\ 329 stdcx. %1,0,%3 \n\ 330 bne- 1b" 331 : "=&r" (old), "=&r" (tmp), "=m" (*ptep) 332 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set) 333 : "cc" ); 334 /* huge pages use the old page table lock */ 335 if (!huge) 336 assert_pte_locked(mm, addr); 337 338 if (old & _PAGE_HASHPTE) 339 hpte_need_flush(mm, addr, ptep, old, huge); 340 341 return old; 342 } 343 344 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 345 unsigned long addr, pte_t *ptep) 346 { 347 unsigned long old; 348 349 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) 350 return 0; 351 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 352 return (old & _PAGE_ACCESSED) != 0; 353 } 354 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 355 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 356 ({ \ 357 int __r; \ 358 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 359 __r; \ 360 }) 361 362 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 363 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 364 pte_t *ptep) 365 { 366 367 if ((pte_val(*ptep) & _PAGE_RW) == 0) 368 return; 369 370 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0); 371 } 372 373 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 374 unsigned long addr, pte_t *ptep) 375 { 376 if ((pte_val(*ptep) & _PAGE_RW) == 0) 377 return; 378 379 pte_update(mm, addr, ptep, _PAGE_RW, 0, 1); 380 } 381 382 /* 383 * We currently remove entries from the hashtable regardless of whether 384 * the entry was young or dirty. The generic routines only flush if the 385 * entry was young or dirty which is not good enough. 386 * 387 * We should be more intelligent about this but for the moment we override 388 * these functions and force a tlb flush unconditionally 389 */ 390 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 391 #define ptep_clear_flush_young(__vma, __address, __ptep) \ 392 ({ \ 393 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \ 394 __ptep); \ 395 __young; \ 396 }) 397 398 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 399 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 400 unsigned long addr, pte_t *ptep) 401 { 402 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 403 return __pte(old); 404 } 405 406 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 407 pte_t * ptep) 408 { 409 pte_update(mm, addr, ptep, ~0UL, 0, 0); 410 } 411 412 413 /* Set the dirty and/or accessed bits atomically in a linux PTE, this 414 * function doesn't need to flush the hash entry 415 */ 416 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) 417 { 418 unsigned long bits = pte_val(entry) & 419 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 420 421 unsigned long old, tmp; 422 423 __asm__ __volatile__( 424 "1: ldarx %0,0,%4\n\ 425 andi. %1,%0,%6\n\ 426 bne- 1b \n\ 427 or %0,%3,%0\n\ 428 stdcx. %0,0,%4\n\ 429 bne- 1b" 430 :"=&r" (old), "=&r" (tmp), "=m" (*ptep) 431 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY) 432 :"cc"); 433 } 434 435 #define __HAVE_ARCH_PTE_SAME 436 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0) 437 438 #define pte_ERROR(e) \ 439 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 440 #define pmd_ERROR(e) \ 441 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 442 #define pgd_ERROR(e) \ 443 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 444 445 /* Encode and de-code a swap entry */ 446 #define MAX_SWAPFILES_CHECK() do { \ 447 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 448 /* \ 449 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 450 * We filter HPTEFLAGS on set_pte. \ 451 */ \ 452 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 453 } while (0) 454 /* 455 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 456 */ 457 #define SWP_TYPE_BITS 5 458 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 459 & ((1UL << SWP_TYPE_BITS) - 1)) 460 #define __swp_offset(x) ((x).val >> PTE_RPN_SHIFT) 461 #define __swp_entry(type, offset) ((swp_entry_t) { \ 462 ((type) << _PAGE_BIT_SWAP_TYPE) \ 463 | ((offset) << PTE_RPN_SHIFT) }) 464 465 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) }) 466 #define __swp_entry_to_pte(x) __pte((x).val) 467 468 void pgtable_cache_add(unsigned shift, void (*ctor)(void *)); 469 void pgtable_cache_init(void); 470 471 /* 472 * The linux hugepage PMD now include the pmd entries followed by the address 473 * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits. 474 * [ 1 bit secondary | 3 bit hidx | 1 bit valid | 000]. We use one byte per 475 * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and 476 * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t. 477 * 478 * The last three bits are intentionally left to zero. This memory location 479 * are also used as normal page PTE pointers. So if we have any pointers 480 * left around while we collapse a hugepage, we need to make sure 481 * _PAGE_PRESENT bit of that is zero when we look at them 482 */ 483 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index) 484 { 485 return (hpte_slot_array[index] >> 3) & 0x1; 486 } 487 488 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array, 489 int index) 490 { 491 return hpte_slot_array[index] >> 4; 492 } 493 494 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array, 495 unsigned int index, unsigned int hidx) 496 { 497 hpte_slot_array[index] = hidx << 4 | 0x1 << 3; 498 } 499 500 struct page *realmode_pfn_to_page(unsigned long pfn); 501 502 static inline char *get_hpte_slot_array(pmd_t *pmdp) 503 { 504 /* 505 * The hpte hindex is stored in the pgtable whose address is in the 506 * second half of the PMD 507 * 508 * Order this load with the test for pmd_trans_huge in the caller 509 */ 510 smp_rmb(); 511 return *(char **)(pmdp + PTRS_PER_PMD); 512 513 514 } 515 516 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 517 extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr, 518 pmd_t *pmdp, unsigned long old_pmd); 519 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 520 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 521 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 522 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 523 pmd_t *pmdp, pmd_t pmd); 524 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 525 pmd_t *pmd); 526 /* 527 * 528 * For core kernel code by design pmd_trans_huge is never run on any hugetlbfs 529 * page. The hugetlbfs page table walking and mangling paths are totally 530 * separated form the core VM paths and they're differentiated by 531 * VM_HUGETLB being set on vm_flags well before any pmd_trans_huge could run. 532 * 533 * pmd_trans_huge() is defined as false at build time if 534 * CONFIG_TRANSPARENT_HUGEPAGE=n to optimize away code blocks at build 535 * time in such case. 536 * 537 * For ppc64 we need to differntiate from explicit hugepages from THP, because 538 * for THP we also track the subpage details at the pmd level. We don't do 539 * that for explicit huge pages. 540 * 541 */ 542 static inline int pmd_trans_huge(pmd_t pmd) 543 { 544 /* 545 * leaf pte for huge page, bottom two bits != 00 546 */ 547 return (pmd_val(pmd) & 0x3) && (pmd_val(pmd) & _PAGE_THP_HUGE); 548 } 549 550 static inline int pmd_trans_splitting(pmd_t pmd) 551 { 552 if (pmd_trans_huge(pmd)) 553 return pmd_val(pmd) & _PAGE_SPLITTING; 554 return 0; 555 } 556 557 extern int has_transparent_hugepage(void); 558 #else 559 static inline void hpte_do_hugepage_flush(struct mm_struct *mm, 560 unsigned long addr, pmd_t *pmdp, 561 unsigned long old_pmd) 562 { 563 564 WARN(1, "%s called with THP disabled\n", __func__); 565 } 566 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 567 568 static inline int pmd_large(pmd_t pmd) 569 { 570 /* 571 * leaf pte for huge page, bottom two bits != 00 572 */ 573 return ((pmd_val(pmd) & 0x3) != 0x0); 574 } 575 576 static inline pte_t pmd_pte(pmd_t pmd) 577 { 578 return __pte(pmd_val(pmd)); 579 } 580 581 static inline pmd_t pte_pmd(pte_t pte) 582 { 583 return __pmd(pte_val(pte)); 584 } 585 586 static inline pte_t *pmdp_ptep(pmd_t *pmd) 587 { 588 return (pte_t *)pmd; 589 } 590 591 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 592 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 593 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 594 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 595 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 596 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 597 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 598 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 599 600 #define __HAVE_ARCH_PMD_WRITE 601 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 602 603 static inline pmd_t pmd_mkhuge(pmd_t pmd) 604 { 605 /* Do nothing, mk_pmd() does this part. */ 606 return pmd; 607 } 608 609 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 610 { 611 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 612 } 613 614 static inline pmd_t pmd_mksplitting(pmd_t pmd) 615 { 616 return __pmd(pmd_val(pmd) | _PAGE_SPLITTING); 617 } 618 619 #define __HAVE_ARCH_PMD_SAME 620 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 621 { 622 return (((pmd_val(pmd_a) ^ pmd_val(pmd_b)) & ~_PAGE_HPTEFLAGS) == 0); 623 } 624 625 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 626 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 627 unsigned long address, pmd_t *pmdp, 628 pmd_t entry, int dirty); 629 630 extern unsigned long pmd_hugepage_update(struct mm_struct *mm, 631 unsigned long addr, 632 pmd_t *pmdp, 633 unsigned long clr, 634 unsigned long set); 635 636 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 637 unsigned long addr, pmd_t *pmdp) 638 { 639 unsigned long old; 640 641 if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) 642 return 0; 643 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 644 return ((old & _PAGE_ACCESSED) != 0); 645 } 646 647 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 648 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 649 unsigned long address, pmd_t *pmdp); 650 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 651 extern int pmdp_clear_flush_young(struct vm_area_struct *vma, 652 unsigned long address, pmd_t *pmdp); 653 654 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 655 extern pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 656 unsigned long addr, pmd_t *pmdp); 657 658 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 659 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 660 pmd_t *pmdp) 661 { 662 663 if ((pmd_val(*pmdp) & _PAGE_RW) == 0) 664 return; 665 666 pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW, 0); 667 } 668 669 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH 670 extern void pmdp_splitting_flush(struct vm_area_struct *vma, 671 unsigned long address, pmd_t *pmdp); 672 673 extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 674 unsigned long address, pmd_t *pmdp); 675 #define pmdp_collapse_flush pmdp_collapse_flush 676 677 #define __HAVE_ARCH_PGTABLE_DEPOSIT 678 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, 679 pgtable_t pgtable); 680 #define __HAVE_ARCH_PGTABLE_WITHDRAW 681 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); 682 683 #define __HAVE_ARCH_PMDP_INVALIDATE 684 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 685 pmd_t *pmdp); 686 687 #define pmd_move_must_withdraw pmd_move_must_withdraw 688 struct spinlock; 689 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 690 struct spinlock *old_pmd_ptl) 691 { 692 /* 693 * Archs like ppc64 use pgtable to store per pmd 694 * specific information. So when we switch the pmd, 695 * we should also withdraw and deposit the pgtable 696 */ 697 return true; 698 } 699 #endif /* __ASSEMBLY__ */ 700 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 701