1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/5level-fixup.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x1000000000000000UL 36 #define _RPAGE_RSV2 0x0800000000000000UL 37 #define _RPAGE_RSV3 0x0400000000000000UL 38 #define _RPAGE_RSV4 0x0200000000000000UL 39 #define _RPAGE_RSV5 0x00040UL 40 41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 43 /* 44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 46 * differentiate between two use a SW field when invalidating. 47 * 48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 49 * 50 * This is used only when _PAGE_PRESENT is cleared. 51 */ 52 #define _PAGE_INVALID _RPAGE_SW0 53 54 /* 55 * Top and bottom bits of RPN which can be used by hash 56 * translation mode, because we expect them to be zero 57 * otherwise. 58 */ 59 #define _RPAGE_RPN0 0x01000 60 #define _RPAGE_RPN1 0x02000 61 #define _RPAGE_RPN44 0x0100000000000000UL 62 #define _RPAGE_RPN43 0x0080000000000000UL 63 #define _RPAGE_RPN42 0x0040000000000000UL 64 #define _RPAGE_RPN41 0x0020000000000000UL 65 66 /* Max physical address bit as per radix table */ 67 #define _RPAGE_PA_MAX 57 68 69 /* 70 * Max physical address bit we will use for now. 71 * 72 * This is mostly a hardware limitation and for now Power9 has 73 * a 51 bit limit. 74 * 75 * This is different from the number of physical bit required to address 76 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 77 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 78 * number of sections we can support (SECTIONS_SHIFT). 79 * 80 * This is different from Radix page table limitation above and 81 * should always be less than that. The limit is done such that 82 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 83 * for hash linux page table specific bits. 84 * 85 * In order to be compatible with future hardware generations we keep 86 * some offsets and limit this for now to 53 87 */ 88 #define _PAGE_PA_MAX 53 89 90 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 91 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 92 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 93 #define __HAVE_ARCH_PTE_DEVMAP 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 120 _PAGE_RW | _PAGE_EXEC) 121 /* 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 123 * pgprot changes 124 */ 125 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 126 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 127 _PAGE_SOFT_DIRTY) 128 129 #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ 130 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) 131 /* 132 * We define 2 sets of base prot bits, one for basic pages (ie, 133 * cacheable kernel and user pages) and one for non cacheable 134 * pages. We always set _PAGE_COHERENT when SMP is enabled or 135 * the processor might need it for DMA coherency. 136 */ 137 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 138 #define _PAGE_BASE (_PAGE_BASE_NC) 139 140 /* Permission masks used to generate the __P and __S table, 141 * 142 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 143 * 144 * Write permissions imply read permissions for now (we could make write-only 145 * pages on BookE but we don't bother for now). Execute permission control is 146 * possible on platforms that define _PAGE_EXEC 147 */ 148 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 149 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 150 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 151 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 154 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 155 156 /* Permission masks used for kernel mappings */ 157 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 158 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 _PAGE_TOLERANT) 160 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 161 _PAGE_NON_IDEMPOTENT) 162 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 163 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 164 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 165 166 /* 167 * Protection used for kernel text. We want the debuggers to be able to 168 * set breakpoints anywhere, so don't write protect the kernel text 169 * on platforms where such control is possible. 170 */ 171 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 172 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 173 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 174 #else 175 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 176 #endif 177 178 /* Make modules code happy. We don't set RO yet */ 179 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 180 #define PAGE_AGP (PAGE_KERNEL_NC) 181 182 #ifndef __ASSEMBLY__ 183 /* 184 * page table defines 185 */ 186 extern unsigned long __pte_index_size; 187 extern unsigned long __pmd_index_size; 188 extern unsigned long __pud_index_size; 189 extern unsigned long __pgd_index_size; 190 extern unsigned long __pud_cache_index; 191 #define PTE_INDEX_SIZE __pte_index_size 192 #define PMD_INDEX_SIZE __pmd_index_size 193 #define PUD_INDEX_SIZE __pud_index_size 194 #define PGD_INDEX_SIZE __pgd_index_size 195 /* pmd table use page table fragments */ 196 #define PMD_CACHE_INDEX 0 197 #define PUD_CACHE_INDEX __pud_cache_index 198 /* 199 * Because of use of pte fragments and THP, size of page table 200 * are not always derived out of index size above. 201 */ 202 extern unsigned long __pte_table_size; 203 extern unsigned long __pmd_table_size; 204 extern unsigned long __pud_table_size; 205 extern unsigned long __pgd_table_size; 206 #define PTE_TABLE_SIZE __pte_table_size 207 #define PMD_TABLE_SIZE __pmd_table_size 208 #define PUD_TABLE_SIZE __pud_table_size 209 #define PGD_TABLE_SIZE __pgd_table_size 210 211 extern unsigned long __pmd_val_bits; 212 extern unsigned long __pud_val_bits; 213 extern unsigned long __pgd_val_bits; 214 #define PMD_VAL_BITS __pmd_val_bits 215 #define PUD_VAL_BITS __pud_val_bits 216 #define PGD_VAL_BITS __pgd_val_bits 217 218 extern unsigned long __pte_frag_nr; 219 #define PTE_FRAG_NR __pte_frag_nr 220 extern unsigned long __pte_frag_size_shift; 221 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 222 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 223 224 extern unsigned long __pmd_frag_nr; 225 #define PMD_FRAG_NR __pmd_frag_nr 226 extern unsigned long __pmd_frag_size_shift; 227 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 228 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 229 230 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 231 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 232 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 233 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 234 235 /* PMD_SHIFT determines what a second-level page table entry can map */ 236 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 237 #define PMD_SIZE (1UL << PMD_SHIFT) 238 #define PMD_MASK (~(PMD_SIZE-1)) 239 240 /* PUD_SHIFT determines what a third-level page table entry can map */ 241 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 242 #define PUD_SIZE (1UL << PUD_SHIFT) 243 #define PUD_MASK (~(PUD_SIZE-1)) 244 245 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 246 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 247 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 248 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 249 250 /* Bits to mask out from a PMD to get to the PTE page */ 251 #define PMD_MASKED_BITS 0xc0000000000000ffUL 252 /* Bits to mask out from a PUD to get to the PMD page */ 253 #define PUD_MASKED_BITS 0xc0000000000000ffUL 254 /* Bits to mask out from a PGD to get to the PUD page */ 255 #define PGD_MASKED_BITS 0xc0000000000000ffUL 256 257 /* 258 * Used as an indicator for rcu callback functions 259 */ 260 enum pgtable_index { 261 PTE_INDEX = 0, 262 PMD_INDEX, 263 PUD_INDEX, 264 PGD_INDEX, 265 /* 266 * Below are used with 4k page size and hugetlb 267 */ 268 HTLB_16M_INDEX, 269 HTLB_16G_INDEX, 270 }; 271 272 extern unsigned long __vmalloc_start; 273 extern unsigned long __vmalloc_end; 274 #define VMALLOC_START __vmalloc_start 275 #define VMALLOC_END __vmalloc_end 276 277 extern unsigned long __kernel_virt_start; 278 extern unsigned long __kernel_virt_size; 279 extern unsigned long __kernel_io_start; 280 #define KERN_VIRT_START __kernel_virt_start 281 #define KERN_VIRT_SIZE __kernel_virt_size 282 #define KERN_IO_START __kernel_io_start 283 extern struct page *vmemmap; 284 extern unsigned long ioremap_bot; 285 extern unsigned long pci_io_base; 286 #endif /* __ASSEMBLY__ */ 287 288 #include <asm/book3s/64/hash.h> 289 #include <asm/book3s/64/radix.h> 290 291 #ifdef CONFIG_PPC_64K_PAGES 292 #include <asm/book3s/64/pgtable-64k.h> 293 #else 294 #include <asm/book3s/64/pgtable-4k.h> 295 #endif 296 297 #include <asm/barrier.h> 298 /* 299 * The second half of the kernel virtual space is used for IO mappings, 300 * it's itself carved into the PIO region (ISA and PHB IO space) and 301 * the ioremap space 302 * 303 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 304 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 305 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 306 */ 307 #define FULL_IO_SIZE 0x80000000ul 308 #define ISA_IO_BASE (KERN_IO_START) 309 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 310 #define PHB_IO_BASE (ISA_IO_END) 311 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 312 #define IOREMAP_BASE (PHB_IO_END) 313 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 314 315 /* Advertise special mapping type for AGP */ 316 #define HAVE_PAGE_AGP 317 318 #ifndef __ASSEMBLY__ 319 320 /* 321 * This is the default implementation of various PTE accessors, it's 322 * used in all cases except Book3S with 64K pages where we have a 323 * concept of sub-pages 324 */ 325 #ifndef __real_pte 326 327 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 328 #define __rpte_to_pte(r) ((r).pte) 329 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 330 331 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 332 do { \ 333 index = 0; \ 334 shift = mmu_psize_defs[psize].shift; \ 335 336 #define pte_iterate_hashed_end() } while(0) 337 338 /* 339 * We expect this to be called only for user addresses or kernel virtual 340 * addresses other than the linear mapping. 341 */ 342 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 343 344 #endif /* __real_pte */ 345 346 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 347 pte_t *ptep, unsigned long clr, 348 unsigned long set, int huge) 349 { 350 if (radix_enabled()) 351 return radix__pte_update(mm, addr, ptep, clr, set, huge); 352 return hash__pte_update(mm, addr, ptep, clr, set, huge); 353 } 354 /* 355 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 356 * We currently remove entries from the hashtable regardless of whether 357 * the entry was young or dirty. 358 * 359 * We should be more intelligent about this but for the moment we override 360 * these functions and force a tlb flush unconditionally 361 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 362 * function for both hash and radix. 363 */ 364 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 365 unsigned long addr, pte_t *ptep) 366 { 367 unsigned long old; 368 369 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 370 return 0; 371 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 372 return (old & _PAGE_ACCESSED) != 0; 373 } 374 375 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 376 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 377 ({ \ 378 int __r; \ 379 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 380 __r; \ 381 }) 382 383 static inline int __pte_write(pte_t pte) 384 { 385 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 386 } 387 388 #ifdef CONFIG_NUMA_BALANCING 389 #define pte_savedwrite pte_savedwrite 390 static inline bool pte_savedwrite(pte_t pte) 391 { 392 /* 393 * Saved write ptes are prot none ptes that doesn't have 394 * privileged bit sit. We mark prot none as one which has 395 * present and pviliged bit set and RWX cleared. To mark 396 * protnone which used to have _PAGE_WRITE set we clear 397 * the privileged bit. 398 */ 399 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 400 } 401 #else 402 #define pte_savedwrite pte_savedwrite 403 static inline bool pte_savedwrite(pte_t pte) 404 { 405 return false; 406 } 407 #endif 408 409 static inline int pte_write(pte_t pte) 410 { 411 return __pte_write(pte) || pte_savedwrite(pte); 412 } 413 414 static inline int pte_read(pte_t pte) 415 { 416 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 417 } 418 419 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 420 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 421 pte_t *ptep) 422 { 423 if (__pte_write(*ptep)) 424 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 425 else if (unlikely(pte_savedwrite(*ptep))) 426 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 427 } 428 429 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 430 unsigned long addr, pte_t *ptep) 431 { 432 /* 433 * We should not find protnone for hugetlb, but this complete the 434 * interface. 435 */ 436 if (__pte_write(*ptep)) 437 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 438 else if (unlikely(pte_savedwrite(*ptep))) 439 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 440 } 441 442 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 443 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 444 unsigned long addr, pte_t *ptep) 445 { 446 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 447 return __pte(old); 448 } 449 450 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 451 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 452 unsigned long addr, 453 pte_t *ptep, int full) 454 { 455 if (full && radix_enabled()) { 456 /* 457 * We know that this is a full mm pte clear and 458 * hence can be sure there is no parallel set_pte. 459 */ 460 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 461 } 462 return ptep_get_and_clear(mm, addr, ptep); 463 } 464 465 466 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 467 pte_t * ptep) 468 { 469 pte_update(mm, addr, ptep, ~0UL, 0, 0); 470 } 471 472 static inline int pte_dirty(pte_t pte) 473 { 474 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 475 } 476 477 static inline int pte_young(pte_t pte) 478 { 479 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 480 } 481 482 static inline int pte_special(pte_t pte) 483 { 484 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 485 } 486 487 static inline bool pte_exec(pte_t pte) 488 { 489 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 490 } 491 492 493 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 494 static inline bool pte_soft_dirty(pte_t pte) 495 { 496 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 497 } 498 499 static inline pte_t pte_mksoft_dirty(pte_t pte) 500 { 501 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 502 } 503 504 static inline pte_t pte_clear_soft_dirty(pte_t pte) 505 { 506 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 507 } 508 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 509 510 #ifdef CONFIG_NUMA_BALANCING 511 static inline int pte_protnone(pte_t pte) 512 { 513 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 514 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 515 } 516 517 #define pte_mk_savedwrite pte_mk_savedwrite 518 static inline pte_t pte_mk_savedwrite(pte_t pte) 519 { 520 /* 521 * Used by Autonuma subsystem to preserve the write bit 522 * while marking the pte PROT_NONE. Only allow this 523 * on PROT_NONE pte 524 */ 525 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 526 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 527 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 528 } 529 530 #define pte_clear_savedwrite pte_clear_savedwrite 531 static inline pte_t pte_clear_savedwrite(pte_t pte) 532 { 533 /* 534 * Used by KSM subsystem to make a protnone pte readonly. 535 */ 536 VM_BUG_ON(!pte_protnone(pte)); 537 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 538 } 539 #else 540 #define pte_clear_savedwrite pte_clear_savedwrite 541 static inline pte_t pte_clear_savedwrite(pte_t pte) 542 { 543 VM_WARN_ON(1); 544 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 545 } 546 #endif /* CONFIG_NUMA_BALANCING */ 547 548 static inline int pte_present(pte_t pte) 549 { 550 /* 551 * A pte is considerent present if _PAGE_PRESENT is set. 552 * We also need to consider the pte present which is marked 553 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 554 * if we find _PAGE_PRESENT cleared. 555 */ 556 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)); 557 } 558 559 static inline bool pte_hw_valid(pte_t pte) 560 { 561 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 562 } 563 564 #ifdef CONFIG_PPC_MEM_KEYS 565 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 566 #else 567 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 568 { 569 return true; 570 } 571 #endif /* CONFIG_PPC_MEM_KEYS */ 572 573 static inline bool pte_user(pte_t pte) 574 { 575 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 576 } 577 578 #define pte_access_permitted pte_access_permitted 579 static inline bool pte_access_permitted(pte_t pte, bool write) 580 { 581 /* 582 * _PAGE_READ is needed for any access and will be 583 * cleared for PROT_NONE 584 */ 585 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 586 return false; 587 588 if (write && !pte_write(pte)) 589 return false; 590 591 return arch_pte_access_permitted(pte_val(pte), write, 0); 592 } 593 594 /* 595 * Conversion functions: convert a page and protection to a page entry, 596 * and a page entry and page directory to the page they refer to. 597 * 598 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 599 * long for now. 600 */ 601 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 602 { 603 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 604 pgprot_val(pgprot)); 605 } 606 607 static inline unsigned long pte_pfn(pte_t pte) 608 { 609 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 610 } 611 612 /* Generic modifiers for PTE bits */ 613 static inline pte_t pte_wrprotect(pte_t pte) 614 { 615 if (unlikely(pte_savedwrite(pte))) 616 return pte_clear_savedwrite(pte); 617 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 618 } 619 620 static inline pte_t pte_exprotect(pte_t pte) 621 { 622 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 623 } 624 625 static inline pte_t pte_mkclean(pte_t pte) 626 { 627 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 628 } 629 630 static inline pte_t pte_mkold(pte_t pte) 631 { 632 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 633 } 634 635 static inline pte_t pte_mkexec(pte_t pte) 636 { 637 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 638 } 639 640 static inline pte_t pte_mkpte(pte_t pte) 641 { 642 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 643 } 644 645 static inline pte_t pte_mkwrite(pte_t pte) 646 { 647 /* 648 * write implies read, hence set both 649 */ 650 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 651 } 652 653 static inline pte_t pte_mkdirty(pte_t pte) 654 { 655 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 656 } 657 658 static inline pte_t pte_mkyoung(pte_t pte) 659 { 660 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 661 } 662 663 static inline pte_t pte_mkspecial(pte_t pte) 664 { 665 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 666 } 667 668 static inline pte_t pte_mkhuge(pte_t pte) 669 { 670 return pte; 671 } 672 673 static inline pte_t pte_mkdevmap(pte_t pte) 674 { 675 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 676 } 677 678 static inline pte_t pte_mkprivileged(pte_t pte) 679 { 680 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 681 } 682 683 static inline pte_t pte_mkuser(pte_t pte) 684 { 685 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 686 } 687 688 /* 689 * This is potentially called with a pmd as the argument, in which case it's not 690 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 691 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 692 * use in page directory entries (ie. non-ptes). 693 */ 694 static inline int pte_devmap(pte_t pte) 695 { 696 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 697 698 return (pte_raw(pte) & mask) == mask; 699 } 700 701 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 702 { 703 /* FIXME!! check whether this need to be a conditional */ 704 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 705 cpu_to_be64(pgprot_val(newprot))); 706 } 707 708 /* Encode and de-code a swap entry */ 709 #define MAX_SWAPFILES_CHECK() do { \ 710 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 711 /* \ 712 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 713 * We filter HPTEFLAGS on set_pte. \ 714 */ \ 715 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 716 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 717 } while (0) 718 /* 719 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 720 */ 721 #define SWP_TYPE_BITS 5 722 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 723 & ((1UL << SWP_TYPE_BITS) - 1)) 724 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 725 #define __swp_entry(type, offset) ((swp_entry_t) { \ 726 ((type) << _PAGE_BIT_SWAP_TYPE) \ 727 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 728 /* 729 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 730 * swap type and offset we get from swap and convert that to pte to find a 731 * matching pte in linux page table. 732 * Clear bits not found in swap entries here. 733 */ 734 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 735 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 736 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 737 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 738 739 #ifdef CONFIG_MEM_SOFT_DIRTY 740 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 741 #else 742 #define _PAGE_SWP_SOFT_DIRTY 0UL 743 #endif /* CONFIG_MEM_SOFT_DIRTY */ 744 745 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 746 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 747 { 748 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 749 } 750 751 static inline bool pte_swp_soft_dirty(pte_t pte) 752 { 753 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 754 } 755 756 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 757 { 758 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 759 } 760 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 761 762 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 763 { 764 /* 765 * This check for _PAGE_RWX and _PAGE_PRESENT bits 766 */ 767 if (access & ~ptev) 768 return false; 769 /* 770 * This check for access to privilege space 771 */ 772 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 773 return false; 774 775 return true; 776 } 777 /* 778 * Generic functions with hash/radix callbacks 779 */ 780 781 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 782 pte_t *ptep, pte_t entry, 783 unsigned long address, 784 int psize) 785 { 786 if (radix_enabled()) 787 return radix__ptep_set_access_flags(vma, ptep, entry, 788 address, psize); 789 return hash__ptep_set_access_flags(ptep, entry); 790 } 791 792 #define __HAVE_ARCH_PTE_SAME 793 static inline int pte_same(pte_t pte_a, pte_t pte_b) 794 { 795 if (radix_enabled()) 796 return radix__pte_same(pte_a, pte_b); 797 return hash__pte_same(pte_a, pte_b); 798 } 799 800 static inline int pte_none(pte_t pte) 801 { 802 if (radix_enabled()) 803 return radix__pte_none(pte); 804 return hash__pte_none(pte); 805 } 806 807 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 808 pte_t *ptep, pte_t pte, int percpu) 809 { 810 if (radix_enabled()) 811 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 812 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 813 } 814 815 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 816 817 #define pgprot_noncached pgprot_noncached 818 static inline pgprot_t pgprot_noncached(pgprot_t prot) 819 { 820 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 821 _PAGE_NON_IDEMPOTENT); 822 } 823 824 #define pgprot_noncached_wc pgprot_noncached_wc 825 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 826 { 827 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 828 _PAGE_TOLERANT); 829 } 830 831 #define pgprot_cached pgprot_cached 832 static inline pgprot_t pgprot_cached(pgprot_t prot) 833 { 834 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 835 } 836 837 #define pgprot_writecombine pgprot_writecombine 838 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 839 { 840 return pgprot_noncached_wc(prot); 841 } 842 /* 843 * check a pte mapping have cache inhibited property 844 */ 845 static inline bool pte_ci(pte_t pte) 846 { 847 __be64 pte_v = pte_raw(pte); 848 849 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 850 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 851 return true; 852 return false; 853 } 854 855 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 856 { 857 *pmdp = __pmd(val); 858 } 859 860 static inline void pmd_clear(pmd_t *pmdp) 861 { 862 *pmdp = __pmd(0); 863 } 864 865 static inline int pmd_none(pmd_t pmd) 866 { 867 return !pmd_raw(pmd); 868 } 869 870 static inline int pmd_present(pmd_t pmd) 871 { 872 /* 873 * A pmd is considerent present if _PAGE_PRESENT is set. 874 * We also need to consider the pmd present which is marked 875 * invalid during a split. Hence we look for _PAGE_INVALID 876 * if we find _PAGE_PRESENT cleared. 877 */ 878 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 879 return true; 880 881 return false; 882 } 883 884 static inline int pmd_bad(pmd_t pmd) 885 { 886 if (radix_enabled()) 887 return radix__pmd_bad(pmd); 888 return hash__pmd_bad(pmd); 889 } 890 891 static inline void pud_set(pud_t *pudp, unsigned long val) 892 { 893 *pudp = __pud(val); 894 } 895 896 static inline void pud_clear(pud_t *pudp) 897 { 898 *pudp = __pud(0); 899 } 900 901 static inline int pud_none(pud_t pud) 902 { 903 return !pud_raw(pud); 904 } 905 906 static inline int pud_present(pud_t pud) 907 { 908 return (pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 909 } 910 911 extern struct page *pud_page(pud_t pud); 912 extern struct page *pmd_page(pmd_t pmd); 913 static inline pte_t pud_pte(pud_t pud) 914 { 915 return __pte_raw(pud_raw(pud)); 916 } 917 918 static inline pud_t pte_pud(pte_t pte) 919 { 920 return __pud_raw(pte_raw(pte)); 921 } 922 #define pud_write(pud) pte_write(pud_pte(pud)) 923 924 static inline int pud_bad(pud_t pud) 925 { 926 if (radix_enabled()) 927 return radix__pud_bad(pud); 928 return hash__pud_bad(pud); 929 } 930 931 #define pud_access_permitted pud_access_permitted 932 static inline bool pud_access_permitted(pud_t pud, bool write) 933 { 934 return pte_access_permitted(pud_pte(pud), write); 935 } 936 937 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 938 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 939 { 940 *pgdp = __pgd(val); 941 } 942 943 static inline void pgd_clear(pgd_t *pgdp) 944 { 945 *pgdp = __pgd(0); 946 } 947 948 static inline int pgd_none(pgd_t pgd) 949 { 950 return !pgd_raw(pgd); 951 } 952 953 static inline int pgd_present(pgd_t pgd) 954 { 955 return (pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT)); 956 } 957 958 static inline pte_t pgd_pte(pgd_t pgd) 959 { 960 return __pte_raw(pgd_raw(pgd)); 961 } 962 963 static inline pgd_t pte_pgd(pte_t pte) 964 { 965 return __pgd_raw(pte_raw(pte)); 966 } 967 968 static inline int pgd_bad(pgd_t pgd) 969 { 970 if (radix_enabled()) 971 return radix__pgd_bad(pgd); 972 return hash__pgd_bad(pgd); 973 } 974 975 #define pgd_access_permitted pgd_access_permitted 976 static inline bool pgd_access_permitted(pgd_t pgd, bool write) 977 { 978 return pte_access_permitted(pgd_pte(pgd), write); 979 } 980 981 extern struct page *pgd_page(pgd_t pgd); 982 983 /* Pointers in the page table tree are physical addresses */ 984 #define __pgtable_ptr_val(ptr) __pa(ptr) 985 986 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 987 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 988 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 989 990 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 991 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 992 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 993 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 994 995 /* 996 * Find an entry in a page-table-directory. We combine the address region 997 * (the high order N bits) and the pgd portion of the address. 998 */ 999 1000 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 1001 1002 #define pud_offset(pgdp, addr) \ 1003 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 1004 #define pmd_offset(pudp,addr) \ 1005 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 1006 #define pte_offset_kernel(dir,addr) \ 1007 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 1008 1009 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 1010 #define pte_unmap(pte) do { } while(0) 1011 1012 /* to find an entry in a kernel page-table-directory */ 1013 /* This now only contains the vmalloc pages */ 1014 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 1015 1016 #define pte_ERROR(e) \ 1017 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1018 #define pmd_ERROR(e) \ 1019 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1020 #define pud_ERROR(e) \ 1021 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1022 #define pgd_ERROR(e) \ 1023 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1024 1025 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1026 { 1027 if (radix_enabled()) { 1028 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1029 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1030 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1031 #endif 1032 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1033 } 1034 return hash__map_kernel_page(ea, pa, prot); 1035 } 1036 1037 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1038 unsigned long page_size, 1039 unsigned long phys) 1040 { 1041 if (radix_enabled()) 1042 return radix__vmemmap_create_mapping(start, page_size, phys); 1043 return hash__vmemmap_create_mapping(start, page_size, phys); 1044 } 1045 1046 #ifdef CONFIG_MEMORY_HOTPLUG 1047 static inline void vmemmap_remove_mapping(unsigned long start, 1048 unsigned long page_size) 1049 { 1050 if (radix_enabled()) 1051 return radix__vmemmap_remove_mapping(start, page_size); 1052 return hash__vmemmap_remove_mapping(start, page_size); 1053 } 1054 #endif 1055 struct page *realmode_pfn_to_page(unsigned long pfn); 1056 1057 static inline pte_t pmd_pte(pmd_t pmd) 1058 { 1059 return __pte_raw(pmd_raw(pmd)); 1060 } 1061 1062 static inline pmd_t pte_pmd(pte_t pte) 1063 { 1064 return __pmd_raw(pte_raw(pte)); 1065 } 1066 1067 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1068 { 1069 return (pte_t *)pmd; 1070 } 1071 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1072 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1073 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1074 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1075 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1076 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1077 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1078 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1079 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1080 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1081 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1082 1083 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1084 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1085 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1086 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1087 1088 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1089 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1090 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1091 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1092 #endif 1093 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1094 1095 #ifdef CONFIG_NUMA_BALANCING 1096 static inline int pmd_protnone(pmd_t pmd) 1097 { 1098 return pte_protnone(pmd_pte(pmd)); 1099 } 1100 #endif /* CONFIG_NUMA_BALANCING */ 1101 1102 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1103 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1104 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1105 1106 #define pmd_access_permitted pmd_access_permitted 1107 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1108 { 1109 return pte_access_permitted(pmd_pte(pmd), write); 1110 } 1111 1112 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1113 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1114 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1115 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1116 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1117 pmd_t *pmdp, pmd_t pmd); 1118 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 1119 pmd_t *pmd); 1120 extern int hash__has_transparent_hugepage(void); 1121 static inline int has_transparent_hugepage(void) 1122 { 1123 if (radix_enabled()) 1124 return radix__has_transparent_hugepage(); 1125 return hash__has_transparent_hugepage(); 1126 } 1127 #define has_transparent_hugepage has_transparent_hugepage 1128 1129 static inline unsigned long 1130 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1131 unsigned long clr, unsigned long set) 1132 { 1133 if (radix_enabled()) 1134 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1135 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1136 } 1137 1138 /* 1139 * returns true for pmd migration entries, THP, devmap, hugetlb 1140 * But compile time dependent on THP config 1141 */ 1142 static inline int pmd_large(pmd_t pmd) 1143 { 1144 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1145 } 1146 1147 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 1148 { 1149 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 1150 } 1151 /* 1152 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1153 * the below will work for radix too 1154 */ 1155 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1156 unsigned long addr, pmd_t *pmdp) 1157 { 1158 unsigned long old; 1159 1160 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1161 return 0; 1162 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1163 return ((old & _PAGE_ACCESSED) != 0); 1164 } 1165 1166 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1167 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1168 pmd_t *pmdp) 1169 { 1170 if (__pmd_write((*pmdp))) 1171 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1172 else if (unlikely(pmd_savedwrite(*pmdp))) 1173 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1174 } 1175 1176 /* 1177 * Only returns true for a THP. False for pmd migration entry. 1178 * We also need to return true when we come across a pte that 1179 * in between a thp split. While splitting THP, we mark the pmd 1180 * invalid (pmdp_invalidate()) before we set it with pte page 1181 * address. A pmd_trans_huge() check against a pmd entry during that time 1182 * should return true. 1183 * We should not call this on a hugetlb entry. We should check for HugeTLB 1184 * entry using vma->vm_flags 1185 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1186 */ 1187 static inline int pmd_trans_huge(pmd_t pmd) 1188 { 1189 if (!pmd_present(pmd)) 1190 return false; 1191 1192 if (radix_enabled()) 1193 return radix__pmd_trans_huge(pmd); 1194 return hash__pmd_trans_huge(pmd); 1195 } 1196 1197 #define __HAVE_ARCH_PMD_SAME 1198 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1199 { 1200 if (radix_enabled()) 1201 return radix__pmd_same(pmd_a, pmd_b); 1202 return hash__pmd_same(pmd_a, pmd_b); 1203 } 1204 1205 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1206 { 1207 if (radix_enabled()) 1208 return radix__pmd_mkhuge(pmd); 1209 return hash__pmd_mkhuge(pmd); 1210 } 1211 1212 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1213 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1214 unsigned long address, pmd_t *pmdp, 1215 pmd_t entry, int dirty); 1216 1217 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1218 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1219 unsigned long address, pmd_t *pmdp); 1220 1221 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1222 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1223 unsigned long addr, pmd_t *pmdp) 1224 { 1225 if (radix_enabled()) 1226 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1227 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1228 } 1229 1230 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1231 unsigned long address, pmd_t *pmdp) 1232 { 1233 if (radix_enabled()) 1234 return radix__pmdp_collapse_flush(vma, address, pmdp); 1235 return hash__pmdp_collapse_flush(vma, address, pmdp); 1236 } 1237 #define pmdp_collapse_flush pmdp_collapse_flush 1238 1239 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1240 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1241 pmd_t *pmdp, pgtable_t pgtable) 1242 { 1243 if (radix_enabled()) 1244 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1245 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1246 } 1247 1248 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1249 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1250 pmd_t *pmdp) 1251 { 1252 if (radix_enabled()) 1253 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1254 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1255 } 1256 1257 #define __HAVE_ARCH_PMDP_INVALIDATE 1258 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1259 pmd_t *pmdp); 1260 1261 #define pmd_move_must_withdraw pmd_move_must_withdraw 1262 struct spinlock; 1263 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1264 struct spinlock *old_pmd_ptl, 1265 struct vm_area_struct *vma) 1266 { 1267 if (radix_enabled()) 1268 return false; 1269 /* 1270 * Archs like ppc64 use pgtable to store per pmd 1271 * specific information. So when we switch the pmd, 1272 * we should also withdraw and deposit the pgtable 1273 */ 1274 return true; 1275 } 1276 1277 1278 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1279 static inline bool arch_needs_pgtable_deposit(void) 1280 { 1281 if (radix_enabled()) 1282 return false; 1283 return true; 1284 } 1285 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1286 1287 1288 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1289 { 1290 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); 1291 } 1292 1293 static inline int pmd_devmap(pmd_t pmd) 1294 { 1295 return pte_devmap(pmd_pte(pmd)); 1296 } 1297 1298 static inline int pud_devmap(pud_t pud) 1299 { 1300 return 0; 1301 } 1302 1303 static inline int pgd_devmap(pgd_t pgd) 1304 { 1305 return 0; 1306 } 1307 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1308 1309 static inline const int pud_pfn(pud_t pud) 1310 { 1311 /* 1312 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1313 * check so this should never be used. If it grows another user we 1314 * want to know about it. 1315 */ 1316 BUILD_BUG(); 1317 return 0; 1318 } 1319 1320 #endif /* __ASSEMBLY__ */ 1321 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1322