1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #include <linux/sizes.h> 11 #endif 12 13 /* 14 * Common bits between hash and Radix page table 15 */ 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 21 #define _PAGE_SAO 0x00010 /* Strong access order */ 22 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 23 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 24 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 25 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 26 /* 27 * Software bits 28 */ 29 #define _RPAGE_SW0 0x2000000000000000UL 30 #define _RPAGE_SW1 0x00800 31 #define _RPAGE_SW2 0x00400 32 #define _RPAGE_SW3 0x00200 33 #define _RPAGE_RSV1 0x00040UL 34 35 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 36 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 37 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 38 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 39 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 40 41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 43 /* 44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 46 * differentiate between two use a SW field when invalidating. 47 * 48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 49 * 50 * This is used only when _PAGE_PRESENT is cleared. 51 */ 52 #define _PAGE_INVALID _RPAGE_SW0 53 54 /* 55 * Top and bottom bits of RPN which can be used by hash 56 * translation mode, because we expect them to be zero 57 * otherwise. 58 */ 59 #define _RPAGE_RPN0 0x01000 60 #define _RPAGE_RPN1 0x02000 61 #define _RPAGE_RPN43 0x0080000000000000UL 62 #define _RPAGE_RPN42 0x0040000000000000UL 63 #define _RPAGE_RPN41 0x0020000000000000UL 64 65 /* Max physical address bit as per radix table */ 66 #define _RPAGE_PA_MAX 56 67 68 /* 69 * Max physical address bit we will use for now. 70 * 71 * This is mostly a hardware limitation and for now Power9 has 72 * a 51 bit limit. 73 * 74 * This is different from the number of physical bit required to address 75 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 76 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 77 * number of sections we can support (SECTIONS_SHIFT). 78 * 79 * This is different from Radix page table limitation above and 80 * should always be less than that. The limit is done such that 81 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 82 * for hash linux page table specific bits. 83 * 84 * In order to be compatible with future hardware generations we keep 85 * some offsets and limit this for now to 53 86 */ 87 #define _PAGE_PA_MAX 53 88 89 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 90 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 91 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 92 93 /* 94 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 95 * Instead of fixing all of them, add an alternate define which 96 * maps CI pte mapping. 97 */ 98 #define _PAGE_NO_CACHE _PAGE_TOLERANT 99 /* 100 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 101 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 102 * and every thing below PAGE_SHIFT; 103 */ 104 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 105 #define PTE_RPN_SHIFT PAGE_SHIFT 106 /* 107 * set of bits not changed in pmd_modify. Even though we have hash specific bits 108 * in here, on radix we expect them to be zero. 109 */ 110 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 111 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 112 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 113 /* 114 * user access blocked by key 115 */ 116 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 117 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 118 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 120 /* 121 * _PAGE_CHG_MASK masks of bits that are to be preserved across 122 * pgprot changes 123 */ 124 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 125 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 126 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 127 128 /* 129 * We define 2 sets of base prot bits, one for basic pages (ie, 130 * cacheable kernel and user pages) and one for non cacheable 131 * pages. We always set _PAGE_COHERENT when SMP is enabled or 132 * the processor might need it for DMA coherency. 133 */ 134 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 135 #define _PAGE_BASE (_PAGE_BASE_NC) 136 137 #include <asm/pgtable-masks.h> 138 139 /* Permission masks used for kernel mappings */ 140 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 141 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) 142 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) 143 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 144 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 145 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 146 147 #ifndef __ASSEMBLY__ 148 /* 149 * page table defines 150 */ 151 extern unsigned long __pte_index_size; 152 extern unsigned long __pmd_index_size; 153 extern unsigned long __pud_index_size; 154 extern unsigned long __pgd_index_size; 155 extern unsigned long __pud_cache_index; 156 #define PTE_INDEX_SIZE __pte_index_size 157 #define PMD_INDEX_SIZE __pmd_index_size 158 #define PUD_INDEX_SIZE __pud_index_size 159 #define PGD_INDEX_SIZE __pgd_index_size 160 /* pmd table use page table fragments */ 161 #define PMD_CACHE_INDEX 0 162 #define PUD_CACHE_INDEX __pud_cache_index 163 /* 164 * Because of use of pte fragments and THP, size of page table 165 * are not always derived out of index size above. 166 */ 167 extern unsigned long __pte_table_size; 168 extern unsigned long __pmd_table_size; 169 extern unsigned long __pud_table_size; 170 extern unsigned long __pgd_table_size; 171 #define PTE_TABLE_SIZE __pte_table_size 172 #define PMD_TABLE_SIZE __pmd_table_size 173 #define PUD_TABLE_SIZE __pud_table_size 174 #define PGD_TABLE_SIZE __pgd_table_size 175 176 extern unsigned long __pmd_val_bits; 177 extern unsigned long __pud_val_bits; 178 extern unsigned long __pgd_val_bits; 179 #define PMD_VAL_BITS __pmd_val_bits 180 #define PUD_VAL_BITS __pud_val_bits 181 #define PGD_VAL_BITS __pgd_val_bits 182 183 extern unsigned long __pte_frag_nr; 184 #define PTE_FRAG_NR __pte_frag_nr 185 extern unsigned long __pte_frag_size_shift; 186 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 187 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 188 189 extern unsigned long __pmd_frag_nr; 190 #define PMD_FRAG_NR __pmd_frag_nr 191 extern unsigned long __pmd_frag_size_shift; 192 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 193 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 194 195 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 196 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 197 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 198 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 199 200 #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) 201 #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) 202 #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) 203 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ 204 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) 205 206 /* PMD_SHIFT determines what a second-level page table entry can map */ 207 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 208 #define PMD_SIZE (1UL << PMD_SHIFT) 209 #define PMD_MASK (~(PMD_SIZE-1)) 210 211 /* PUD_SHIFT determines what a third-level page table entry can map */ 212 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 213 #define PUD_SIZE (1UL << PUD_SHIFT) 214 #define PUD_MASK (~(PUD_SIZE-1)) 215 216 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 217 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 218 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 219 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 220 221 /* Bits to mask out from a PMD to get to the PTE page */ 222 #define PMD_MASKED_BITS 0xc0000000000000ffUL 223 /* Bits to mask out from a PUD to get to the PMD page */ 224 #define PUD_MASKED_BITS 0xc0000000000000ffUL 225 /* Bits to mask out from a PGD to get to the PUD page */ 226 #define P4D_MASKED_BITS 0xc0000000000000ffUL 227 228 /* 229 * Used as an indicator for rcu callback functions 230 */ 231 enum pgtable_index { 232 PTE_INDEX = 0, 233 PMD_INDEX, 234 PUD_INDEX, 235 PGD_INDEX, 236 /* 237 * Below are used with 4k page size and hugetlb 238 */ 239 HTLB_16M_INDEX, 240 HTLB_16G_INDEX, 241 }; 242 243 extern unsigned long __vmalloc_start; 244 extern unsigned long __vmalloc_end; 245 #define VMALLOC_START __vmalloc_start 246 #define VMALLOC_END __vmalloc_end 247 248 static inline unsigned int ioremap_max_order(void) 249 { 250 if (radix_enabled()) 251 return PUD_SHIFT; 252 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 253 } 254 #define IOREMAP_MAX_ORDER ioremap_max_order() 255 256 extern unsigned long __kernel_virt_start; 257 extern unsigned long __kernel_io_start; 258 extern unsigned long __kernel_io_end; 259 #define KERN_VIRT_START __kernel_virt_start 260 #define KERN_IO_START __kernel_io_start 261 #define KERN_IO_END __kernel_io_end 262 263 extern struct page *vmemmap; 264 extern unsigned long pci_io_base; 265 #endif /* __ASSEMBLY__ */ 266 267 #include <asm/book3s/64/hash.h> 268 #include <asm/book3s/64/radix.h> 269 270 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 271 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 272 #else 273 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 274 #endif 275 276 277 #ifdef CONFIG_PPC_64K_PAGES 278 #include <asm/book3s/64/pgtable-64k.h> 279 #else 280 #include <asm/book3s/64/pgtable-4k.h> 281 #endif 282 283 #include <asm/barrier.h> 284 /* 285 * IO space itself carved into the PIO region (ISA and PHB IO space) and 286 * the ioremap space 287 * 288 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 289 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 290 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 291 */ 292 #define FULL_IO_SIZE 0x80000000ul 293 #define ISA_IO_BASE (KERN_IO_START) 294 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 295 #define PHB_IO_BASE (ISA_IO_END) 296 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 297 #define IOREMAP_BASE (PHB_IO_END) 298 #define IOREMAP_START (ioremap_bot) 299 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 300 #define FIXADDR_SIZE SZ_32M 301 #define FIXADDR_TOP (IOREMAP_END + FIXADDR_SIZE) 302 303 #ifndef __ASSEMBLY__ 304 305 /* 306 * This is the default implementation of various PTE accessors, it's 307 * used in all cases except Book3S with 64K pages where we have a 308 * concept of sub-pages 309 */ 310 #ifndef __real_pte 311 312 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 313 #define __rpte_to_pte(r) ((r).pte) 314 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 315 316 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 317 do { \ 318 index = 0; \ 319 shift = mmu_psize_defs[psize].shift; \ 320 321 #define pte_iterate_hashed_end() } while(0) 322 323 /* 324 * We expect this to be called only for user addresses or kernel virtual 325 * addresses other than the linear mapping. 326 */ 327 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 328 329 #endif /* __real_pte */ 330 331 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 332 pte_t *ptep, unsigned long clr, 333 unsigned long set, int huge) 334 { 335 if (radix_enabled()) 336 return radix__pte_update(mm, addr, ptep, clr, set, huge); 337 return hash__pte_update(mm, addr, ptep, clr, set, huge); 338 } 339 /* 340 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 341 * We currently remove entries from the hashtable regardless of whether 342 * the entry was young or dirty. 343 * 344 * We should be more intelligent about this but for the moment we override 345 * these functions and force a tlb flush unconditionally 346 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 347 * function for both hash and radix. 348 */ 349 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 350 unsigned long addr, pte_t *ptep) 351 { 352 unsigned long old; 353 354 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 355 return 0; 356 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 357 return (old & _PAGE_ACCESSED) != 0; 358 } 359 360 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 361 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 362 ({ \ 363 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 364 }) 365 366 /* 367 * On Book3S CPUs, clearing the accessed bit without a TLB flush 368 * doesn't cause data corruption. [ It could cause incorrect 369 * page aging and the (mistaken) reclaim of hot pages, but the 370 * chance of that should be relatively low. ] 371 * 372 * So as a performance optimization don't flush the TLB when 373 * clearing the accessed bit, it will eventually be flushed by 374 * a context switch or a VM operation anyway. [ In the rare 375 * event of it not getting flushed for a long time the delay 376 * shouldn't really matter because there's no real memory 377 * pressure for swapout to react to. ] 378 * 379 * Note: this optimisation also exists in pte_needs_flush() and 380 * huge_pmd_needs_flush(). 381 */ 382 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 383 #define ptep_clear_flush_young ptep_test_and_clear_young 384 385 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 386 #define pmdp_clear_flush_young pmdp_test_and_clear_young 387 388 static inline int pte_write(pte_t pte) 389 { 390 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 391 } 392 393 static inline int pte_read(pte_t pte) 394 { 395 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 396 } 397 398 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 399 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 400 pte_t *ptep) 401 { 402 if (pte_write(*ptep)) 403 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 404 } 405 406 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 407 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 408 unsigned long addr, pte_t *ptep) 409 { 410 if (pte_write(*ptep)) 411 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 412 } 413 414 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 415 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 416 unsigned long addr, pte_t *ptep) 417 { 418 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 419 return __pte(old); 420 } 421 422 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 423 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 424 unsigned long addr, 425 pte_t *ptep, int full) 426 { 427 if (full && radix_enabled()) { 428 /* 429 * We know that this is a full mm pte clear and 430 * hence can be sure there is no parallel set_pte. 431 */ 432 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 433 } 434 return ptep_get_and_clear(mm, addr, ptep); 435 } 436 437 438 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 439 pte_t * ptep) 440 { 441 pte_update(mm, addr, ptep, ~0UL, 0, 0); 442 } 443 444 static inline int pte_dirty(pte_t pte) 445 { 446 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 447 } 448 449 static inline int pte_young(pte_t pte) 450 { 451 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 452 } 453 454 static inline int pte_special(pte_t pte) 455 { 456 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 457 } 458 459 static inline bool pte_exec(pte_t pte) 460 { 461 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 462 } 463 464 465 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 466 static inline bool pte_soft_dirty(pte_t pte) 467 { 468 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 469 } 470 471 static inline pte_t pte_mksoft_dirty(pte_t pte) 472 { 473 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 474 } 475 476 static inline pte_t pte_clear_soft_dirty(pte_t pte) 477 { 478 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 479 } 480 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 481 482 #ifdef CONFIG_NUMA_BALANCING 483 static inline int pte_protnone(pte_t pte) 484 { 485 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 486 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 487 } 488 #endif /* CONFIG_NUMA_BALANCING */ 489 490 static inline bool pte_hw_valid(pte_t pte) 491 { 492 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 493 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 494 } 495 496 static inline int pte_present(pte_t pte) 497 { 498 /* 499 * A pte is considerent present if _PAGE_PRESENT is set. 500 * We also need to consider the pte present which is marked 501 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 502 * if we find _PAGE_PRESENT cleared. 503 */ 504 505 if (pte_hw_valid(pte)) 506 return true; 507 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 508 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 509 } 510 511 #ifdef CONFIG_PPC_MEM_KEYS 512 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 513 #else 514 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 515 { 516 return true; 517 } 518 #endif /* CONFIG_PPC_MEM_KEYS */ 519 520 static inline bool pte_user(pte_t pte) 521 { 522 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 523 } 524 525 #define pte_access_permitted pte_access_permitted 526 static inline bool pte_access_permitted(pte_t pte, bool write) 527 { 528 /* 529 * _PAGE_READ is needed for any access and will be cleared for 530 * PROT_NONE. Execute-only mapping via PROT_EXEC also returns false. 531 */ 532 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 533 return false; 534 535 if (write && !pte_write(pte)) 536 return false; 537 538 return arch_pte_access_permitted(pte_val(pte), write, 0); 539 } 540 541 /* 542 * Conversion functions: convert a page and protection to a page entry, 543 * and a page entry and page directory to the page they refer to. 544 * 545 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 546 * long for now. 547 */ 548 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 549 { 550 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 551 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 552 553 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 554 } 555 556 /* Generic modifiers for PTE bits */ 557 static inline pte_t pte_wrprotect(pte_t pte) 558 { 559 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 560 } 561 562 static inline pte_t pte_exprotect(pte_t pte) 563 { 564 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 565 } 566 567 static inline pte_t pte_mkclean(pte_t pte) 568 { 569 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 570 } 571 572 static inline pte_t pte_mkold(pte_t pte) 573 { 574 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 575 } 576 577 static inline pte_t pte_mkexec(pte_t pte) 578 { 579 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 580 } 581 582 static inline pte_t pte_mkwrite_novma(pte_t pte) 583 { 584 /* 585 * write implies read, hence set both 586 */ 587 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 588 } 589 590 static inline pte_t pte_mkdirty(pte_t pte) 591 { 592 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 593 } 594 595 static inline pte_t pte_mkyoung(pte_t pte) 596 { 597 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 598 } 599 600 static inline pte_t pte_mkspecial(pte_t pte) 601 { 602 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 603 } 604 605 static inline pte_t pte_mkhuge(pte_t pte) 606 { 607 return pte; 608 } 609 610 static inline pte_t pte_mkdevmap(pte_t pte) 611 { 612 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 613 } 614 615 /* 616 * This is potentially called with a pmd as the argument, in which case it's not 617 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 618 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 619 * use in page directory entries (ie. non-ptes). 620 */ 621 static inline int pte_devmap(pte_t pte) 622 { 623 __be64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 624 625 return (pte_raw(pte) & mask) == mask; 626 } 627 628 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 629 { 630 /* FIXME!! check whether this need to be a conditional */ 631 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 632 cpu_to_be64(pgprot_val(newprot))); 633 } 634 635 /* Encode and de-code a swap entry */ 636 #define MAX_SWAPFILES_CHECK() do { \ 637 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 638 /* \ 639 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 640 * We filter HPTEFLAGS on set_pte. \ 641 */ \ 642 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ 643 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 644 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ 645 } while (0) 646 647 #define SWP_TYPE_BITS 5 648 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) 649 #define __swp_type(x) ((x).val & SWP_TYPE_MASK) 650 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 651 #define __swp_entry(type, offset) ((swp_entry_t) { \ 652 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 653 /* 654 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 655 * swap type and offset we get from swap and convert that to pte to find a 656 * matching pte in linux page table. 657 * Clear bits not found in swap entries here. 658 */ 659 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 660 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 661 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 662 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 663 664 #ifdef CONFIG_MEM_SOFT_DIRTY 665 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY 666 #else 667 #define _PAGE_SWP_SOFT_DIRTY 0UL 668 #endif /* CONFIG_MEM_SOFT_DIRTY */ 669 670 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT 671 672 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 673 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 674 { 675 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 676 } 677 678 static inline bool pte_swp_soft_dirty(pte_t pte) 679 { 680 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 681 } 682 683 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 684 { 685 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 686 } 687 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 688 689 static inline pte_t pte_swp_mkexclusive(pte_t pte) 690 { 691 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 692 } 693 694 static inline int pte_swp_exclusive(pte_t pte) 695 { 696 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 697 } 698 699 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 700 { 701 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); 702 } 703 704 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 705 { 706 /* 707 * This check for _PAGE_RWX and _PAGE_PRESENT bits 708 */ 709 if (access & ~ptev) 710 return false; 711 /* 712 * This check for access to privilege space 713 */ 714 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 715 return false; 716 717 return true; 718 } 719 /* 720 * Generic functions with hash/radix callbacks 721 */ 722 723 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 724 pte_t *ptep, pte_t entry, 725 unsigned long address, 726 int psize) 727 { 728 if (radix_enabled()) 729 return radix__ptep_set_access_flags(vma, ptep, entry, 730 address, psize); 731 return hash__ptep_set_access_flags(ptep, entry); 732 } 733 734 #define __HAVE_ARCH_PTE_SAME 735 static inline int pte_same(pte_t pte_a, pte_t pte_b) 736 { 737 if (radix_enabled()) 738 return radix__pte_same(pte_a, pte_b); 739 return hash__pte_same(pte_a, pte_b); 740 } 741 742 static inline int pte_none(pte_t pte) 743 { 744 if (radix_enabled()) 745 return radix__pte_none(pte); 746 return hash__pte_none(pte); 747 } 748 749 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 750 pte_t *ptep, pte_t pte, int percpu) 751 { 752 753 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 754 /* 755 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 756 * in all the callers. 757 */ 758 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 759 760 if (radix_enabled()) 761 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 762 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 763 } 764 765 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 766 767 #define pgprot_noncached pgprot_noncached 768 static inline pgprot_t pgprot_noncached(pgprot_t prot) 769 { 770 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 771 _PAGE_NON_IDEMPOTENT); 772 } 773 774 #define pgprot_noncached_wc pgprot_noncached_wc 775 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 776 { 777 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 778 _PAGE_TOLERANT); 779 } 780 781 #define pgprot_cached pgprot_cached 782 static inline pgprot_t pgprot_cached(pgprot_t prot) 783 { 784 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 785 } 786 787 #define pgprot_writecombine pgprot_writecombine 788 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 789 { 790 return pgprot_noncached_wc(prot); 791 } 792 /* 793 * check a pte mapping have cache inhibited property 794 */ 795 static inline bool pte_ci(pte_t pte) 796 { 797 __be64 pte_v = pte_raw(pte); 798 799 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 800 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 801 return true; 802 return false; 803 } 804 805 static inline void pmd_clear(pmd_t *pmdp) 806 { 807 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 808 /* 809 * Don't use this if we can possibly have a hash page table 810 * entry mapping this. 811 */ 812 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 813 } 814 *pmdp = __pmd(0); 815 } 816 817 static inline int pmd_none(pmd_t pmd) 818 { 819 return !pmd_raw(pmd); 820 } 821 822 static inline int pmd_present(pmd_t pmd) 823 { 824 /* 825 * A pmd is considerent present if _PAGE_PRESENT is set. 826 * We also need to consider the pmd present which is marked 827 * invalid during a split. Hence we look for _PAGE_INVALID 828 * if we find _PAGE_PRESENT cleared. 829 */ 830 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 831 return true; 832 833 return false; 834 } 835 836 static inline int pmd_is_serializing(pmd_t pmd) 837 { 838 /* 839 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 840 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 841 * 842 * This condition may also occur when flushing a pmd while flushing 843 * it (see ptep_modify_prot_start), so callers must ensure this 844 * case is fine as well. 845 */ 846 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 847 cpu_to_be64(_PAGE_INVALID)) 848 return true; 849 850 return false; 851 } 852 853 static inline int pmd_bad(pmd_t pmd) 854 { 855 if (radix_enabled()) 856 return radix__pmd_bad(pmd); 857 return hash__pmd_bad(pmd); 858 } 859 860 static inline void pud_clear(pud_t *pudp) 861 { 862 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 863 /* 864 * Don't use this if we can possibly have a hash page table 865 * entry mapping this. 866 */ 867 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 868 } 869 *pudp = __pud(0); 870 } 871 872 static inline int pud_none(pud_t pud) 873 { 874 return !pud_raw(pud); 875 } 876 877 static inline int pud_present(pud_t pud) 878 { 879 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 880 } 881 882 extern struct page *pud_page(pud_t pud); 883 extern struct page *pmd_page(pmd_t pmd); 884 static inline pte_t pud_pte(pud_t pud) 885 { 886 return __pte_raw(pud_raw(pud)); 887 } 888 889 static inline pud_t pte_pud(pte_t pte) 890 { 891 return __pud_raw(pte_raw(pte)); 892 } 893 894 static inline pte_t *pudp_ptep(pud_t *pud) 895 { 896 return (pte_t *)pud; 897 } 898 899 #define pud_pfn(pud) pte_pfn(pud_pte(pud)) 900 #define pud_dirty(pud) pte_dirty(pud_pte(pud)) 901 #define pud_young(pud) pte_young(pud_pte(pud)) 902 #define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud))) 903 #define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud))) 904 #define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud))) 905 #define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud))) 906 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 907 #define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud))) 908 #define pud_write(pud) pte_write(pud_pte(pud)) 909 910 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 911 #define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud)) 912 #define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud))) 913 #define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud))) 914 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 915 916 static inline int pud_bad(pud_t pud) 917 { 918 if (radix_enabled()) 919 return radix__pud_bad(pud); 920 return hash__pud_bad(pud); 921 } 922 923 #define pud_access_permitted pud_access_permitted 924 static inline bool pud_access_permitted(pud_t pud, bool write) 925 { 926 return pte_access_permitted(pud_pte(pud), write); 927 } 928 929 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 930 static inline __be64 p4d_raw(p4d_t x) 931 { 932 return pgd_raw(x.pgd); 933 } 934 935 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 936 937 static inline void p4d_clear(p4d_t *p4dp) 938 { 939 *p4dp = __p4d(0); 940 } 941 942 static inline int p4d_none(p4d_t p4d) 943 { 944 return !p4d_raw(p4d); 945 } 946 947 static inline int p4d_present(p4d_t p4d) 948 { 949 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 950 } 951 952 static inline pte_t p4d_pte(p4d_t p4d) 953 { 954 return __pte_raw(p4d_raw(p4d)); 955 } 956 957 static inline p4d_t pte_p4d(pte_t pte) 958 { 959 return __p4d_raw(pte_raw(pte)); 960 } 961 962 static inline int p4d_bad(p4d_t p4d) 963 { 964 if (radix_enabled()) 965 return radix__p4d_bad(p4d); 966 return hash__p4d_bad(p4d); 967 } 968 969 #define p4d_access_permitted p4d_access_permitted 970 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 971 { 972 return pte_access_permitted(p4d_pte(p4d), write); 973 } 974 975 extern struct page *p4d_page(p4d_t p4d); 976 977 /* Pointers in the page table tree are physical addresses */ 978 #define __pgtable_ptr_val(ptr) __pa(ptr) 979 980 static inline pud_t *p4d_pgtable(p4d_t p4d) 981 { 982 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); 983 } 984 985 static inline pmd_t *pud_pgtable(pud_t pud) 986 { 987 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); 988 } 989 990 #define pmd_ERROR(e) \ 991 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 992 #define pud_ERROR(e) \ 993 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 994 #define pgd_ERROR(e) \ 995 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 996 997 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 998 { 999 if (radix_enabled()) { 1000 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1001 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1002 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1003 #endif 1004 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1005 } 1006 return hash__map_kernel_page(ea, pa, prot); 1007 } 1008 1009 void unmap_kernel_page(unsigned long va); 1010 1011 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1012 unsigned long page_size, 1013 unsigned long phys) 1014 { 1015 if (radix_enabled()) 1016 return radix__vmemmap_create_mapping(start, page_size, phys); 1017 return hash__vmemmap_create_mapping(start, page_size, phys); 1018 } 1019 1020 #ifdef CONFIG_MEMORY_HOTPLUG 1021 static inline void vmemmap_remove_mapping(unsigned long start, 1022 unsigned long page_size) 1023 { 1024 if (radix_enabled()) 1025 return radix__vmemmap_remove_mapping(start, page_size); 1026 return hash__vmemmap_remove_mapping(start, page_size); 1027 } 1028 #endif 1029 1030 #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE) 1031 static inline void __kernel_map_pages(struct page *page, int numpages, int enable) 1032 { 1033 if (radix_enabled()) 1034 radix__kernel_map_pages(page, numpages, enable); 1035 else 1036 hash__kernel_map_pages(page, numpages, enable); 1037 } 1038 #endif 1039 1040 static inline pte_t pmd_pte(pmd_t pmd) 1041 { 1042 return __pte_raw(pmd_raw(pmd)); 1043 } 1044 1045 static inline pmd_t pte_pmd(pte_t pte) 1046 { 1047 return __pmd_raw(pte_raw(pte)); 1048 } 1049 1050 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1051 { 1052 return (pte_t *)pmd; 1053 } 1054 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1055 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1056 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1057 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1058 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1059 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1060 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1061 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1062 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 1063 1064 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1065 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1066 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1067 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1068 1069 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1070 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1071 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1072 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1073 #endif 1074 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1075 1076 #ifdef CONFIG_NUMA_BALANCING 1077 static inline int pmd_protnone(pmd_t pmd) 1078 { 1079 return pte_protnone(pmd_pte(pmd)); 1080 } 1081 #endif /* CONFIG_NUMA_BALANCING */ 1082 1083 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1084 1085 #define pmd_access_permitted pmd_access_permitted 1086 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1087 { 1088 /* 1089 * pmdp_invalidate sets this combination (which is not caught by 1090 * !pte_present() check in pte_access_permitted), to prevent 1091 * lock-free lookups, as part of the serialize_against_pte_lookup() 1092 * synchronisation. 1093 * 1094 * This also catches the case where the PTE's hardware PRESENT bit is 1095 * cleared while TLB is flushed, which is suboptimal but should not 1096 * be frequent. 1097 */ 1098 if (pmd_is_serializing(pmd)) 1099 return false; 1100 1101 return pte_access_permitted(pmd_pte(pmd), write); 1102 } 1103 1104 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1105 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1106 extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot); 1107 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1108 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1109 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1110 pmd_t *pmdp, pmd_t pmd); 1111 extern void set_pud_at(struct mm_struct *mm, unsigned long addr, 1112 pud_t *pudp, pud_t pud); 1113 1114 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1115 unsigned long addr, pmd_t *pmd) 1116 { 1117 } 1118 1119 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1120 unsigned long addr, pud_t *pud) 1121 { 1122 } 1123 1124 extern int hash__has_transparent_hugepage(void); 1125 static inline int has_transparent_hugepage(void) 1126 { 1127 if (radix_enabled()) 1128 return radix__has_transparent_hugepage(); 1129 return hash__has_transparent_hugepage(); 1130 } 1131 #define has_transparent_hugepage has_transparent_hugepage 1132 1133 static inline int has_transparent_pud_hugepage(void) 1134 { 1135 if (radix_enabled()) 1136 return radix__has_transparent_pud_hugepage(); 1137 return 0; 1138 } 1139 #define has_transparent_pud_hugepage has_transparent_pud_hugepage 1140 1141 static inline unsigned long 1142 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1143 unsigned long clr, unsigned long set) 1144 { 1145 if (radix_enabled()) 1146 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1147 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1148 } 1149 1150 static inline unsigned long 1151 pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp, 1152 unsigned long clr, unsigned long set) 1153 { 1154 if (radix_enabled()) 1155 return radix__pud_hugepage_update(mm, addr, pudp, clr, set); 1156 BUG(); 1157 return pud_val(*pudp); 1158 } 1159 1160 /* 1161 * returns true for pmd migration entries, THP, devmap, hugetlb 1162 * But compile time dependent on THP config 1163 */ 1164 static inline int pmd_large(pmd_t pmd) 1165 { 1166 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1167 } 1168 1169 static inline int pud_large(pud_t pud) 1170 { 1171 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1172 } 1173 1174 /* 1175 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1176 * the below will work for radix too 1177 */ 1178 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1179 unsigned long addr, pmd_t *pmdp) 1180 { 1181 unsigned long old; 1182 1183 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1184 return 0; 1185 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1186 return ((old & _PAGE_ACCESSED) != 0); 1187 } 1188 1189 static inline int __pudp_test_and_clear_young(struct mm_struct *mm, 1190 unsigned long addr, pud_t *pudp) 1191 { 1192 unsigned long old; 1193 1194 if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1195 return 0; 1196 old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0); 1197 return ((old & _PAGE_ACCESSED) != 0); 1198 } 1199 1200 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1201 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1202 pmd_t *pmdp) 1203 { 1204 if (pmd_write(*pmdp)) 1205 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1206 } 1207 1208 #define __HAVE_ARCH_PUDP_SET_WRPROTECT 1209 static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1210 pud_t *pudp) 1211 { 1212 if (pud_write(*pudp)) 1213 pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0); 1214 } 1215 1216 /* 1217 * Only returns true for a THP. False for pmd migration entry. 1218 * We also need to return true when we come across a pte that 1219 * in between a thp split. While splitting THP, we mark the pmd 1220 * invalid (pmdp_invalidate()) before we set it with pte page 1221 * address. A pmd_trans_huge() check against a pmd entry during that time 1222 * should return true. 1223 * We should not call this on a hugetlb entry. We should check for HugeTLB 1224 * entry using vma->vm_flags 1225 * The page table walk rule is explained in Documentation/mm/transhuge.rst 1226 */ 1227 static inline int pmd_trans_huge(pmd_t pmd) 1228 { 1229 if (!pmd_present(pmd)) 1230 return false; 1231 1232 if (radix_enabled()) 1233 return radix__pmd_trans_huge(pmd); 1234 return hash__pmd_trans_huge(pmd); 1235 } 1236 1237 static inline int pud_trans_huge(pud_t pud) 1238 { 1239 if (!pud_present(pud)) 1240 return false; 1241 1242 if (radix_enabled()) 1243 return radix__pud_trans_huge(pud); 1244 return 0; 1245 } 1246 1247 1248 #define __HAVE_ARCH_PMD_SAME 1249 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1250 { 1251 if (radix_enabled()) 1252 return radix__pmd_same(pmd_a, pmd_b); 1253 return hash__pmd_same(pmd_a, pmd_b); 1254 } 1255 1256 #define pud_same pud_same 1257 static inline int pud_same(pud_t pud_a, pud_t pud_b) 1258 { 1259 if (radix_enabled()) 1260 return radix__pud_same(pud_a, pud_b); 1261 return hash__pud_same(pud_a, pud_b); 1262 } 1263 1264 1265 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1266 { 1267 if (radix_enabled()) 1268 return radix__pmd_mkhuge(pmd); 1269 return hash__pmd_mkhuge(pmd); 1270 } 1271 1272 static inline pud_t __pud_mkhuge(pud_t pud) 1273 { 1274 if (radix_enabled()) 1275 return radix__pud_mkhuge(pud); 1276 BUG(); 1277 return pud; 1278 } 1279 1280 /* 1281 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1282 */ 1283 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1284 { 1285 #ifdef CONFIG_DEBUG_VM 1286 if (radix_enabled()) 1287 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1288 else 1289 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1290 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1291 #endif 1292 return pmd; 1293 } 1294 1295 static inline pud_t pud_mkhuge(pud_t pud) 1296 { 1297 #ifdef CONFIG_DEBUG_VM 1298 if (radix_enabled()) 1299 WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0); 1300 else 1301 WARN_ON(1); 1302 #endif 1303 return pud; 1304 } 1305 1306 1307 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1308 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1309 unsigned long address, pmd_t *pmdp, 1310 pmd_t entry, int dirty); 1311 #define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS 1312 extern int pudp_set_access_flags(struct vm_area_struct *vma, 1313 unsigned long address, pud_t *pudp, 1314 pud_t entry, int dirty); 1315 1316 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1317 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1318 unsigned long address, pmd_t *pmdp); 1319 #define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG 1320 extern int pudp_test_and_clear_young(struct vm_area_struct *vma, 1321 unsigned long address, pud_t *pudp); 1322 1323 1324 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1325 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1326 unsigned long addr, pmd_t *pmdp) 1327 { 1328 if (radix_enabled()) 1329 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1330 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1331 } 1332 1333 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1334 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1335 unsigned long addr, pud_t *pudp) 1336 { 1337 if (radix_enabled()) 1338 return radix__pudp_huge_get_and_clear(mm, addr, pudp); 1339 BUG(); 1340 return *pudp; 1341 } 1342 1343 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1344 unsigned long address, pmd_t *pmdp) 1345 { 1346 if (radix_enabled()) 1347 return radix__pmdp_collapse_flush(vma, address, pmdp); 1348 return hash__pmdp_collapse_flush(vma, address, pmdp); 1349 } 1350 #define pmdp_collapse_flush pmdp_collapse_flush 1351 1352 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1353 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1354 unsigned long addr, 1355 pmd_t *pmdp, int full); 1356 1357 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 1358 pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 1359 unsigned long addr, 1360 pud_t *pudp, int full); 1361 1362 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1363 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1364 pmd_t *pmdp, pgtable_t pgtable) 1365 { 1366 if (radix_enabled()) 1367 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1368 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1369 } 1370 1371 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1372 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1373 pmd_t *pmdp) 1374 { 1375 if (radix_enabled()) 1376 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1377 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1378 } 1379 1380 #define __HAVE_ARCH_PMDP_INVALIDATE 1381 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1382 pmd_t *pmdp); 1383 1384 #define pmd_move_must_withdraw pmd_move_must_withdraw 1385 struct spinlock; 1386 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1387 struct spinlock *old_pmd_ptl, 1388 struct vm_area_struct *vma); 1389 /* 1390 * Hash translation mode use the deposited table to store hash pte 1391 * slot information. 1392 */ 1393 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1394 static inline bool arch_needs_pgtable_deposit(void) 1395 { 1396 if (radix_enabled()) 1397 return false; 1398 return true; 1399 } 1400 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1401 1402 1403 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1404 { 1405 if (radix_enabled()) 1406 return radix__pmd_mkdevmap(pmd); 1407 return hash__pmd_mkdevmap(pmd); 1408 } 1409 1410 static inline pud_t pud_mkdevmap(pud_t pud) 1411 { 1412 if (radix_enabled()) 1413 return radix__pud_mkdevmap(pud); 1414 BUG(); 1415 return pud; 1416 } 1417 1418 static inline int pmd_devmap(pmd_t pmd) 1419 { 1420 return pte_devmap(pmd_pte(pmd)); 1421 } 1422 1423 static inline int pud_devmap(pud_t pud) 1424 { 1425 return pte_devmap(pud_pte(pud)); 1426 } 1427 1428 static inline int pgd_devmap(pgd_t pgd) 1429 { 1430 return 0; 1431 } 1432 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1433 1434 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1435 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1436 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1437 pte_t *, pte_t, pte_t); 1438 1439 /* 1440 * Returns true for a R -> RW upgrade of pte 1441 */ 1442 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1443 { 1444 if (!(old_val & _PAGE_READ)) 1445 return false; 1446 1447 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1448 return true; 1449 1450 return false; 1451 } 1452 1453 /* 1454 * Like pmd_huge() and pmd_large(), but works regardless of config options 1455 */ 1456 #define pmd_is_leaf pmd_is_leaf 1457 #define pmd_leaf pmd_is_leaf 1458 static inline bool pmd_is_leaf(pmd_t pmd) 1459 { 1460 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1461 } 1462 1463 #define pud_is_leaf pud_is_leaf 1464 #define pud_leaf pud_is_leaf 1465 static inline bool pud_is_leaf(pud_t pud) 1466 { 1467 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1468 } 1469 1470 #endif /* __ASSEMBLY__ */ 1471 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1472