1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #include <linux/sizes.h> 11 #endif 12 13 /* 14 * Common bits between hash and Radix page table 15 */ 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 21 #define _PAGE_SAO 0x00010 /* Strong access order */ 22 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 23 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 24 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 25 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 26 /* 27 * Software bits 28 */ 29 #define _RPAGE_SW0 0x2000000000000000UL 30 #define _RPAGE_SW1 0x00800 31 #define _RPAGE_SW2 0x00400 32 #define _RPAGE_SW3 0x00200 33 #define _RPAGE_RSV1 0x00040UL 34 35 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 36 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 37 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 38 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 39 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 40 41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 43 /* 44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 46 * differentiate between two use a SW field when invalidating. 47 * 48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 49 * 50 * This is used only when _PAGE_PRESENT is cleared. 51 */ 52 #define _PAGE_INVALID _RPAGE_SW0 53 54 /* 55 * Top and bottom bits of RPN which can be used by hash 56 * translation mode, because we expect them to be zero 57 * otherwise. 58 */ 59 #define _RPAGE_RPN0 0x01000 60 #define _RPAGE_RPN1 0x02000 61 #define _RPAGE_RPN43 0x0080000000000000UL 62 #define _RPAGE_RPN42 0x0040000000000000UL 63 #define _RPAGE_RPN41 0x0020000000000000UL 64 65 /* Max physical address bit as per radix table */ 66 #define _RPAGE_PA_MAX 56 67 68 /* 69 * Max physical address bit we will use for now. 70 * 71 * This is mostly a hardware limitation and for now Power9 has 72 * a 51 bit limit. 73 * 74 * This is different from the number of physical bit required to address 75 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 76 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 77 * number of sections we can support (SECTIONS_SHIFT). 78 * 79 * This is different from Radix page table limitation above and 80 * should always be less than that. The limit is done such that 81 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 82 * for hash linux page table specific bits. 83 * 84 * In order to be compatible with future hardware generations we keep 85 * some offsets and limit this for now to 53 86 */ 87 #define _PAGE_PA_MAX 53 88 89 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 90 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 91 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 92 93 /* 94 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 95 * Instead of fixing all of them, add an alternate define which 96 * maps CI pte mapping. 97 */ 98 #define _PAGE_NO_CACHE _PAGE_TOLERANT 99 /* 100 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 101 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 102 * and every thing below PAGE_SHIFT; 103 */ 104 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 105 #define PTE_RPN_SHIFT PAGE_SHIFT 106 /* 107 * set of bits not changed in pmd_modify. Even though we have hash specific bits 108 * in here, on radix we expect them to be zero. 109 */ 110 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 111 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 112 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 113 /* 114 * user access blocked by key 115 */ 116 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 117 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 118 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 120 /* 121 * _PAGE_CHG_MASK masks of bits that are to be preserved across 122 * pgprot changes 123 */ 124 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 125 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 126 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 127 128 /* 129 * We define 2 sets of base prot bits, one for basic pages (ie, 130 * cacheable kernel and user pages) and one for non cacheable 131 * pages. We always set _PAGE_COHERENT when SMP is enabled or 132 * the processor might need it for DMA coherency. 133 */ 134 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 135 #define _PAGE_BASE (_PAGE_BASE_NC) 136 137 #include <asm/pgtable-masks.h> 138 139 /* Permission masks used for kernel mappings */ 140 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 141 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) 142 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) 143 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 144 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 145 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 146 147 #ifndef __ASSEMBLY__ 148 /* 149 * page table defines 150 */ 151 extern unsigned long __pte_index_size; 152 extern unsigned long __pmd_index_size; 153 extern unsigned long __pud_index_size; 154 extern unsigned long __pgd_index_size; 155 extern unsigned long __pud_cache_index; 156 #define PTE_INDEX_SIZE __pte_index_size 157 #define PMD_INDEX_SIZE __pmd_index_size 158 #define PUD_INDEX_SIZE __pud_index_size 159 #define PGD_INDEX_SIZE __pgd_index_size 160 /* pmd table use page table fragments */ 161 #define PMD_CACHE_INDEX 0 162 #define PUD_CACHE_INDEX __pud_cache_index 163 /* 164 * Because of use of pte fragments and THP, size of page table 165 * are not always derived out of index size above. 166 */ 167 extern unsigned long __pte_table_size; 168 extern unsigned long __pmd_table_size; 169 extern unsigned long __pud_table_size; 170 extern unsigned long __pgd_table_size; 171 #define PTE_TABLE_SIZE __pte_table_size 172 #define PMD_TABLE_SIZE __pmd_table_size 173 #define PUD_TABLE_SIZE __pud_table_size 174 #define PGD_TABLE_SIZE __pgd_table_size 175 176 extern unsigned long __pmd_val_bits; 177 extern unsigned long __pud_val_bits; 178 extern unsigned long __pgd_val_bits; 179 #define PMD_VAL_BITS __pmd_val_bits 180 #define PUD_VAL_BITS __pud_val_bits 181 #define PGD_VAL_BITS __pgd_val_bits 182 183 extern unsigned long __pte_frag_nr; 184 #define PTE_FRAG_NR __pte_frag_nr 185 extern unsigned long __pte_frag_size_shift; 186 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 187 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 188 189 extern unsigned long __pmd_frag_nr; 190 #define PMD_FRAG_NR __pmd_frag_nr 191 extern unsigned long __pmd_frag_size_shift; 192 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 193 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 194 195 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 196 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 197 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 198 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 199 200 #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) 201 #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) 202 #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) 203 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ 204 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) 205 206 /* PMD_SHIFT determines what a second-level page table entry can map */ 207 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 208 #define PMD_SIZE (1UL << PMD_SHIFT) 209 #define PMD_MASK (~(PMD_SIZE-1)) 210 211 /* PUD_SHIFT determines what a third-level page table entry can map */ 212 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 213 #define PUD_SIZE (1UL << PUD_SHIFT) 214 #define PUD_MASK (~(PUD_SIZE-1)) 215 216 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 217 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 218 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 219 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 220 221 /* Bits to mask out from a PMD to get to the PTE page */ 222 #define PMD_MASKED_BITS 0xc0000000000000ffUL 223 /* Bits to mask out from a PUD to get to the PMD page */ 224 #define PUD_MASKED_BITS 0xc0000000000000ffUL 225 /* Bits to mask out from a PGD to get to the PUD page */ 226 #define P4D_MASKED_BITS 0xc0000000000000ffUL 227 228 /* 229 * Used as an indicator for rcu callback functions 230 */ 231 enum pgtable_index { 232 PTE_INDEX = 0, 233 PMD_INDEX, 234 PUD_INDEX, 235 PGD_INDEX, 236 /* 237 * Below are used with 4k page size and hugetlb 238 */ 239 HTLB_16M_INDEX, 240 HTLB_16G_INDEX, 241 }; 242 243 extern unsigned long __vmalloc_start; 244 extern unsigned long __vmalloc_end; 245 #define VMALLOC_START __vmalloc_start 246 #define VMALLOC_END __vmalloc_end 247 248 static inline unsigned int ioremap_max_order(void) 249 { 250 if (radix_enabled()) 251 return PUD_SHIFT; 252 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 253 } 254 #define IOREMAP_MAX_ORDER ioremap_max_order() 255 256 extern unsigned long __kernel_virt_start; 257 extern unsigned long __kernel_io_start; 258 extern unsigned long __kernel_io_end; 259 #define KERN_VIRT_START __kernel_virt_start 260 #define KERN_IO_START __kernel_io_start 261 #define KERN_IO_END __kernel_io_end 262 263 extern struct page *vmemmap; 264 extern unsigned long pci_io_base; 265 266 #define pmd_leaf pmd_leaf 267 static inline bool pmd_leaf(pmd_t pmd) 268 { 269 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 270 } 271 272 #define pud_leaf pud_leaf 273 static inline bool pud_leaf(pud_t pud) 274 { 275 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 276 } 277 278 #define pmd_leaf_size pmd_leaf_size 279 static inline unsigned long pmd_leaf_size(pmd_t pmd) 280 { 281 if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled()) 282 return SZ_16M; 283 else 284 return PMD_SIZE; 285 } 286 287 #define pud_leaf_size pud_leaf_size 288 static inline unsigned long pud_leaf_size(pud_t pud) 289 { 290 if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled()) 291 return SZ_16G; 292 else 293 return PUD_SIZE; 294 } 295 #endif /* __ASSEMBLY__ */ 296 297 #include <asm/book3s/64/hash.h> 298 #include <asm/book3s/64/radix.h> 299 300 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 301 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 302 #else 303 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 304 #endif 305 306 /* hash 4k can't share hugetlb and also doesn't support THP */ 307 #ifdef CONFIG_PPC_64K_PAGES 308 #include <asm/book3s/64/pgtable-64k.h> 309 #endif 310 311 #include <asm/barrier.h> 312 /* 313 * IO space itself carved into the PIO region (ISA and PHB IO space) and 314 * the ioremap space 315 * 316 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 317 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 318 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 319 */ 320 #define FULL_IO_SIZE 0x80000000ul 321 #define ISA_IO_BASE (KERN_IO_START) 322 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 323 #define PHB_IO_BASE (ISA_IO_END) 324 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 325 #define IOREMAP_BASE (PHB_IO_END) 326 #define IOREMAP_START (ioremap_bot) 327 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 328 #define FIXADDR_SIZE SZ_32M 329 #define FIXADDR_TOP (IOREMAP_END + FIXADDR_SIZE) 330 331 #ifndef __ASSEMBLY__ 332 333 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 334 pte_t *ptep, unsigned long clr, 335 unsigned long set, int huge) 336 { 337 if (radix_enabled()) 338 return radix__pte_update(mm, addr, ptep, clr, set, huge); 339 return hash__pte_update(mm, addr, ptep, clr, set, huge); 340 } 341 /* 342 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 343 * We currently remove entries from the hashtable regardless of whether 344 * the entry was young or dirty. 345 * 346 * We should be more intelligent about this but for the moment we override 347 * these functions and force a tlb flush unconditionally 348 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 349 * function for both hash and radix. 350 */ 351 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 352 unsigned long addr, pte_t *ptep) 353 { 354 unsigned long old; 355 356 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 357 return 0; 358 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 359 return (old & _PAGE_ACCESSED) != 0; 360 } 361 362 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 363 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 364 ({ \ 365 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 366 }) 367 368 /* 369 * On Book3S CPUs, clearing the accessed bit without a TLB flush 370 * doesn't cause data corruption. [ It could cause incorrect 371 * page aging and the (mistaken) reclaim of hot pages, but the 372 * chance of that should be relatively low. ] 373 * 374 * So as a performance optimization don't flush the TLB when 375 * clearing the accessed bit, it will eventually be flushed by 376 * a context switch or a VM operation anyway. [ In the rare 377 * event of it not getting flushed for a long time the delay 378 * shouldn't really matter because there's no real memory 379 * pressure for swapout to react to. ] 380 * 381 * Note: this optimisation also exists in pte_needs_flush() and 382 * huge_pmd_needs_flush(). 383 */ 384 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 385 #define ptep_clear_flush_young ptep_test_and_clear_young 386 387 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 388 #define pmdp_clear_flush_young pmdp_test_and_clear_young 389 390 static inline int pte_write(pte_t pte) 391 { 392 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 393 } 394 395 static inline int pte_read(pte_t pte) 396 { 397 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 398 } 399 400 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 401 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 402 pte_t *ptep) 403 { 404 if (pte_write(*ptep)) 405 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 406 } 407 408 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 409 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 410 unsigned long addr, pte_t *ptep) 411 { 412 if (pte_write(*ptep)) 413 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 414 } 415 416 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 417 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 418 unsigned long addr, pte_t *ptep) 419 { 420 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 421 return __pte(old); 422 } 423 424 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 425 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 426 unsigned long addr, 427 pte_t *ptep, int full) 428 { 429 if (full && radix_enabled()) { 430 /* 431 * We know that this is a full mm pte clear and 432 * hence can be sure there is no parallel set_pte. 433 */ 434 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 435 } 436 return ptep_get_and_clear(mm, addr, ptep); 437 } 438 439 440 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 441 pte_t * ptep) 442 { 443 pte_update(mm, addr, ptep, ~0UL, 0, 0); 444 } 445 446 static inline int pte_dirty(pte_t pte) 447 { 448 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 449 } 450 451 static inline int pte_young(pte_t pte) 452 { 453 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 454 } 455 456 static inline int pte_special(pte_t pte) 457 { 458 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 459 } 460 461 static inline bool pte_exec(pte_t pte) 462 { 463 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 464 } 465 466 467 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 468 static inline bool pte_soft_dirty(pte_t pte) 469 { 470 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 471 } 472 473 static inline pte_t pte_mksoft_dirty(pte_t pte) 474 { 475 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 476 } 477 478 static inline pte_t pte_clear_soft_dirty(pte_t pte) 479 { 480 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 481 } 482 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 483 484 #ifdef CONFIG_NUMA_BALANCING 485 static inline int pte_protnone(pte_t pte) 486 { 487 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 488 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 489 } 490 #endif /* CONFIG_NUMA_BALANCING */ 491 492 static inline bool pte_hw_valid(pte_t pte) 493 { 494 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 495 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 496 } 497 498 static inline int pte_present(pte_t pte) 499 { 500 /* 501 * A pte is considerent present if _PAGE_PRESENT is set. 502 * We also need to consider the pte present which is marked 503 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 504 * if we find _PAGE_PRESENT cleared. 505 */ 506 507 if (pte_hw_valid(pte)) 508 return true; 509 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 510 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 511 } 512 513 #ifdef CONFIG_PPC_MEM_KEYS 514 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 515 #else 516 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 517 { 518 return true; 519 } 520 #endif /* CONFIG_PPC_MEM_KEYS */ 521 522 static inline bool pte_user(pte_t pte) 523 { 524 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 525 } 526 527 #define pte_access_permitted pte_access_permitted 528 static inline bool pte_access_permitted(pte_t pte, bool write) 529 { 530 /* 531 * _PAGE_READ is needed for any access and will be cleared for 532 * PROT_NONE. Execute-only mapping via PROT_EXEC also returns false. 533 */ 534 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 535 return false; 536 537 if (write && !pte_write(pte)) 538 return false; 539 540 return arch_pte_access_permitted(pte_val(pte), write, 0); 541 } 542 543 /* 544 * Conversion functions: convert a page and protection to a page entry, 545 * and a page entry and page directory to the page they refer to. 546 * 547 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 548 * long for now. 549 */ 550 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 551 { 552 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 553 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 554 555 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 556 } 557 558 /* Generic modifiers for PTE bits */ 559 static inline pte_t pte_wrprotect(pte_t pte) 560 { 561 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 562 } 563 564 static inline pte_t pte_exprotect(pte_t pte) 565 { 566 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 567 } 568 569 static inline pte_t pte_mkclean(pte_t pte) 570 { 571 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 572 } 573 574 static inline pte_t pte_mkold(pte_t pte) 575 { 576 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 577 } 578 579 static inline pte_t pte_mkexec(pte_t pte) 580 { 581 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 582 } 583 584 static inline pte_t pte_mkwrite_novma(pte_t pte) 585 { 586 /* 587 * write implies read, hence set both 588 */ 589 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 590 } 591 592 static inline pte_t pte_mkdirty(pte_t pte) 593 { 594 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 595 } 596 597 static inline pte_t pte_mkyoung(pte_t pte) 598 { 599 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 600 } 601 602 static inline pte_t pte_mkspecial(pte_t pte) 603 { 604 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 605 } 606 607 static inline pte_t pte_mkhuge(pte_t pte) 608 { 609 return pte; 610 } 611 612 static inline pte_t pte_mkdevmap(pte_t pte) 613 { 614 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 615 } 616 617 /* 618 * This is potentially called with a pmd as the argument, in which case it's not 619 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 620 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 621 * use in page directory entries (ie. non-ptes). 622 */ 623 static inline int pte_devmap(pte_t pte) 624 { 625 __be64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 626 627 return (pte_raw(pte) & mask) == mask; 628 } 629 630 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 631 { 632 /* FIXME!! check whether this need to be a conditional */ 633 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 634 cpu_to_be64(pgprot_val(newprot))); 635 } 636 637 /* Encode and de-code a swap entry */ 638 #define MAX_SWAPFILES_CHECK() do { \ 639 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 640 /* \ 641 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 642 * We filter HPTEFLAGS on set_pte. \ 643 */ \ 644 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ 645 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 646 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ 647 } while (0) 648 649 #define SWP_TYPE_BITS 5 650 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) 651 #define __swp_type(x) ((x).val & SWP_TYPE_MASK) 652 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 653 #define __swp_entry(type, offset) ((swp_entry_t) { \ 654 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 655 /* 656 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 657 * swap type and offset we get from swap and convert that to pte to find a 658 * matching pte in linux page table. 659 * Clear bits not found in swap entries here. 660 */ 661 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 662 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 663 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 664 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 665 666 #ifdef CONFIG_MEM_SOFT_DIRTY 667 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY 668 #else 669 #define _PAGE_SWP_SOFT_DIRTY 0UL 670 #endif /* CONFIG_MEM_SOFT_DIRTY */ 671 672 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT 673 674 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 675 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 676 { 677 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 678 } 679 680 static inline bool pte_swp_soft_dirty(pte_t pte) 681 { 682 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 683 } 684 685 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 686 { 687 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 688 } 689 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 690 691 static inline pte_t pte_swp_mkexclusive(pte_t pte) 692 { 693 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 694 } 695 696 static inline int pte_swp_exclusive(pte_t pte) 697 { 698 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 699 } 700 701 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 702 { 703 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); 704 } 705 706 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 707 { 708 /* 709 * This check for _PAGE_RWX and _PAGE_PRESENT bits 710 */ 711 if (access & ~ptev) 712 return false; 713 /* 714 * This check for access to privilege space 715 */ 716 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 717 return false; 718 719 return true; 720 } 721 /* 722 * Generic functions with hash/radix callbacks 723 */ 724 725 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 726 pte_t *ptep, pte_t entry, 727 unsigned long address, 728 int psize) 729 { 730 if (radix_enabled()) 731 return radix__ptep_set_access_flags(vma, ptep, entry, 732 address, psize); 733 return hash__ptep_set_access_flags(ptep, entry); 734 } 735 736 #define __HAVE_ARCH_PTE_SAME 737 static inline int pte_same(pte_t pte_a, pte_t pte_b) 738 { 739 if (radix_enabled()) 740 return radix__pte_same(pte_a, pte_b); 741 return hash__pte_same(pte_a, pte_b); 742 } 743 744 static inline int pte_none(pte_t pte) 745 { 746 if (radix_enabled()) 747 return radix__pte_none(pte); 748 return hash__pte_none(pte); 749 } 750 751 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 752 pte_t *ptep, pte_t pte, int percpu) 753 { 754 755 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 756 /* 757 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 758 * in all the callers. 759 */ 760 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 761 762 if (radix_enabled()) 763 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 764 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 765 } 766 767 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 768 769 #define pgprot_noncached pgprot_noncached 770 static inline pgprot_t pgprot_noncached(pgprot_t prot) 771 { 772 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 773 _PAGE_NON_IDEMPOTENT); 774 } 775 776 #define pgprot_noncached_wc pgprot_noncached_wc 777 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 778 { 779 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 780 _PAGE_TOLERANT); 781 } 782 783 #define pgprot_cached pgprot_cached 784 static inline pgprot_t pgprot_cached(pgprot_t prot) 785 { 786 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 787 } 788 789 #define pgprot_writecombine pgprot_writecombine 790 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 791 { 792 return pgprot_noncached_wc(prot); 793 } 794 /* 795 * check a pte mapping have cache inhibited property 796 */ 797 static inline bool pte_ci(pte_t pte) 798 { 799 __be64 pte_v = pte_raw(pte); 800 801 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 802 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 803 return true; 804 return false; 805 } 806 807 static inline void pmd_clear(pmd_t *pmdp) 808 { 809 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 810 /* 811 * Don't use this if we can possibly have a hash page table 812 * entry mapping this. 813 */ 814 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 815 } 816 *pmdp = __pmd(0); 817 } 818 819 static inline int pmd_none(pmd_t pmd) 820 { 821 return !pmd_raw(pmd); 822 } 823 824 static inline int pmd_present(pmd_t pmd) 825 { 826 /* 827 * A pmd is considerent present if _PAGE_PRESENT is set. 828 * We also need to consider the pmd present which is marked 829 * invalid during a split. Hence we look for _PAGE_INVALID 830 * if we find _PAGE_PRESENT cleared. 831 */ 832 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 833 return true; 834 835 return false; 836 } 837 838 static inline int pmd_is_serializing(pmd_t pmd) 839 { 840 /* 841 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 842 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 843 * 844 * This condition may also occur when flushing a pmd while flushing 845 * it (see ptep_modify_prot_start), so callers must ensure this 846 * case is fine as well. 847 */ 848 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 849 cpu_to_be64(_PAGE_INVALID)) 850 return true; 851 852 return false; 853 } 854 855 static inline int pmd_bad(pmd_t pmd) 856 { 857 if (radix_enabled()) 858 return radix__pmd_bad(pmd); 859 return hash__pmd_bad(pmd); 860 } 861 862 static inline void pud_clear(pud_t *pudp) 863 { 864 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 865 /* 866 * Don't use this if we can possibly have a hash page table 867 * entry mapping this. 868 */ 869 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 870 } 871 *pudp = __pud(0); 872 } 873 874 static inline int pud_none(pud_t pud) 875 { 876 return !pud_raw(pud); 877 } 878 879 static inline int pud_present(pud_t pud) 880 { 881 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 882 } 883 884 extern struct page *pud_page(pud_t pud); 885 extern struct page *pmd_page(pmd_t pmd); 886 static inline pte_t pud_pte(pud_t pud) 887 { 888 return __pte_raw(pud_raw(pud)); 889 } 890 891 static inline pud_t pte_pud(pte_t pte) 892 { 893 return __pud_raw(pte_raw(pte)); 894 } 895 896 static inline pte_t *pudp_ptep(pud_t *pud) 897 { 898 return (pte_t *)pud; 899 } 900 901 #define pud_pfn(pud) pte_pfn(pud_pte(pud)) 902 #define pud_dirty(pud) pte_dirty(pud_pte(pud)) 903 #define pud_young(pud) pte_young(pud_pte(pud)) 904 #define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud))) 905 #define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud))) 906 #define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud))) 907 #define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud))) 908 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 909 #define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud))) 910 #define pud_write(pud) pte_write(pud_pte(pud)) 911 912 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 913 #define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud)) 914 #define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud))) 915 #define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud))) 916 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 917 918 static inline int pud_bad(pud_t pud) 919 { 920 if (radix_enabled()) 921 return radix__pud_bad(pud); 922 return hash__pud_bad(pud); 923 } 924 925 #define pud_access_permitted pud_access_permitted 926 static inline bool pud_access_permitted(pud_t pud, bool write) 927 { 928 return pte_access_permitted(pud_pte(pud), write); 929 } 930 931 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 932 static inline __be64 p4d_raw(p4d_t x) 933 { 934 return pgd_raw(x.pgd); 935 } 936 937 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 938 939 static inline void p4d_clear(p4d_t *p4dp) 940 { 941 *p4dp = __p4d(0); 942 } 943 944 static inline int p4d_none(p4d_t p4d) 945 { 946 return !p4d_raw(p4d); 947 } 948 949 static inline int p4d_present(p4d_t p4d) 950 { 951 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 952 } 953 954 static inline pte_t p4d_pte(p4d_t p4d) 955 { 956 return __pte_raw(p4d_raw(p4d)); 957 } 958 959 static inline p4d_t pte_p4d(pte_t pte) 960 { 961 return __p4d_raw(pte_raw(pte)); 962 } 963 964 static inline int p4d_bad(p4d_t p4d) 965 { 966 if (radix_enabled()) 967 return radix__p4d_bad(p4d); 968 return hash__p4d_bad(p4d); 969 } 970 971 #define p4d_access_permitted p4d_access_permitted 972 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 973 { 974 return pte_access_permitted(p4d_pte(p4d), write); 975 } 976 977 extern struct page *p4d_page(p4d_t p4d); 978 979 /* Pointers in the page table tree are physical addresses */ 980 #define __pgtable_ptr_val(ptr) __pa(ptr) 981 982 static inline pud_t *p4d_pgtable(p4d_t p4d) 983 { 984 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); 985 } 986 987 static inline pmd_t *pud_pgtable(pud_t pud) 988 { 989 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); 990 } 991 992 #define pmd_ERROR(e) \ 993 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 994 #define pud_ERROR(e) \ 995 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 996 #define pgd_ERROR(e) \ 997 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 998 999 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1000 { 1001 if (radix_enabled()) { 1002 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1003 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1004 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1005 #endif 1006 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1007 } 1008 return hash__map_kernel_page(ea, pa, prot); 1009 } 1010 1011 void unmap_kernel_page(unsigned long va); 1012 1013 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1014 unsigned long page_size, 1015 unsigned long phys) 1016 { 1017 if (radix_enabled()) 1018 return radix__vmemmap_create_mapping(start, page_size, phys); 1019 return hash__vmemmap_create_mapping(start, page_size, phys); 1020 } 1021 1022 #ifdef CONFIG_MEMORY_HOTPLUG 1023 static inline void vmemmap_remove_mapping(unsigned long start, 1024 unsigned long page_size) 1025 { 1026 if (radix_enabled()) 1027 return radix__vmemmap_remove_mapping(start, page_size); 1028 return hash__vmemmap_remove_mapping(start, page_size); 1029 } 1030 #endif 1031 1032 static inline pte_t pmd_pte(pmd_t pmd) 1033 { 1034 return __pte_raw(pmd_raw(pmd)); 1035 } 1036 1037 static inline pmd_t pte_pmd(pte_t pte) 1038 { 1039 return __pmd_raw(pte_raw(pte)); 1040 } 1041 1042 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1043 { 1044 return (pte_t *)pmd; 1045 } 1046 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1047 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1048 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1049 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1050 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1051 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1052 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1053 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1054 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 1055 1056 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1057 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1058 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1059 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1060 1061 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1062 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1063 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1064 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1065 #endif 1066 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1067 1068 #ifdef CONFIG_NUMA_BALANCING 1069 static inline int pmd_protnone(pmd_t pmd) 1070 { 1071 return pte_protnone(pmd_pte(pmd)); 1072 } 1073 #endif /* CONFIG_NUMA_BALANCING */ 1074 1075 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1076 1077 #define pmd_access_permitted pmd_access_permitted 1078 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1079 { 1080 /* 1081 * pmdp_invalidate sets this combination (which is not caught by 1082 * !pte_present() check in pte_access_permitted), to prevent 1083 * lock-free lookups, as part of the serialize_against_pte_lookup() 1084 * synchronisation. 1085 * 1086 * This also catches the case where the PTE's hardware PRESENT bit is 1087 * cleared while TLB is flushed, which is suboptimal but should not 1088 * be frequent. 1089 */ 1090 if (pmd_is_serializing(pmd)) 1091 return false; 1092 1093 return pte_access_permitted(pmd_pte(pmd), write); 1094 } 1095 1096 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1097 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1098 extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot); 1099 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1100 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1101 extern pud_t pud_modify(pud_t pud, pgprot_t newprot); 1102 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1103 pmd_t *pmdp, pmd_t pmd); 1104 extern void set_pud_at(struct mm_struct *mm, unsigned long addr, 1105 pud_t *pudp, pud_t pud); 1106 1107 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1108 unsigned long addr, pmd_t *pmd) 1109 { 1110 } 1111 1112 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1113 unsigned long addr, pud_t *pud) 1114 { 1115 } 1116 1117 extern int hash__has_transparent_hugepage(void); 1118 static inline int has_transparent_hugepage(void) 1119 { 1120 if (radix_enabled()) 1121 return radix__has_transparent_hugepage(); 1122 return hash__has_transparent_hugepage(); 1123 } 1124 #define has_transparent_hugepage has_transparent_hugepage 1125 1126 static inline int has_transparent_pud_hugepage(void) 1127 { 1128 if (radix_enabled()) 1129 return radix__has_transparent_pud_hugepage(); 1130 return 0; 1131 } 1132 #define has_transparent_pud_hugepage has_transparent_pud_hugepage 1133 1134 static inline unsigned long 1135 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1136 unsigned long clr, unsigned long set) 1137 { 1138 if (radix_enabled()) 1139 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1140 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1141 } 1142 1143 static inline unsigned long 1144 pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp, 1145 unsigned long clr, unsigned long set) 1146 { 1147 if (radix_enabled()) 1148 return radix__pud_hugepage_update(mm, addr, pudp, clr, set); 1149 BUG(); 1150 return pud_val(*pudp); 1151 } 1152 1153 /* 1154 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1155 * the below will work for radix too 1156 */ 1157 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1158 unsigned long addr, pmd_t *pmdp) 1159 { 1160 unsigned long old; 1161 1162 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1163 return 0; 1164 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1165 return ((old & _PAGE_ACCESSED) != 0); 1166 } 1167 1168 static inline int __pudp_test_and_clear_young(struct mm_struct *mm, 1169 unsigned long addr, pud_t *pudp) 1170 { 1171 unsigned long old; 1172 1173 if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1174 return 0; 1175 old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0); 1176 return ((old & _PAGE_ACCESSED) != 0); 1177 } 1178 1179 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1180 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1181 pmd_t *pmdp) 1182 { 1183 if (pmd_write(*pmdp)) 1184 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1185 } 1186 1187 #define __HAVE_ARCH_PUDP_SET_WRPROTECT 1188 static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1189 pud_t *pudp) 1190 { 1191 if (pud_write(*pudp)) 1192 pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0); 1193 } 1194 1195 /* 1196 * Only returns true for a THP. False for pmd migration entry. 1197 * We also need to return true when we come across a pte that 1198 * in between a thp split. While splitting THP, we mark the pmd 1199 * invalid (pmdp_invalidate()) before we set it with pte page 1200 * address. A pmd_trans_huge() check against a pmd entry during that time 1201 * should return true. 1202 * We should not call this on a hugetlb entry. We should check for HugeTLB 1203 * entry using vma->vm_flags 1204 * The page table walk rule is explained in Documentation/mm/transhuge.rst 1205 */ 1206 static inline int pmd_trans_huge(pmd_t pmd) 1207 { 1208 if (!pmd_present(pmd)) 1209 return false; 1210 1211 if (radix_enabled()) 1212 return radix__pmd_trans_huge(pmd); 1213 return hash__pmd_trans_huge(pmd); 1214 } 1215 1216 static inline int pud_trans_huge(pud_t pud) 1217 { 1218 if (!pud_present(pud)) 1219 return false; 1220 1221 if (radix_enabled()) 1222 return radix__pud_trans_huge(pud); 1223 return 0; 1224 } 1225 1226 1227 #define __HAVE_ARCH_PMD_SAME 1228 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1229 { 1230 if (radix_enabled()) 1231 return radix__pmd_same(pmd_a, pmd_b); 1232 return hash__pmd_same(pmd_a, pmd_b); 1233 } 1234 1235 #define pud_same pud_same 1236 static inline int pud_same(pud_t pud_a, pud_t pud_b) 1237 { 1238 if (radix_enabled()) 1239 return radix__pud_same(pud_a, pud_b); 1240 return hash__pud_same(pud_a, pud_b); 1241 } 1242 1243 1244 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1245 { 1246 if (radix_enabled()) 1247 return radix__pmd_mkhuge(pmd); 1248 return hash__pmd_mkhuge(pmd); 1249 } 1250 1251 static inline pud_t __pud_mkhuge(pud_t pud) 1252 { 1253 if (radix_enabled()) 1254 return radix__pud_mkhuge(pud); 1255 BUG(); 1256 return pud; 1257 } 1258 1259 /* 1260 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1261 */ 1262 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1263 { 1264 #ifdef CONFIG_DEBUG_VM 1265 if (radix_enabled()) 1266 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1267 else 1268 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1269 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1270 #endif 1271 return pmd; 1272 } 1273 1274 static inline pud_t pud_mkhuge(pud_t pud) 1275 { 1276 #ifdef CONFIG_DEBUG_VM 1277 if (radix_enabled()) 1278 WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0); 1279 else 1280 WARN_ON(1); 1281 #endif 1282 return pud; 1283 } 1284 1285 1286 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1287 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1288 unsigned long address, pmd_t *pmdp, 1289 pmd_t entry, int dirty); 1290 #define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS 1291 extern int pudp_set_access_flags(struct vm_area_struct *vma, 1292 unsigned long address, pud_t *pudp, 1293 pud_t entry, int dirty); 1294 1295 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1296 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1297 unsigned long address, pmd_t *pmdp); 1298 #define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG 1299 extern int pudp_test_and_clear_young(struct vm_area_struct *vma, 1300 unsigned long address, pud_t *pudp); 1301 1302 1303 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1304 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1305 unsigned long addr, pmd_t *pmdp) 1306 { 1307 if (radix_enabled()) 1308 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1309 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1310 } 1311 1312 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1313 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1314 unsigned long addr, pud_t *pudp) 1315 { 1316 if (radix_enabled()) 1317 return radix__pudp_huge_get_and_clear(mm, addr, pudp); 1318 BUG(); 1319 return *pudp; 1320 } 1321 1322 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1323 unsigned long address, pmd_t *pmdp) 1324 { 1325 if (radix_enabled()) 1326 return radix__pmdp_collapse_flush(vma, address, pmdp); 1327 return hash__pmdp_collapse_flush(vma, address, pmdp); 1328 } 1329 #define pmdp_collapse_flush pmdp_collapse_flush 1330 1331 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1332 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1333 unsigned long addr, 1334 pmd_t *pmdp, int full); 1335 1336 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 1337 pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 1338 unsigned long addr, 1339 pud_t *pudp, int full); 1340 1341 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1342 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1343 pmd_t *pmdp, pgtable_t pgtable) 1344 { 1345 if (radix_enabled()) 1346 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1347 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1348 } 1349 1350 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1351 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1352 pmd_t *pmdp) 1353 { 1354 if (radix_enabled()) 1355 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1356 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1357 } 1358 1359 #define __HAVE_ARCH_PMDP_INVALIDATE 1360 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1361 pmd_t *pmdp); 1362 extern pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address, 1363 pud_t *pudp); 1364 1365 #define pmd_move_must_withdraw pmd_move_must_withdraw 1366 struct spinlock; 1367 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1368 struct spinlock *old_pmd_ptl, 1369 struct vm_area_struct *vma); 1370 /* 1371 * Hash translation mode use the deposited table to store hash pte 1372 * slot information. 1373 */ 1374 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1375 static inline bool arch_needs_pgtable_deposit(void) 1376 { 1377 if (radix_enabled()) 1378 return false; 1379 return true; 1380 } 1381 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1382 1383 1384 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1385 { 1386 if (radix_enabled()) 1387 return radix__pmd_mkdevmap(pmd); 1388 return hash__pmd_mkdevmap(pmd); 1389 } 1390 1391 static inline pud_t pud_mkdevmap(pud_t pud) 1392 { 1393 if (radix_enabled()) 1394 return radix__pud_mkdevmap(pud); 1395 BUG(); 1396 return pud; 1397 } 1398 1399 static inline int pmd_devmap(pmd_t pmd) 1400 { 1401 return pte_devmap(pmd_pte(pmd)); 1402 } 1403 1404 static inline int pud_devmap(pud_t pud) 1405 { 1406 return pte_devmap(pud_pte(pud)); 1407 } 1408 1409 static inline int pgd_devmap(pgd_t pgd) 1410 { 1411 return 0; 1412 } 1413 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1414 1415 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1416 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1417 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1418 pte_t *, pte_t, pte_t); 1419 1420 /* 1421 * Returns true for a R -> RW upgrade of pte 1422 */ 1423 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1424 { 1425 if (!(old_val & _PAGE_READ)) 1426 return false; 1427 1428 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1429 return true; 1430 1431 return false; 1432 } 1433 1434 #endif /* __ASSEMBLY__ */ 1435 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1436