1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLER__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #include <linux/sizes.h> 11 #endif 12 13 /* 14 * Common bits between hash and Radix page table 15 */ 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 21 #define _PAGE_SAO 0x00010 /* Strong access order */ 22 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 23 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 24 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 25 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 26 /* 27 * Software bits 28 */ 29 #define _RPAGE_SW0 0x2000000000000000UL 30 #define _RPAGE_SW1 0x00800 31 #define _RPAGE_SW2 0x00400 32 #define _RPAGE_SW3 0x00200 33 #define _RPAGE_RSV1 0x00040UL 34 35 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 36 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 37 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 38 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 39 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 40 41 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 42 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 43 /* 44 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 45 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 46 * differentiate between two use a SW field when invalidating. 47 * 48 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 49 * 50 * This is used only when _PAGE_PRESENT is cleared. 51 */ 52 #define _PAGE_INVALID _RPAGE_SW0 53 54 /* 55 * Top and bottom bits of RPN which can be used by hash 56 * translation mode, because we expect them to be zero 57 * otherwise. 58 */ 59 #define _RPAGE_RPN0 0x01000 60 #define _RPAGE_RPN1 0x02000 61 #define _RPAGE_RPN43 0x0080000000000000UL 62 #define _RPAGE_RPN42 0x0040000000000000UL 63 #define _RPAGE_RPN41 0x0020000000000000UL 64 65 /* Max physical address bit as per radix table */ 66 #define _RPAGE_PA_MAX 56 67 68 /* 69 * Max physical address bit we will use for now. 70 * 71 * This is mostly a hardware limitation and for now Power9 has 72 * a 51 bit limit. 73 * 74 * This is different from the number of physical bit required to address 75 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 76 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 77 * number of sections we can support (SECTIONS_SHIFT). 78 * 79 * This is different from Radix page table limitation above and 80 * should always be less than that. The limit is done such that 81 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 82 * for hash linux page table specific bits. 83 * 84 * In order to be compatible with future hardware generations we keep 85 * some offsets and limit this for now to 53 86 */ 87 #define _PAGE_PA_MAX 53 88 89 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 90 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 91 92 /* 93 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 94 * Instead of fixing all of them, add an alternate define which 95 * maps CI pte mapping. 96 */ 97 #define _PAGE_NO_CACHE _PAGE_TOLERANT 98 /* 99 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 100 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 101 * and every thing below PAGE_SHIFT; 102 */ 103 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 104 #define PTE_RPN_SHIFT PAGE_SHIFT 105 /* 106 * set of bits not changed in pmd_modify. Even though we have hash specific bits 107 * in here, on radix we expect them to be zero. 108 */ 109 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 110 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 111 _PAGE_SOFT_DIRTY) 112 /* 113 * user access blocked by key 114 */ 115 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 116 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 117 #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) 118 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) 119 /* 120 * _PAGE_CHG_MASK masks of bits that are to be preserved across 121 * pgprot changes 122 */ 123 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 124 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 125 _PAGE_SOFT_DIRTY) 126 127 /* 128 * We define 2 sets of base prot bits, one for basic pages (ie, 129 * cacheable kernel and user pages) and one for non cacheable 130 * pages. We always set _PAGE_COHERENT when SMP is enabled or 131 * the processor might need it for DMA coherency. 132 */ 133 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 134 #define _PAGE_BASE (_PAGE_BASE_NC) 135 136 #include <asm/pgtable-masks.h> 137 138 /* Permission masks used for kernel mappings */ 139 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 140 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) 141 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) 142 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 143 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 144 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 145 146 #ifndef __ASSEMBLER__ 147 #include <linux/page_table_check.h> 148 149 /* 150 * page table defines 151 */ 152 extern unsigned long __pte_index_size; 153 extern unsigned long __pmd_index_size; 154 extern unsigned long __pud_index_size; 155 extern unsigned long __pgd_index_size; 156 extern unsigned long __pud_cache_index; 157 #define PTE_INDEX_SIZE __pte_index_size 158 #define PMD_INDEX_SIZE __pmd_index_size 159 #define PUD_INDEX_SIZE __pud_index_size 160 #define PGD_INDEX_SIZE __pgd_index_size 161 /* pmd table use page table fragments */ 162 #define PMD_CACHE_INDEX 0 163 #define PUD_CACHE_INDEX __pud_cache_index 164 /* 165 * Because of use of pte fragments and THP, size of page table 166 * are not always derived out of index size above. 167 */ 168 extern unsigned long __pte_table_size; 169 extern unsigned long __pmd_table_size; 170 extern unsigned long __pud_table_size; 171 extern unsigned long __pgd_table_size; 172 #define PTE_TABLE_SIZE __pte_table_size 173 #define PMD_TABLE_SIZE __pmd_table_size 174 #define PUD_TABLE_SIZE __pud_table_size 175 #define PGD_TABLE_SIZE __pgd_table_size 176 177 extern unsigned long __pmd_val_bits; 178 extern unsigned long __pud_val_bits; 179 extern unsigned long __pgd_val_bits; 180 #define PMD_VAL_BITS __pmd_val_bits 181 #define PUD_VAL_BITS __pud_val_bits 182 #define PGD_VAL_BITS __pgd_val_bits 183 184 extern unsigned long __pte_frag_nr; 185 #define PTE_FRAG_NR __pte_frag_nr 186 extern unsigned long __pte_frag_size_shift; 187 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 188 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 189 190 extern unsigned long __pmd_frag_nr; 191 #define PMD_FRAG_NR __pmd_frag_nr 192 extern unsigned long __pmd_frag_size_shift; 193 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 194 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 195 196 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 197 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 198 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 199 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 200 201 #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) 202 #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) 203 #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) 204 #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ 205 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) 206 207 /* PMD_SHIFT determines what a second-level page table entry can map */ 208 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 209 #define PMD_SIZE (1UL << PMD_SHIFT) 210 #define PMD_MASK (~(PMD_SIZE-1)) 211 212 /* PUD_SHIFT determines what a third-level page table entry can map */ 213 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 214 #define PUD_SIZE (1UL << PUD_SHIFT) 215 #define PUD_MASK (~(PUD_SIZE-1)) 216 217 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 218 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 219 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 220 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 221 222 /* Bits to mask out from a PMD to get to the PTE page */ 223 #define PMD_MASKED_BITS 0xc0000000000000ffUL 224 /* Bits to mask out from a PUD to get to the PMD page */ 225 #define PUD_MASKED_BITS 0xc0000000000000ffUL 226 /* Bits to mask out from a PGD to get to the PUD page */ 227 #define P4D_MASKED_BITS 0xc0000000000000ffUL 228 229 /* 230 * Used as an indicator for rcu callback functions 231 */ 232 enum pgtable_index { 233 PTE_INDEX = 0, 234 PMD_INDEX, 235 PUD_INDEX, 236 PGD_INDEX, 237 /* 238 * Below are used with 4k page size and hugetlb 239 */ 240 HTLB_16M_INDEX, 241 HTLB_16G_INDEX, 242 }; 243 244 extern unsigned long __vmalloc_start; 245 extern unsigned long __vmalloc_end; 246 #define VMALLOC_START __vmalloc_start 247 #define VMALLOC_END __vmalloc_end 248 249 static inline unsigned int ioremap_max_order(void) 250 { 251 if (radix_enabled()) 252 return PUD_SHIFT; 253 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 254 } 255 #define IOREMAP_MAX_ORDER ioremap_max_order() 256 257 extern unsigned long __kernel_virt_start; 258 extern unsigned long __kernel_io_start; 259 extern unsigned long __kernel_io_end; 260 #define KERN_VIRT_START __kernel_virt_start 261 #define KERN_IO_START __kernel_io_start 262 #define KERN_IO_END __kernel_io_end 263 264 extern struct page *vmemmap; 265 extern unsigned long pci_io_base; 266 267 #define pmd_leaf pmd_leaf 268 static inline bool pmd_leaf(pmd_t pmd) 269 { 270 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 271 } 272 273 #define pud_leaf pud_leaf 274 static inline bool pud_leaf(pud_t pud) 275 { 276 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 277 } 278 279 #define pmd_leaf_size pmd_leaf_size 280 static inline unsigned long pmd_leaf_size(pmd_t pmd) 281 { 282 if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled()) 283 return SZ_16M; 284 else 285 return PMD_SIZE; 286 } 287 288 #define pud_leaf_size pud_leaf_size 289 static inline unsigned long pud_leaf_size(pud_t pud) 290 { 291 if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !radix_enabled()) 292 return SZ_16G; 293 else 294 return PUD_SIZE; 295 } 296 #endif /* __ASSEMBLER__ */ 297 298 #include <asm/book3s/64/hash.h> 299 #include <asm/book3s/64/radix.h> 300 301 #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS 302 #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS 303 #else 304 #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS 305 #endif 306 307 /* hash 4k can't share hugetlb and also doesn't support THP */ 308 #ifdef CONFIG_PPC_64K_PAGES 309 #include <asm/book3s/64/pgtable-64k.h> 310 #endif 311 312 #include <asm/barrier.h> 313 /* 314 * IO space itself carved into the PIO region (ISA and PHB IO space) and 315 * the ioremap space 316 * 317 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 318 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 319 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 320 */ 321 #define FULL_IO_SIZE 0x80000000ul 322 #define ISA_IO_BASE (KERN_IO_START) 323 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 324 #define PHB_IO_BASE (ISA_IO_END) 325 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 326 #define IOREMAP_BASE (PHB_IO_END) 327 #define IOREMAP_START (ioremap_bot) 328 #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) 329 #define FIXADDR_SIZE SZ_32M 330 #define FIXADDR_TOP (IOREMAP_END + FIXADDR_SIZE) 331 332 #ifndef __ASSEMBLER__ 333 334 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 335 pte_t *ptep, unsigned long clr, 336 unsigned long set, int huge) 337 { 338 if (radix_enabled()) 339 return radix__pte_update(mm, addr, ptep, clr, set, huge); 340 return hash__pte_update(mm, addr, ptep, clr, set, huge); 341 } 342 /* 343 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 344 * We currently remove entries from the hashtable regardless of whether 345 * the entry was young or dirty. 346 * 347 * We should be more intelligent about this but for the moment we override 348 * these functions and force a tlb flush unconditionally 349 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 350 * function for both hash and radix. 351 */ 352 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 353 unsigned long addr, pte_t *ptep) 354 { 355 unsigned long old; 356 357 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 358 return 0; 359 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 360 return (old & _PAGE_ACCESSED) != 0; 361 } 362 363 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 364 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 365 ({ \ 366 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 367 }) 368 369 /* 370 * On Book3S CPUs, clearing the accessed bit without a TLB flush 371 * doesn't cause data corruption. [ It could cause incorrect 372 * page aging and the (mistaken) reclaim of hot pages, but the 373 * chance of that should be relatively low. ] 374 * 375 * So as a performance optimization don't flush the TLB when 376 * clearing the accessed bit, it will eventually be flushed by 377 * a context switch or a VM operation anyway. [ In the rare 378 * event of it not getting flushed for a long time the delay 379 * shouldn't really matter because there's no real memory 380 * pressure for swapout to react to. ] 381 * 382 * Note: this optimisation also exists in pte_needs_flush() and 383 * huge_pmd_needs_flush(). 384 */ 385 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 386 #define ptep_clear_flush_young ptep_test_and_clear_young 387 388 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH 389 #define pmdp_clear_flush_young pmdp_test_and_clear_young 390 391 static inline int pte_write(pte_t pte) 392 { 393 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 394 } 395 396 static inline int pte_read(pte_t pte) 397 { 398 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 399 } 400 401 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 402 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 403 pte_t *ptep) 404 { 405 if (pte_write(*ptep)) 406 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 407 } 408 409 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 410 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 411 unsigned long addr, pte_t *ptep) 412 { 413 if (pte_write(*ptep)) 414 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 415 } 416 417 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 418 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 419 unsigned long addr, pte_t *ptep) 420 { 421 pte_t old_pte = __pte(pte_update(mm, addr, ptep, ~0UL, 0, 0)); 422 423 page_table_check_pte_clear(mm, addr, old_pte); 424 425 return old_pte; 426 } 427 428 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 429 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 430 unsigned long addr, 431 pte_t *ptep, int full) 432 { 433 if (full && radix_enabled()) { 434 pte_t old_pte; 435 436 /* 437 * We know that this is a full mm pte clear and 438 * hence can be sure there is no parallel set_pte. 439 */ 440 old_pte = radix__ptep_get_and_clear_full(mm, addr, ptep, full); 441 page_table_check_pte_clear(mm, addr, old_pte); 442 443 return old_pte; 444 } 445 return ptep_get_and_clear(mm, addr, ptep); 446 } 447 448 449 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 450 pte_t * ptep) 451 { 452 pte_update(mm, addr, ptep, ~0UL, 0, 0); 453 } 454 455 static inline int pte_dirty(pte_t pte) 456 { 457 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 458 } 459 460 static inline int pte_young(pte_t pte) 461 { 462 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 463 } 464 465 static inline int pte_special(pte_t pte) 466 { 467 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 468 } 469 470 static inline bool pte_exec(pte_t pte) 471 { 472 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 473 } 474 475 476 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 477 static inline bool pte_soft_dirty(pte_t pte) 478 { 479 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 480 } 481 482 static inline pte_t pte_mksoft_dirty(pte_t pte) 483 { 484 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 485 } 486 487 static inline pte_t pte_clear_soft_dirty(pte_t pte) 488 { 489 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 490 } 491 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 492 493 #ifdef CONFIG_NUMA_BALANCING 494 static inline int pte_protnone(pte_t pte) 495 { 496 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 497 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 498 } 499 #endif /* CONFIG_NUMA_BALANCING */ 500 501 static inline bool pte_hw_valid(pte_t pte) 502 { 503 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 504 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 505 } 506 507 static inline int pte_present(pte_t pte) 508 { 509 /* 510 * A pte is considerent present if _PAGE_PRESENT is set. 511 * We also need to consider the pte present which is marked 512 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 513 * if we find _PAGE_PRESENT cleared. 514 */ 515 516 if (pte_hw_valid(pte)) 517 return true; 518 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 519 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 520 } 521 522 #ifdef CONFIG_PPC_MEM_KEYS 523 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 524 #else 525 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 526 { 527 return true; 528 } 529 #endif /* CONFIG_PPC_MEM_KEYS */ 530 531 static inline bool pte_user(pte_t pte) 532 { 533 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 534 } 535 536 #define pte_access_permitted pte_access_permitted 537 static inline bool pte_access_permitted(pte_t pte, bool write) 538 { 539 /* 540 * _PAGE_READ is needed for any access and will be cleared for 541 * PROT_NONE. Execute-only mapping via PROT_EXEC also returns false. 542 */ 543 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 544 return false; 545 546 if (write && !pte_write(pte)) 547 return false; 548 549 return arch_pte_access_permitted(pte_val(pte), write, 0); 550 } 551 552 static inline bool pte_user_accessible_page(pte_t pte, unsigned long addr) 553 { 554 return pte_present(pte) && pte_user(pte); 555 } 556 557 /* 558 * Conversion functions: convert a page and protection to a page entry, 559 * and a page entry and page directory to the page they refer to. 560 * 561 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 562 * long for now. 563 */ 564 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 565 { 566 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 567 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 568 569 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 570 } 571 572 /* Generic modifiers for PTE bits */ 573 static inline pte_t pte_wrprotect(pte_t pte) 574 { 575 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 576 } 577 578 static inline pte_t pte_exprotect(pte_t pte) 579 { 580 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 581 } 582 583 static inline pte_t pte_mkclean(pte_t pte) 584 { 585 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 586 } 587 588 static inline pte_t pte_mkold(pte_t pte) 589 { 590 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 591 } 592 593 static inline pte_t pte_mkexec(pte_t pte) 594 { 595 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 596 } 597 598 static inline pte_t pte_mkwrite_novma(pte_t pte) 599 { 600 /* 601 * write implies read, hence set both 602 */ 603 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 604 } 605 606 static inline pte_t pte_mkdirty(pte_t pte) 607 { 608 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 609 } 610 611 static inline pte_t pte_mkyoung(pte_t pte) 612 { 613 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 614 } 615 616 static inline pte_t pte_mkspecial(pte_t pte) 617 { 618 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 619 } 620 621 static inline pte_t pte_mkhuge(pte_t pte) 622 { 623 return pte; 624 } 625 626 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 627 { 628 /* FIXME!! check whether this need to be a conditional */ 629 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 630 cpu_to_be64(pgprot_val(newprot))); 631 } 632 633 /* Encode and de-code a swap entry */ 634 #define MAX_SWAPFILES_CHECK() do { \ 635 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 636 /* \ 637 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 638 * We filter HPTEFLAGS on set_pte. \ 639 */ \ 640 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ 641 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 642 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ 643 } while (0) 644 645 #define SWP_TYPE_BITS 5 646 #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) 647 #define __swp_type(x) ((x).val & SWP_TYPE_MASK) 648 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 649 #define __swp_entry(type, offset) ((swp_entry_t) { \ 650 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 651 /* 652 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 653 * swap type and offset we get from swap and convert that to pte to find a 654 * matching pte in linux page table. 655 * Clear bits not found in swap entries here. 656 */ 657 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 658 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 659 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 660 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 661 662 #ifdef CONFIG_MEM_SOFT_DIRTY 663 #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY 664 #else 665 #define _PAGE_SWP_SOFT_DIRTY 0UL 666 #endif /* CONFIG_MEM_SOFT_DIRTY */ 667 668 #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT 669 670 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 671 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 672 { 673 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 674 } 675 676 static inline bool pte_swp_soft_dirty(pte_t pte) 677 { 678 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 679 } 680 681 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 682 { 683 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 684 } 685 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 686 687 static inline pte_t pte_swp_mkexclusive(pte_t pte) 688 { 689 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 690 } 691 692 static inline bool pte_swp_exclusive(pte_t pte) 693 { 694 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); 695 } 696 697 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 698 { 699 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); 700 } 701 702 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 703 { 704 /* 705 * This check for _PAGE_RWX and _PAGE_PRESENT bits 706 */ 707 if (access & ~ptev) 708 return false; 709 /* 710 * This check for access to privilege space 711 */ 712 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 713 return false; 714 715 return true; 716 } 717 /* 718 * Generic functions with hash/radix callbacks 719 */ 720 721 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 722 pte_t *ptep, pte_t entry, 723 unsigned long address, 724 int psize) 725 { 726 if (radix_enabled()) 727 return radix__ptep_set_access_flags(vma, ptep, entry, 728 address, psize); 729 return hash__ptep_set_access_flags(ptep, entry); 730 } 731 732 #define __HAVE_ARCH_PTE_SAME 733 static inline int pte_same(pte_t pte_a, pte_t pte_b) 734 { 735 if (radix_enabled()) 736 return radix__pte_same(pte_a, pte_b); 737 return hash__pte_same(pte_a, pte_b); 738 } 739 740 static inline int pte_none(pte_t pte) 741 { 742 if (radix_enabled()) 743 return radix__pte_none(pte); 744 return hash__pte_none(pte); 745 } 746 747 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 748 pte_t *ptep, pte_t pte, int percpu) 749 { 750 751 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 752 /* 753 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 754 * in all the callers. 755 */ 756 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 757 758 if (radix_enabled()) 759 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 760 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 761 } 762 763 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 764 765 #define pgprot_noncached pgprot_noncached 766 static inline pgprot_t pgprot_noncached(pgprot_t prot) 767 { 768 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 769 _PAGE_NON_IDEMPOTENT); 770 } 771 772 #define pgprot_noncached_wc pgprot_noncached_wc 773 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 774 { 775 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 776 _PAGE_TOLERANT); 777 } 778 779 #define pgprot_cached pgprot_cached 780 static inline pgprot_t pgprot_cached(pgprot_t prot) 781 { 782 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 783 } 784 785 #define pgprot_writecombine pgprot_writecombine 786 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 787 { 788 return pgprot_noncached_wc(prot); 789 } 790 /* 791 * check a pte mapping have cache inhibited property 792 */ 793 static inline bool pte_ci(pte_t pte) 794 { 795 __be64 pte_v = pte_raw(pte); 796 797 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 798 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 799 return true; 800 return false; 801 } 802 803 static inline void pmd_clear(pmd_t *pmdp) 804 { 805 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 806 /* 807 * Don't use this if we can possibly have a hash page table 808 * entry mapping this. 809 */ 810 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 811 } 812 *pmdp = __pmd(0); 813 } 814 815 static inline int pmd_none(pmd_t pmd) 816 { 817 return !pmd_raw(pmd); 818 } 819 820 static inline int pmd_present(pmd_t pmd) 821 { 822 /* 823 * A pmd is considerent present if _PAGE_PRESENT is set. 824 * We also need to consider the pmd present which is marked 825 * invalid during a split. Hence we look for _PAGE_INVALID 826 * if we find _PAGE_PRESENT cleared. 827 */ 828 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 829 return true; 830 831 return false; 832 } 833 834 static inline int pmd_is_serializing(pmd_t pmd) 835 { 836 /* 837 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 838 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 839 * 840 * This condition may also occur when flushing a pmd while flushing 841 * it (see ptep_modify_prot_start), so callers must ensure this 842 * case is fine as well. 843 */ 844 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 845 cpu_to_be64(_PAGE_INVALID)) 846 return true; 847 848 return false; 849 } 850 851 static inline int pmd_bad(pmd_t pmd) 852 { 853 if (radix_enabled()) 854 return radix__pmd_bad(pmd); 855 return hash__pmd_bad(pmd); 856 } 857 858 static inline void pud_clear(pud_t *pudp) 859 { 860 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 861 /* 862 * Don't use this if we can possibly have a hash page table 863 * entry mapping this. 864 */ 865 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 866 } 867 *pudp = __pud(0); 868 } 869 870 static inline int pud_none(pud_t pud) 871 { 872 return !pud_raw(pud); 873 } 874 875 static inline int pud_present(pud_t pud) 876 { 877 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 878 } 879 880 extern struct page *pud_page(pud_t pud); 881 extern struct page *pmd_page(pmd_t pmd); 882 static inline pte_t pud_pte(pud_t pud) 883 { 884 return __pte_raw(pud_raw(pud)); 885 } 886 887 static inline pud_t pte_pud(pte_t pte) 888 { 889 return __pud_raw(pte_raw(pte)); 890 } 891 892 static inline pte_t *pudp_ptep(pud_t *pud) 893 { 894 return (pte_t *)pud; 895 } 896 897 #define pud_pfn(pud) pte_pfn(pud_pte(pud)) 898 #define pud_dirty(pud) pte_dirty(pud_pte(pud)) 899 #define pud_young(pud) pte_young(pud_pte(pud)) 900 #define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud))) 901 #define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud))) 902 #define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud))) 903 #define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud))) 904 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) 905 #define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud))) 906 #define pud_write(pud) pte_write(pud_pte(pud)) 907 908 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 909 #define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud)) 910 #define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud))) 911 #define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud))) 912 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 913 914 static inline int pud_bad(pud_t pud) 915 { 916 if (radix_enabled()) 917 return radix__pud_bad(pud); 918 return hash__pud_bad(pud); 919 } 920 921 #define pud_access_permitted pud_access_permitted 922 static inline bool pud_access_permitted(pud_t pud, bool write) 923 { 924 return pte_access_permitted(pud_pte(pud), write); 925 } 926 927 #define pud_user_accessible_page pud_user_accessible_page 928 static inline bool pud_user_accessible_page(pud_t pud, unsigned long addr) 929 { 930 return pud_leaf(pud) && pte_user_accessible_page(pud_pte(pud), addr); 931 } 932 933 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 934 static inline __be64 p4d_raw(p4d_t x) 935 { 936 return pgd_raw(x.pgd); 937 } 938 939 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 940 941 static inline void p4d_clear(p4d_t *p4dp) 942 { 943 *p4dp = __p4d(0); 944 } 945 946 static inline int p4d_none(p4d_t p4d) 947 { 948 return !p4d_raw(p4d); 949 } 950 951 static inline int p4d_present(p4d_t p4d) 952 { 953 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 954 } 955 956 static inline pte_t p4d_pte(p4d_t p4d) 957 { 958 return __pte_raw(p4d_raw(p4d)); 959 } 960 961 static inline p4d_t pte_p4d(pte_t pte) 962 { 963 return __p4d_raw(pte_raw(pte)); 964 } 965 966 static inline int p4d_bad(p4d_t p4d) 967 { 968 if (radix_enabled()) 969 return radix__p4d_bad(p4d); 970 return hash__p4d_bad(p4d); 971 } 972 973 #define p4d_access_permitted p4d_access_permitted 974 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 975 { 976 return pte_access_permitted(p4d_pte(p4d), write); 977 } 978 979 extern struct page *p4d_page(p4d_t p4d); 980 981 /* Pointers in the page table tree are physical addresses */ 982 #define __pgtable_ptr_val(ptr) __pa(ptr) 983 984 static inline pud_t *p4d_pgtable(p4d_t p4d) 985 { 986 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); 987 } 988 989 static inline pmd_t *pud_pgtable(pud_t pud) 990 { 991 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); 992 } 993 994 #define pmd_ERROR(e) \ 995 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 996 #define pud_ERROR(e) \ 997 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 998 #define pgd_ERROR(e) \ 999 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1000 1001 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1002 { 1003 if (radix_enabled()) { 1004 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1005 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1006 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1007 #endif 1008 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1009 } 1010 return hash__map_kernel_page(ea, pa, prot); 1011 } 1012 1013 void unmap_kernel_page(unsigned long va); 1014 1015 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1016 unsigned long page_size, 1017 unsigned long phys) 1018 { 1019 if (radix_enabled()) 1020 return radix__vmemmap_create_mapping(start, page_size, phys); 1021 return hash__vmemmap_create_mapping(start, page_size, phys); 1022 } 1023 1024 #ifdef CONFIG_MEMORY_HOTPLUG 1025 static inline void vmemmap_remove_mapping(unsigned long start, 1026 unsigned long page_size) 1027 { 1028 if (radix_enabled()) 1029 return radix__vmemmap_remove_mapping(start, page_size); 1030 return hash__vmemmap_remove_mapping(start, page_size); 1031 } 1032 #endif 1033 1034 static inline pte_t pmd_pte(pmd_t pmd) 1035 { 1036 return __pte_raw(pmd_raw(pmd)); 1037 } 1038 1039 static inline pmd_t pte_pmd(pte_t pte) 1040 { 1041 return __pmd_raw(pte_raw(pte)); 1042 } 1043 1044 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1045 { 1046 return (pte_t *)pmd; 1047 } 1048 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1049 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1050 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1051 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1052 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1053 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1054 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1055 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1056 #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) 1057 1058 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1059 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1060 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1061 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1062 1063 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1064 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1065 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1066 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1067 #endif 1068 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1069 1070 #ifdef CONFIG_NUMA_BALANCING 1071 static inline int pmd_protnone(pmd_t pmd) 1072 { 1073 return pte_protnone(pmd_pte(pmd)); 1074 } 1075 #endif /* CONFIG_NUMA_BALANCING */ 1076 1077 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1078 1079 #define pmd_access_permitted pmd_access_permitted 1080 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1081 { 1082 /* 1083 * pmdp_invalidate sets this combination (which is not caught by 1084 * !pte_present() check in pte_access_permitted), to prevent 1085 * lock-free lookups, as part of the serialize_against_pte_lookup() 1086 * synchronisation. 1087 * 1088 * This also catches the case where the PTE's hardware PRESENT bit is 1089 * cleared while TLB is flushed, which is suboptimal but should not 1090 * be frequent. 1091 */ 1092 if (pmd_is_serializing(pmd)) 1093 return false; 1094 1095 return pte_access_permitted(pmd_pte(pmd), write); 1096 } 1097 1098 #define pmd_user_accessible_page pmd_user_accessible_page 1099 static inline bool pmd_user_accessible_page(pmd_t pmd, unsigned long addr) 1100 { 1101 return pmd_leaf(pmd) && pte_user_accessible_page(pmd_pte(pmd), addr); 1102 } 1103 1104 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1105 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1106 extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot); 1107 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1108 extern pud_t pud_modify(pud_t pud, pgprot_t newprot); 1109 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1110 pmd_t *pmdp, pmd_t pmd); 1111 extern void set_pud_at(struct mm_struct *mm, unsigned long addr, 1112 pud_t *pudp, pud_t pud); 1113 1114 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1115 unsigned long addr, pmd_t *pmd) 1116 { 1117 } 1118 1119 static inline void update_mmu_cache_pud(struct vm_area_struct *vma, 1120 unsigned long addr, pud_t *pud) 1121 { 1122 } 1123 1124 extern int hash__has_transparent_hugepage(void); 1125 static inline int has_transparent_hugepage(void) 1126 { 1127 if (radix_enabled()) 1128 return radix__has_transparent_hugepage(); 1129 return hash__has_transparent_hugepage(); 1130 } 1131 #define has_transparent_hugepage has_transparent_hugepage 1132 1133 static inline int has_transparent_pud_hugepage(void) 1134 { 1135 if (radix_enabled()) 1136 return radix__has_transparent_pud_hugepage(); 1137 return 0; 1138 } 1139 #define has_transparent_pud_hugepage has_transparent_pud_hugepage 1140 1141 static inline unsigned long 1142 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1143 unsigned long clr, unsigned long set) 1144 { 1145 if (radix_enabled()) 1146 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1147 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1148 } 1149 1150 static inline unsigned long 1151 pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp, 1152 unsigned long clr, unsigned long set) 1153 { 1154 if (radix_enabled()) 1155 return radix__pud_hugepage_update(mm, addr, pudp, clr, set); 1156 BUG(); 1157 return pud_val(*pudp); 1158 } 1159 1160 /* 1161 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1162 * the below will work for radix too 1163 */ 1164 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1165 unsigned long addr, pmd_t *pmdp) 1166 { 1167 unsigned long old; 1168 1169 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1170 return 0; 1171 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1172 return ((old & _PAGE_ACCESSED) != 0); 1173 } 1174 1175 static inline int __pudp_test_and_clear_young(struct mm_struct *mm, 1176 unsigned long addr, pud_t *pudp) 1177 { 1178 unsigned long old; 1179 1180 if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1181 return 0; 1182 old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0); 1183 return ((old & _PAGE_ACCESSED) != 0); 1184 } 1185 1186 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1187 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1188 pmd_t *pmdp) 1189 { 1190 if (pmd_write(*pmdp)) 1191 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1192 } 1193 1194 #define __HAVE_ARCH_PUDP_SET_WRPROTECT 1195 static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1196 pud_t *pudp) 1197 { 1198 if (pud_write(*pudp)) 1199 pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0); 1200 } 1201 1202 /* 1203 * Only returns true for a THP. False for pmd migration entry. 1204 * We also need to return true when we come across a pte that 1205 * in between a thp split. While splitting THP, we mark the pmd 1206 * invalid (pmdp_invalidate()) before we set it with pte page 1207 * address. A pmd_trans_huge() check against a pmd entry during that time 1208 * should return true. 1209 * We should not call this on a hugetlb entry. We should check for HugeTLB 1210 * entry using vma->vm_flags 1211 * The page table walk rule is explained in Documentation/mm/transhuge.rst 1212 */ 1213 static inline int pmd_trans_huge(pmd_t pmd) 1214 { 1215 if (!pmd_present(pmd)) 1216 return false; 1217 1218 if (radix_enabled()) 1219 return radix__pmd_trans_huge(pmd); 1220 return hash__pmd_trans_huge(pmd); 1221 } 1222 1223 static inline int pud_trans_huge(pud_t pud) 1224 { 1225 if (!pud_present(pud)) 1226 return false; 1227 1228 if (radix_enabled()) 1229 return radix__pud_trans_huge(pud); 1230 return 0; 1231 } 1232 1233 1234 #define __HAVE_ARCH_PMD_SAME 1235 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1236 { 1237 if (radix_enabled()) 1238 return radix__pmd_same(pmd_a, pmd_b); 1239 return hash__pmd_same(pmd_a, pmd_b); 1240 } 1241 1242 #define pud_same pud_same 1243 static inline int pud_same(pud_t pud_a, pud_t pud_b) 1244 { 1245 if (radix_enabled()) 1246 return radix__pud_same(pud_a, pud_b); 1247 return hash__pud_same(pud_a, pud_b); 1248 } 1249 1250 1251 static inline pmd_t __pmd_mkhuge(pmd_t pmd) 1252 { 1253 if (radix_enabled()) 1254 return radix__pmd_mkhuge(pmd); 1255 return hash__pmd_mkhuge(pmd); 1256 } 1257 1258 static inline pud_t __pud_mkhuge(pud_t pud) 1259 { 1260 if (radix_enabled()) 1261 return radix__pud_mkhuge(pud); 1262 BUG(); 1263 return pud; 1264 } 1265 1266 /* 1267 * pfn_pmd return a pmd_t that can be used as pmd pte entry. 1268 */ 1269 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1270 { 1271 #ifdef CONFIG_DEBUG_VM 1272 if (radix_enabled()) 1273 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); 1274 else 1275 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != 1276 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); 1277 #endif 1278 return pmd; 1279 } 1280 1281 static inline pud_t pud_mkhuge(pud_t pud) 1282 { 1283 #ifdef CONFIG_DEBUG_VM 1284 if (radix_enabled()) 1285 WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0); 1286 else 1287 WARN_ON(1); 1288 #endif 1289 return pud; 1290 } 1291 1292 1293 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1294 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1295 unsigned long address, pmd_t *pmdp, 1296 pmd_t entry, int dirty); 1297 #define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS 1298 extern int pudp_set_access_flags(struct vm_area_struct *vma, 1299 unsigned long address, pud_t *pudp, 1300 pud_t entry, int dirty); 1301 1302 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1303 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1304 unsigned long address, pmd_t *pmdp); 1305 #define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG 1306 extern int pudp_test_and_clear_young(struct vm_area_struct *vma, 1307 unsigned long address, pud_t *pudp); 1308 1309 1310 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1311 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1312 unsigned long addr, pmd_t *pmdp) 1313 { 1314 pmd_t old_pmd; 1315 1316 if (radix_enabled()) { 1317 old_pmd = radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1318 } else { 1319 old_pmd = hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1320 } 1321 1322 page_table_check_pmd_clear(mm, addr, old_pmd); 1323 1324 return old_pmd; 1325 } 1326 1327 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR 1328 static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, 1329 unsigned long addr, pud_t *pudp) 1330 { 1331 pud_t old_pud; 1332 1333 if (radix_enabled()) { 1334 old_pud = radix__pudp_huge_get_and_clear(mm, addr, pudp); 1335 } else { 1336 BUG(); 1337 } 1338 1339 page_table_check_pud_clear(mm, addr, old_pud); 1340 1341 return old_pud; 1342 } 1343 1344 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1345 unsigned long address, pmd_t *pmdp) 1346 { 1347 if (radix_enabled()) 1348 return radix__pmdp_collapse_flush(vma, address, pmdp); 1349 return hash__pmdp_collapse_flush(vma, address, pmdp); 1350 } 1351 #define pmdp_collapse_flush pmdp_collapse_flush 1352 1353 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1354 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1355 unsigned long addr, 1356 pmd_t *pmdp, int full); 1357 1358 #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL 1359 pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, 1360 unsigned long addr, 1361 pud_t *pudp, int full); 1362 1363 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1364 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1365 pmd_t *pmdp, pgtable_t pgtable) 1366 { 1367 if (radix_enabled()) 1368 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1369 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1370 } 1371 1372 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1373 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1374 pmd_t *pmdp) 1375 { 1376 if (radix_enabled()) 1377 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1378 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1379 } 1380 1381 #define __HAVE_ARCH_PMDP_INVALIDATE 1382 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1383 pmd_t *pmdp); 1384 extern pud_t pudp_invalidate(struct vm_area_struct *vma, unsigned long address, 1385 pud_t *pudp); 1386 1387 #define pmd_move_must_withdraw pmd_move_must_withdraw 1388 struct spinlock; 1389 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1390 struct spinlock *old_pmd_ptl, 1391 struct vm_area_struct *vma); 1392 /* 1393 * Hash translation mode use the deposited table to store hash pte 1394 * slot information. 1395 */ 1396 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1397 static inline bool arch_needs_pgtable_deposit(void) 1398 { 1399 if (radix_enabled()) 1400 return false; 1401 return true; 1402 } 1403 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1404 1405 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1406 1407 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1408 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1409 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1410 pte_t *, pte_t, pte_t); 1411 1412 /* 1413 * Returns true for a R -> RW upgrade of pte 1414 */ 1415 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1416 { 1417 if (!(old_val & _PAGE_READ)) 1418 return false; 1419 1420 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1421 return true; 1422 1423 return false; 1424 } 1425 1426 #endif /* __ASSEMBLER__ */ 1427 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1428