1 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 2 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 4 #ifndef __ASSEMBLY__ 5 #include <linux/mmdebug.h> 6 #endif 7 /* 8 * Common bits between hash and Radix page table 9 */ 10 #define _PAGE_BIT_SWAP_TYPE 0 11 12 #define _PAGE_RO 0 13 14 #define _PAGE_EXEC 0x00001 /* execute permission */ 15 #define _PAGE_WRITE 0x00002 /* write access allowed */ 16 #define _PAGE_READ 0x00004 /* read access allowed */ 17 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 18 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 19 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 20 #define _PAGE_SAO 0x00010 /* Strong access order */ 21 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 22 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 23 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 24 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 25 /* 26 * Software bits 27 */ 28 #define _RPAGE_SW0 0x2000000000000000UL 29 #define _RPAGE_SW1 0x00800 30 #define _RPAGE_SW2 0x00400 31 #define _RPAGE_SW3 0x00200 32 #define _RPAGE_RSV1 0x1000000000000000UL 33 #define _RPAGE_RSV2 0x0800000000000000UL 34 #define _RPAGE_RSV3 0x0400000000000000UL 35 #define _RPAGE_RSV4 0x0200000000000000UL 36 37 #ifdef CONFIG_MEM_SOFT_DIRTY 38 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 39 #else 40 #define _PAGE_SOFT_DIRTY 0x00000 41 #endif 42 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 43 44 /* 45 * For P9 DD1 only, we need to track whether the pte's huge. 46 */ 47 #define _PAGE_LARGE _RPAGE_RSV1 48 49 50 #define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */ 51 #define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */ 52 /* 53 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 54 * Instead of fixing all of them, add an alternate define which 55 * maps CI pte mapping. 56 */ 57 #define _PAGE_NO_CACHE _PAGE_TOLERANT 58 /* 59 * We support 57 bit real address in pte. Clear everything above 57, and 60 * every thing below PAGE_SHIFT; 61 */ 62 #define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK)) 63 /* 64 * set of bits not changed in pmd_modify. Even though we have hash specific bits 65 * in here, on radix we expect them to be zero. 66 */ 67 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 68 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 69 _PAGE_SOFT_DIRTY) 70 /* 71 * user access blocked by key 72 */ 73 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 74 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 75 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 76 _PAGE_RW | _PAGE_EXEC) 77 /* 78 * No page size encoding in the linux PTE 79 */ 80 #define _PAGE_PSIZE 0 81 /* 82 * _PAGE_CHG_MASK masks of bits that are to be preserved across 83 * pgprot changes 84 */ 85 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 86 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 87 _PAGE_SOFT_DIRTY) 88 /* 89 * Mask of bits returned by pte_pgprot() 90 */ 91 #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ 92 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ 93 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ 94 _PAGE_SOFT_DIRTY) 95 /* 96 * We define 2 sets of base prot bits, one for basic pages (ie, 97 * cacheable kernel and user pages) and one for non cacheable 98 * pages. We always set _PAGE_COHERENT when SMP is enabled or 99 * the processor might need it for DMA coherency. 100 */ 101 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) 102 #define _PAGE_BASE (_PAGE_BASE_NC) 103 104 /* Permission masks used to generate the __P and __S table, 105 * 106 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 107 * 108 * Write permissions imply read permissions for now (we could make write-only 109 * pages on BookE but we don't bother for now). Execute permission control is 110 * possible on platforms that define _PAGE_EXEC 111 * 112 * Note due to the way vm flags are laid out, the bits are XWR 113 */ 114 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 115 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 116 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 117 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 118 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 119 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 120 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 121 122 #define __P000 PAGE_NONE 123 #define __P001 PAGE_READONLY 124 #define __P010 PAGE_COPY 125 #define __P011 PAGE_COPY 126 #define __P100 PAGE_READONLY_X 127 #define __P101 PAGE_READONLY_X 128 #define __P110 PAGE_COPY_X 129 #define __P111 PAGE_COPY_X 130 131 #define __S000 PAGE_NONE 132 #define __S001 PAGE_READONLY 133 #define __S010 PAGE_SHARED 134 #define __S011 PAGE_SHARED 135 #define __S100 PAGE_READONLY_X 136 #define __S101 PAGE_READONLY_X 137 #define __S110 PAGE_SHARED_X 138 #define __S111 PAGE_SHARED_X 139 140 /* Permission masks used for kernel mappings */ 141 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 142 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 143 _PAGE_TOLERANT) 144 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 145 _PAGE_NON_IDEMPOTENT) 146 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 147 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 148 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 149 150 /* 151 * Protection used for kernel text. We want the debuggers to be able to 152 * set breakpoints anywhere, so don't write protect the kernel text 153 * on platforms where such control is possible. 154 */ 155 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 156 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 157 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 158 #else 159 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 160 #endif 161 162 /* Make modules code happy. We don't set RO yet */ 163 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 164 #define PAGE_AGP (PAGE_KERNEL_NC) 165 166 #ifndef __ASSEMBLY__ 167 /* 168 * page table defines 169 */ 170 extern unsigned long __pte_index_size; 171 extern unsigned long __pmd_index_size; 172 extern unsigned long __pud_index_size; 173 extern unsigned long __pgd_index_size; 174 extern unsigned long __pmd_cache_index; 175 #define PTE_INDEX_SIZE __pte_index_size 176 #define PMD_INDEX_SIZE __pmd_index_size 177 #define PUD_INDEX_SIZE __pud_index_size 178 #define PGD_INDEX_SIZE __pgd_index_size 179 #define PMD_CACHE_INDEX __pmd_cache_index 180 /* 181 * Because of use of pte fragments and THP, size of page table 182 * are not always derived out of index size above. 183 */ 184 extern unsigned long __pte_table_size; 185 extern unsigned long __pmd_table_size; 186 extern unsigned long __pud_table_size; 187 extern unsigned long __pgd_table_size; 188 #define PTE_TABLE_SIZE __pte_table_size 189 #define PMD_TABLE_SIZE __pmd_table_size 190 #define PUD_TABLE_SIZE __pud_table_size 191 #define PGD_TABLE_SIZE __pgd_table_size 192 193 extern unsigned long __pmd_val_bits; 194 extern unsigned long __pud_val_bits; 195 extern unsigned long __pgd_val_bits; 196 #define PMD_VAL_BITS __pmd_val_bits 197 #define PUD_VAL_BITS __pud_val_bits 198 #define PGD_VAL_BITS __pgd_val_bits 199 200 extern unsigned long __pte_frag_nr; 201 #define PTE_FRAG_NR __pte_frag_nr 202 extern unsigned long __pte_frag_size_shift; 203 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 204 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 205 /* 206 * Pgtable size used by swapper, init in asm code 207 */ 208 #define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE) 209 210 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 211 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 212 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 213 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 214 215 /* PMD_SHIFT determines what a second-level page table entry can map */ 216 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 217 #define PMD_SIZE (1UL << PMD_SHIFT) 218 #define PMD_MASK (~(PMD_SIZE-1)) 219 220 /* PUD_SHIFT determines what a third-level page table entry can map */ 221 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 222 #define PUD_SIZE (1UL << PUD_SHIFT) 223 #define PUD_MASK (~(PUD_SIZE-1)) 224 225 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 226 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 227 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 228 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 229 230 /* Bits to mask out from a PMD to get to the PTE page */ 231 #define PMD_MASKED_BITS 0xc0000000000000ffUL 232 /* Bits to mask out from a PUD to get to the PMD page */ 233 #define PUD_MASKED_BITS 0xc0000000000000ffUL 234 /* Bits to mask out from a PGD to get to the PUD page */ 235 #define PGD_MASKED_BITS 0xc0000000000000ffUL 236 237 extern unsigned long __vmalloc_start; 238 extern unsigned long __vmalloc_end; 239 #define VMALLOC_START __vmalloc_start 240 #define VMALLOC_END __vmalloc_end 241 242 extern unsigned long __kernel_virt_start; 243 extern unsigned long __kernel_virt_size; 244 #define KERN_VIRT_START __kernel_virt_start 245 #define KERN_VIRT_SIZE __kernel_virt_size 246 extern struct page *vmemmap; 247 extern unsigned long ioremap_bot; 248 extern unsigned long pci_io_base; 249 #endif /* __ASSEMBLY__ */ 250 251 #include <asm/book3s/64/hash.h> 252 #include <asm/book3s/64/radix.h> 253 254 #ifdef CONFIG_PPC_64K_PAGES 255 #include <asm/book3s/64/pgtable-64k.h> 256 #else 257 #include <asm/book3s/64/pgtable-4k.h> 258 #endif 259 260 #include <asm/barrier.h> 261 /* 262 * The second half of the kernel virtual space is used for IO mappings, 263 * it's itself carved into the PIO region (ISA and PHB IO space) and 264 * the ioremap space 265 * 266 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 267 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 268 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 269 */ 270 #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1)) 271 #define FULL_IO_SIZE 0x80000000ul 272 #define ISA_IO_BASE (KERN_IO_START) 273 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 274 #define PHB_IO_BASE (ISA_IO_END) 275 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 276 #define IOREMAP_BASE (PHB_IO_END) 277 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 278 279 /* Advertise special mapping type for AGP */ 280 #define HAVE_PAGE_AGP 281 282 /* Advertise support for _PAGE_SPECIAL */ 283 #define __HAVE_ARCH_PTE_SPECIAL 284 285 #ifndef __ASSEMBLY__ 286 287 /* 288 * This is the default implementation of various PTE accessors, it's 289 * used in all cases except Book3S with 64K pages where we have a 290 * concept of sub-pages 291 */ 292 #ifndef __real_pte 293 294 #define __real_pte(e,p) ((real_pte_t){(e)}) 295 #define __rpte_to_pte(r) ((r).pte) 296 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 297 298 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 299 do { \ 300 index = 0; \ 301 shift = mmu_psize_defs[psize].shift; \ 302 303 #define pte_iterate_hashed_end() } while(0) 304 305 /* 306 * We expect this to be called only for user addresses or kernel virtual 307 * addresses other than the linear mapping. 308 */ 309 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 310 311 #endif /* __real_pte */ 312 313 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 314 pte_t *ptep, unsigned long clr, 315 unsigned long set, int huge) 316 { 317 if (radix_enabled()) 318 return radix__pte_update(mm, addr, ptep, clr, set, huge); 319 return hash__pte_update(mm, addr, ptep, clr, set, huge); 320 } 321 /* 322 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 323 * We currently remove entries from the hashtable regardless of whether 324 * the entry was young or dirty. 325 * 326 * We should be more intelligent about this but for the moment we override 327 * these functions and force a tlb flush unconditionally 328 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 329 * function for both hash and radix. 330 */ 331 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 332 unsigned long addr, pte_t *ptep) 333 { 334 unsigned long old; 335 336 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 337 return 0; 338 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 339 return (old & _PAGE_ACCESSED) != 0; 340 } 341 342 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 343 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 344 ({ \ 345 int __r; \ 346 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 347 __r; \ 348 }) 349 350 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 351 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 352 pte_t *ptep) 353 { 354 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0) 355 return; 356 357 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 358 } 359 360 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 361 unsigned long addr, pte_t *ptep) 362 { 363 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0) 364 return; 365 366 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 367 } 368 369 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 370 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 371 unsigned long addr, pte_t *ptep) 372 { 373 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 374 return __pte(old); 375 } 376 377 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 378 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 379 unsigned long addr, 380 pte_t *ptep, int full) 381 { 382 if (full && radix_enabled()) { 383 /* 384 * Let's skip the DD1 style pte update here. We know that 385 * this is a full mm pte clear and hence can be sure there is 386 * no parallel set_pte. 387 */ 388 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 389 } 390 return ptep_get_and_clear(mm, addr, ptep); 391 } 392 393 394 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 395 pte_t * ptep) 396 { 397 pte_update(mm, addr, ptep, ~0UL, 0, 0); 398 } 399 400 static inline int pte_write(pte_t pte) 401 { 402 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 403 } 404 405 static inline int pte_dirty(pte_t pte) 406 { 407 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 408 } 409 410 static inline int pte_young(pte_t pte) 411 { 412 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 413 } 414 415 static inline int pte_special(pte_t pte) 416 { 417 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 418 } 419 420 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 421 422 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 423 static inline bool pte_soft_dirty(pte_t pte) 424 { 425 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 426 } 427 428 static inline pte_t pte_mksoft_dirty(pte_t pte) 429 { 430 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); 431 } 432 433 static inline pte_t pte_clear_soft_dirty(pte_t pte) 434 { 435 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); 436 } 437 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 438 439 #ifdef CONFIG_NUMA_BALANCING 440 static inline int pte_protnone(pte_t pte) 441 { 442 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 443 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 444 } 445 446 #define pte_mk_savedwrite pte_mk_savedwrite 447 static inline pte_t pte_mk_savedwrite(pte_t pte) 448 { 449 /* 450 * Used by Autonuma subsystem to preserve the write bit 451 * while marking the pte PROT_NONE. Only allow this 452 * on PROT_NONE pte 453 */ 454 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 455 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 456 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); 457 } 458 459 #define pte_clear_savedwrite pte_clear_savedwrite 460 static inline pte_t pte_clear_savedwrite(pte_t pte) 461 { 462 /* 463 * Used by KSM subsystem to make a protnone pte readonly. 464 */ 465 VM_BUG_ON(!pte_protnone(pte)); 466 return __pte(pte_val(pte) | _PAGE_PRIVILEGED); 467 } 468 469 #define pte_savedwrite pte_savedwrite 470 static inline bool pte_savedwrite(pte_t pte) 471 { 472 /* 473 * Saved write ptes are prot none ptes that doesn't have 474 * privileged bit sit. We mark prot none as one which has 475 * present and pviliged bit set and RWX cleared. To mark 476 * protnone which used to have _PAGE_WRITE set we clear 477 * the privileged bit. 478 */ 479 VM_BUG_ON(!pte_protnone(pte)); 480 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 481 } 482 #endif /* CONFIG_NUMA_BALANCING */ 483 484 static inline int pte_present(pte_t pte) 485 { 486 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); 487 } 488 /* 489 * Conversion functions: convert a page and protection to a page entry, 490 * and a page entry and page directory to the page they refer to. 491 * 492 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 493 * long for now. 494 */ 495 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 496 { 497 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | 498 pgprot_val(pgprot)); 499 } 500 501 static inline unsigned long pte_pfn(pte_t pte) 502 { 503 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 504 } 505 506 /* Generic modifiers for PTE bits */ 507 static inline pte_t pte_wrprotect(pte_t pte) 508 { 509 return __pte(pte_val(pte) & ~_PAGE_WRITE); 510 } 511 512 static inline pte_t pte_mkclean(pte_t pte) 513 { 514 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 515 } 516 517 static inline pte_t pte_mkold(pte_t pte) 518 { 519 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 520 } 521 522 static inline pte_t pte_mkwrite(pte_t pte) 523 { 524 /* 525 * write implies read, hence set both 526 */ 527 return __pte(pte_val(pte) | _PAGE_RW); 528 } 529 530 static inline pte_t pte_mkdirty(pte_t pte) 531 { 532 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); 533 } 534 535 static inline pte_t pte_mkyoung(pte_t pte) 536 { 537 return __pte(pte_val(pte) | _PAGE_ACCESSED); 538 } 539 540 static inline pte_t pte_mkspecial(pte_t pte) 541 { 542 return __pte(pte_val(pte) | _PAGE_SPECIAL); 543 } 544 545 static inline pte_t pte_mkhuge(pte_t pte) 546 { 547 return pte; 548 } 549 550 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 551 { 552 /* FIXME!! check whether this need to be a conditional */ 553 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 554 } 555 556 static inline bool pte_user(pte_t pte) 557 { 558 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 559 } 560 561 /* Encode and de-code a swap entry */ 562 #define MAX_SWAPFILES_CHECK() do { \ 563 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 564 /* \ 565 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 566 * We filter HPTEFLAGS on set_pte. \ 567 */ \ 568 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 569 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 570 } while (0) 571 /* 572 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 573 */ 574 #define SWP_TYPE_BITS 5 575 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 576 & ((1UL << SWP_TYPE_BITS) - 1)) 577 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 578 #define __swp_entry(type, offset) ((swp_entry_t) { \ 579 ((type) << _PAGE_BIT_SWAP_TYPE) \ 580 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 581 /* 582 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 583 * swap type and offset we get from swap and convert that to pte to find a 584 * matching pte in linux page table. 585 * Clear bits not found in swap entries here. 586 */ 587 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 588 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 589 590 #ifdef CONFIG_MEM_SOFT_DIRTY 591 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 592 #else 593 #define _PAGE_SWP_SOFT_DIRTY 0UL 594 #endif /* CONFIG_MEM_SOFT_DIRTY */ 595 596 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 597 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 598 { 599 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); 600 } 601 602 static inline bool pte_swp_soft_dirty(pte_t pte) 603 { 604 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 605 } 606 607 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 608 { 609 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); 610 } 611 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 612 613 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 614 { 615 /* 616 * This check for _PAGE_RWX and _PAGE_PRESENT bits 617 */ 618 if (access & ~ptev) 619 return false; 620 /* 621 * This check for access to privilege space 622 */ 623 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 624 return false; 625 626 return true; 627 } 628 /* 629 * Generic functions with hash/radix callbacks 630 */ 631 632 static inline void __ptep_set_access_flags(struct mm_struct *mm, 633 pte_t *ptep, pte_t entry, 634 unsigned long address) 635 { 636 if (radix_enabled()) 637 return radix__ptep_set_access_flags(mm, ptep, entry, address); 638 return hash__ptep_set_access_flags(ptep, entry); 639 } 640 641 #define __HAVE_ARCH_PTE_SAME 642 static inline int pte_same(pte_t pte_a, pte_t pte_b) 643 { 644 if (radix_enabled()) 645 return radix__pte_same(pte_a, pte_b); 646 return hash__pte_same(pte_a, pte_b); 647 } 648 649 static inline int pte_none(pte_t pte) 650 { 651 if (radix_enabled()) 652 return radix__pte_none(pte); 653 return hash__pte_none(pte); 654 } 655 656 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 657 pte_t *ptep, pte_t pte, int percpu) 658 { 659 if (radix_enabled()) 660 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 661 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 662 } 663 664 #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 665 666 #define pgprot_noncached pgprot_noncached 667 static inline pgprot_t pgprot_noncached(pgprot_t prot) 668 { 669 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 670 _PAGE_NON_IDEMPOTENT); 671 } 672 673 #define pgprot_noncached_wc pgprot_noncached_wc 674 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 675 { 676 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 677 _PAGE_TOLERANT); 678 } 679 680 #define pgprot_cached pgprot_cached 681 static inline pgprot_t pgprot_cached(pgprot_t prot) 682 { 683 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 684 } 685 686 #define pgprot_writecombine pgprot_writecombine 687 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 688 { 689 return pgprot_noncached_wc(prot); 690 } 691 /* 692 * check a pte mapping have cache inhibited property 693 */ 694 static inline bool pte_ci(pte_t pte) 695 { 696 unsigned long pte_v = pte_val(pte); 697 698 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || 699 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) 700 return true; 701 return false; 702 } 703 704 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 705 { 706 *pmdp = __pmd(val); 707 } 708 709 static inline void pmd_clear(pmd_t *pmdp) 710 { 711 *pmdp = __pmd(0); 712 } 713 714 static inline int pmd_none(pmd_t pmd) 715 { 716 return !pmd_raw(pmd); 717 } 718 719 static inline int pmd_present(pmd_t pmd) 720 { 721 722 return !pmd_none(pmd); 723 } 724 725 static inline int pmd_bad(pmd_t pmd) 726 { 727 if (radix_enabled()) 728 return radix__pmd_bad(pmd); 729 return hash__pmd_bad(pmd); 730 } 731 732 static inline void pud_set(pud_t *pudp, unsigned long val) 733 { 734 *pudp = __pud(val); 735 } 736 737 static inline void pud_clear(pud_t *pudp) 738 { 739 *pudp = __pud(0); 740 } 741 742 static inline int pud_none(pud_t pud) 743 { 744 return !pud_raw(pud); 745 } 746 747 static inline int pud_present(pud_t pud) 748 { 749 return !pud_none(pud); 750 } 751 752 extern struct page *pud_page(pud_t pud); 753 extern struct page *pmd_page(pmd_t pmd); 754 static inline pte_t pud_pte(pud_t pud) 755 { 756 return __pte_raw(pud_raw(pud)); 757 } 758 759 static inline pud_t pte_pud(pte_t pte) 760 { 761 return __pud_raw(pte_raw(pte)); 762 } 763 #define pud_write(pud) pte_write(pud_pte(pud)) 764 765 static inline int pud_bad(pud_t pud) 766 { 767 if (radix_enabled()) 768 return radix__pud_bad(pud); 769 return hash__pud_bad(pud); 770 } 771 772 773 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 774 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 775 { 776 *pgdp = __pgd(val); 777 } 778 779 static inline void pgd_clear(pgd_t *pgdp) 780 { 781 *pgdp = __pgd(0); 782 } 783 784 static inline int pgd_none(pgd_t pgd) 785 { 786 return !pgd_raw(pgd); 787 } 788 789 static inline int pgd_present(pgd_t pgd) 790 { 791 return !pgd_none(pgd); 792 } 793 794 static inline pte_t pgd_pte(pgd_t pgd) 795 { 796 return __pte_raw(pgd_raw(pgd)); 797 } 798 799 static inline pgd_t pte_pgd(pte_t pte) 800 { 801 return __pgd_raw(pte_raw(pte)); 802 } 803 804 static inline int pgd_bad(pgd_t pgd) 805 { 806 if (radix_enabled()) 807 return radix__pgd_bad(pgd); 808 return hash__pgd_bad(pgd); 809 } 810 811 extern struct page *pgd_page(pgd_t pgd); 812 813 /* Pointers in the page table tree are physical addresses */ 814 #define __pgtable_ptr_val(ptr) __pa(ptr) 815 816 #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) 817 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 818 #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) 819 820 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 821 #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) 822 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) 823 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) 824 825 /* 826 * Find an entry in a page-table-directory. We combine the address region 827 * (the high order N bits) and the pgd portion of the address. 828 */ 829 830 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 831 832 #define pud_offset(pgdp, addr) \ 833 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) 834 #define pmd_offset(pudp,addr) \ 835 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) 836 #define pte_offset_kernel(dir,addr) \ 837 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) 838 839 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 840 #define pte_unmap(pte) do { } while(0) 841 842 /* to find an entry in a kernel page-table-directory */ 843 /* This now only contains the vmalloc pages */ 844 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 845 846 #define pte_ERROR(e) \ 847 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 848 #define pmd_ERROR(e) \ 849 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 850 #define pud_ERROR(e) \ 851 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 852 #define pgd_ERROR(e) \ 853 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 854 855 static inline int map_kernel_page(unsigned long ea, unsigned long pa, 856 unsigned long flags) 857 { 858 if (radix_enabled()) { 859 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 860 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 861 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 862 #endif 863 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); 864 } 865 return hash__map_kernel_page(ea, pa, flags); 866 } 867 868 static inline int __meminit vmemmap_create_mapping(unsigned long start, 869 unsigned long page_size, 870 unsigned long phys) 871 { 872 if (radix_enabled()) 873 return radix__vmemmap_create_mapping(start, page_size, phys); 874 return hash__vmemmap_create_mapping(start, page_size, phys); 875 } 876 877 #ifdef CONFIG_MEMORY_HOTPLUG 878 static inline void vmemmap_remove_mapping(unsigned long start, 879 unsigned long page_size) 880 { 881 if (radix_enabled()) 882 return radix__vmemmap_remove_mapping(start, page_size); 883 return hash__vmemmap_remove_mapping(start, page_size); 884 } 885 #endif 886 struct page *realmode_pfn_to_page(unsigned long pfn); 887 888 static inline pte_t pmd_pte(pmd_t pmd) 889 { 890 return __pte_raw(pmd_raw(pmd)); 891 } 892 893 static inline pmd_t pte_pmd(pte_t pte) 894 { 895 return __pmd_raw(pte_raw(pte)); 896 } 897 898 static inline pte_t *pmdp_ptep(pmd_t *pmd) 899 { 900 return (pte_t *)pmd; 901 } 902 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 903 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 904 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 905 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 906 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 907 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 908 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 909 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 910 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 911 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 912 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 913 914 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 915 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 916 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 917 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 918 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 919 920 #ifdef CONFIG_NUMA_BALANCING 921 static inline int pmd_protnone(pmd_t pmd) 922 { 923 return pte_protnone(pmd_pte(pmd)); 924 } 925 #endif /* CONFIG_NUMA_BALANCING */ 926 927 #define __HAVE_ARCH_PMD_WRITE 928 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 929 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 930 931 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 932 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 933 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 934 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 935 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 936 pmd_t *pmdp, pmd_t pmd); 937 extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, 938 pmd_t *pmd); 939 extern int hash__has_transparent_hugepage(void); 940 static inline int has_transparent_hugepage(void) 941 { 942 if (radix_enabled()) 943 return radix__has_transparent_hugepage(); 944 return hash__has_transparent_hugepage(); 945 } 946 #define has_transparent_hugepage has_transparent_hugepage 947 948 static inline unsigned long 949 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 950 unsigned long clr, unsigned long set) 951 { 952 if (radix_enabled()) 953 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 954 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 955 } 956 957 static inline int pmd_large(pmd_t pmd) 958 { 959 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 960 } 961 962 static inline pmd_t pmd_mknotpresent(pmd_t pmd) 963 { 964 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); 965 } 966 /* 967 * For radix we should always find H_PAGE_HASHPTE zero. Hence 968 * the below will work for radix too 969 */ 970 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 971 unsigned long addr, pmd_t *pmdp) 972 { 973 unsigned long old; 974 975 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 976 return 0; 977 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 978 return ((old & _PAGE_ACCESSED) != 0); 979 } 980 981 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 982 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 983 pmd_t *pmdp) 984 { 985 986 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_WRITE)) == 0) 987 return; 988 989 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 990 } 991 992 static inline int pmd_trans_huge(pmd_t pmd) 993 { 994 if (radix_enabled()) 995 return radix__pmd_trans_huge(pmd); 996 return hash__pmd_trans_huge(pmd); 997 } 998 999 #define __HAVE_ARCH_PMD_SAME 1000 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1001 { 1002 if (radix_enabled()) 1003 return radix__pmd_same(pmd_a, pmd_b); 1004 return hash__pmd_same(pmd_a, pmd_b); 1005 } 1006 1007 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1008 { 1009 if (radix_enabled()) 1010 return radix__pmd_mkhuge(pmd); 1011 return hash__pmd_mkhuge(pmd); 1012 } 1013 1014 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1015 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1016 unsigned long address, pmd_t *pmdp, 1017 pmd_t entry, int dirty); 1018 1019 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1020 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1021 unsigned long address, pmd_t *pmdp); 1022 1023 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1024 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1025 unsigned long addr, pmd_t *pmdp) 1026 { 1027 if (radix_enabled()) 1028 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1029 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1030 } 1031 1032 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1033 unsigned long address, pmd_t *pmdp) 1034 { 1035 if (radix_enabled()) 1036 return radix__pmdp_collapse_flush(vma, address, pmdp); 1037 return hash__pmdp_collapse_flush(vma, address, pmdp); 1038 } 1039 #define pmdp_collapse_flush pmdp_collapse_flush 1040 1041 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1042 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1043 pmd_t *pmdp, pgtable_t pgtable) 1044 { 1045 if (radix_enabled()) 1046 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1047 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1048 } 1049 1050 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1051 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1052 pmd_t *pmdp) 1053 { 1054 if (radix_enabled()) 1055 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1056 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1057 } 1058 1059 #define __HAVE_ARCH_PMDP_INVALIDATE 1060 extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1061 pmd_t *pmdp); 1062 1063 #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE 1064 static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma, 1065 unsigned long address, pmd_t *pmdp) 1066 { 1067 if (radix_enabled()) 1068 return radix__pmdp_huge_split_prepare(vma, address, pmdp); 1069 return hash__pmdp_huge_split_prepare(vma, address, pmdp); 1070 } 1071 1072 #define pmd_move_must_withdraw pmd_move_must_withdraw 1073 struct spinlock; 1074 static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1075 struct spinlock *old_pmd_ptl, 1076 struct vm_area_struct *vma) 1077 { 1078 if (radix_enabled()) 1079 return false; 1080 /* 1081 * Archs like ppc64 use pgtable to store per pmd 1082 * specific information. So when we switch the pmd, 1083 * we should also withdraw and deposit the pgtable 1084 */ 1085 return true; 1086 } 1087 1088 1089 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1090 static inline bool arch_needs_pgtable_deposit(void) 1091 { 1092 if (radix_enabled()) 1093 return false; 1094 return true; 1095 } 1096 1097 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1098 #endif /* __ASSEMBLY__ */ 1099 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1100