1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 3 #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ 4 5 #include <asm-generic/pgtable-nop4d.h> 6 7 #ifndef __ASSEMBLY__ 8 #include <linux/mmdebug.h> 9 #include <linux/bug.h> 10 #endif 11 12 /* 13 * Common bits between hash and Radix page table 14 */ 15 #define _PAGE_BIT_SWAP_TYPE 0 16 17 #define _PAGE_EXEC 0x00001 /* execute permission */ 18 #define _PAGE_WRITE 0x00002 /* write access allowed */ 19 #define _PAGE_READ 0x00004 /* read access allowed */ 20 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 21 #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 22 #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ 23 #define _PAGE_SAO 0x00010 /* Strong access order */ 24 #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ 25 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ 26 #define _PAGE_DIRTY 0x00080 /* C: page changed */ 27 #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ 28 /* 29 * Software bits 30 */ 31 #define _RPAGE_SW0 0x2000000000000000UL 32 #define _RPAGE_SW1 0x00800 33 #define _RPAGE_SW2 0x00400 34 #define _RPAGE_SW3 0x00200 35 #define _RPAGE_RSV1 0x00040UL 36 37 #define _RPAGE_PKEY_BIT4 0x1000000000000000UL 38 #define _RPAGE_PKEY_BIT3 0x0800000000000000UL 39 #define _RPAGE_PKEY_BIT2 0x0400000000000000UL 40 #define _RPAGE_PKEY_BIT1 0x0200000000000000UL 41 #define _RPAGE_PKEY_BIT0 0x0100000000000000UL 42 43 #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ 44 #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ 45 /* 46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing 47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to 48 * differentiate between two use a SW field when invalidating. 49 * 50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags 51 * 52 * This is used only when _PAGE_PRESENT is cleared. 53 */ 54 #define _PAGE_INVALID _RPAGE_SW0 55 56 /* 57 * Top and bottom bits of RPN which can be used by hash 58 * translation mode, because we expect them to be zero 59 * otherwise. 60 */ 61 #define _RPAGE_RPN0 0x01000 62 #define _RPAGE_RPN1 0x02000 63 #define _RPAGE_RPN43 0x0080000000000000UL 64 #define _RPAGE_RPN42 0x0040000000000000UL 65 #define _RPAGE_RPN41 0x0020000000000000UL 66 67 /* Max physical address bit as per radix table */ 68 #define _RPAGE_PA_MAX 56 69 70 /* 71 * Max physical address bit we will use for now. 72 * 73 * This is mostly a hardware limitation and for now Power9 has 74 * a 51 bit limit. 75 * 76 * This is different from the number of physical bit required to address 77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. 78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum 79 * number of sections we can support (SECTIONS_SHIFT). 80 * 81 * This is different from Radix page table limitation above and 82 * should always be less than that. The limit is done such that 83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX 84 * for hash linux page table specific bits. 85 * 86 * In order to be compatible with future hardware generations we keep 87 * some offsets and limit this for now to 53 88 */ 89 #define _PAGE_PA_MAX 53 90 91 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ 92 #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ 93 #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ 94 95 /* 96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE 97 * Instead of fixing all of them, add an alternate define which 98 * maps CI pte mapping. 99 */ 100 #define _PAGE_NO_CACHE _PAGE_TOLERANT 101 /* 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side 103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX 104 * and every thing below PAGE_SHIFT; 105 */ 106 #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) 107 /* 108 * set of bits not changed in pmd_modify. Even though we have hash specific bits 109 * in here, on radix we expect them to be zero. 110 */ 111 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 112 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ 113 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 114 /* 115 * user access blocked by key 116 */ 117 #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) 118 #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) 119 #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ 120 _PAGE_RW | _PAGE_EXEC) 121 /* 122 * _PAGE_CHG_MASK masks of bits that are to be preserved across 123 * pgprot changes 124 */ 125 #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 126 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ 127 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) 128 129 /* 130 * We define 2 sets of base prot bits, one for basic pages (ie, 131 * cacheable kernel and user pages) and one for non cacheable 132 * pages. We always set _PAGE_COHERENT when SMP is enabled or 133 * the processor might need it for DMA coherency. 134 */ 135 #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 136 #define _PAGE_BASE (_PAGE_BASE_NC) 137 138 /* Permission masks used to generate the __P and __S table, 139 * 140 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h 141 * 142 * Write permissions imply read permissions for now (we could make write-only 143 * pages on BookE but we don't bother for now). Execute permission control is 144 * possible on platforms that define _PAGE_EXEC 145 */ 146 #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) 147 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) 148 #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) 149 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) 150 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 151 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) 152 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) 153 154 /* Permission masks used for kernel mappings */ 155 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 156 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 157 _PAGE_TOLERANT) 158 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ 159 _PAGE_NON_IDEMPOTENT) 160 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 161 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 162 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 163 164 /* 165 * Protection used for kernel text. We want the debuggers to be able to 166 * set breakpoints anywhere, so don't write protect the kernel text 167 * on platforms where such control is possible. 168 */ 169 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ 170 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) 171 #define PAGE_KERNEL_TEXT PAGE_KERNEL_X 172 #else 173 #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX 174 #endif 175 176 /* Make modules code happy. We don't set RO yet */ 177 #define PAGE_KERNEL_EXEC PAGE_KERNEL_X 178 #define PAGE_AGP (PAGE_KERNEL_NC) 179 180 #ifndef __ASSEMBLY__ 181 /* 182 * page table defines 183 */ 184 extern unsigned long __pte_index_size; 185 extern unsigned long __pmd_index_size; 186 extern unsigned long __pud_index_size; 187 extern unsigned long __pgd_index_size; 188 extern unsigned long __pud_cache_index; 189 #define PTE_INDEX_SIZE __pte_index_size 190 #define PMD_INDEX_SIZE __pmd_index_size 191 #define PUD_INDEX_SIZE __pud_index_size 192 #define PGD_INDEX_SIZE __pgd_index_size 193 /* pmd table use page table fragments */ 194 #define PMD_CACHE_INDEX 0 195 #define PUD_CACHE_INDEX __pud_cache_index 196 /* 197 * Because of use of pte fragments and THP, size of page table 198 * are not always derived out of index size above. 199 */ 200 extern unsigned long __pte_table_size; 201 extern unsigned long __pmd_table_size; 202 extern unsigned long __pud_table_size; 203 extern unsigned long __pgd_table_size; 204 #define PTE_TABLE_SIZE __pte_table_size 205 #define PMD_TABLE_SIZE __pmd_table_size 206 #define PUD_TABLE_SIZE __pud_table_size 207 #define PGD_TABLE_SIZE __pgd_table_size 208 209 extern unsigned long __pmd_val_bits; 210 extern unsigned long __pud_val_bits; 211 extern unsigned long __pgd_val_bits; 212 #define PMD_VAL_BITS __pmd_val_bits 213 #define PUD_VAL_BITS __pud_val_bits 214 #define PGD_VAL_BITS __pgd_val_bits 215 216 extern unsigned long __pte_frag_nr; 217 #define PTE_FRAG_NR __pte_frag_nr 218 extern unsigned long __pte_frag_size_shift; 219 #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift 220 #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) 221 222 extern unsigned long __pmd_frag_nr; 223 #define PMD_FRAG_NR __pmd_frag_nr 224 extern unsigned long __pmd_frag_size_shift; 225 #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift 226 #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) 227 228 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 229 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 230 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 231 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 232 233 /* PMD_SHIFT determines what a second-level page table entry can map */ 234 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 235 #define PMD_SIZE (1UL << PMD_SHIFT) 236 #define PMD_MASK (~(PMD_SIZE-1)) 237 238 /* PUD_SHIFT determines what a third-level page table entry can map */ 239 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 240 #define PUD_SIZE (1UL << PUD_SHIFT) 241 #define PUD_MASK (~(PUD_SIZE-1)) 242 243 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 244 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 245 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 246 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 247 248 /* Bits to mask out from a PMD to get to the PTE page */ 249 #define PMD_MASKED_BITS 0xc0000000000000ffUL 250 /* Bits to mask out from a PUD to get to the PMD page */ 251 #define PUD_MASKED_BITS 0xc0000000000000ffUL 252 /* Bits to mask out from a PGD to get to the PUD page */ 253 #define P4D_MASKED_BITS 0xc0000000000000ffUL 254 255 /* 256 * Used as an indicator for rcu callback functions 257 */ 258 enum pgtable_index { 259 PTE_INDEX = 0, 260 PMD_INDEX, 261 PUD_INDEX, 262 PGD_INDEX, 263 /* 264 * Below are used with 4k page size and hugetlb 265 */ 266 HTLB_16M_INDEX, 267 HTLB_16G_INDEX, 268 }; 269 270 extern unsigned long __vmalloc_start; 271 extern unsigned long __vmalloc_end; 272 #define VMALLOC_START __vmalloc_start 273 #define VMALLOC_END __vmalloc_end 274 275 static inline unsigned int ioremap_max_order(void) 276 { 277 if (radix_enabled()) 278 return PUD_SHIFT; 279 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ 280 } 281 #define IOREMAP_MAX_ORDER ioremap_max_order() 282 283 extern unsigned long __kernel_virt_start; 284 extern unsigned long __kernel_io_start; 285 extern unsigned long __kernel_io_end; 286 #define KERN_VIRT_START __kernel_virt_start 287 #define KERN_IO_START __kernel_io_start 288 #define KERN_IO_END __kernel_io_end 289 290 extern struct page *vmemmap; 291 extern unsigned long pci_io_base; 292 #endif /* __ASSEMBLY__ */ 293 294 #include <asm/book3s/64/hash.h> 295 #include <asm/book3s/64/radix.h> 296 297 #ifdef CONFIG_PPC_64K_PAGES 298 #include <asm/book3s/64/pgtable-64k.h> 299 #else 300 #include <asm/book3s/64/pgtable-4k.h> 301 #endif 302 303 #include <asm/barrier.h> 304 /* 305 * IO space itself carved into the PIO region (ISA and PHB IO space) and 306 * the ioremap space 307 * 308 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 309 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 310 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 311 */ 312 #define FULL_IO_SIZE 0x80000000ul 313 #define ISA_IO_BASE (KERN_IO_START) 314 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 315 #define PHB_IO_BASE (ISA_IO_END) 316 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 317 #define IOREMAP_BASE (PHB_IO_END) 318 #define IOREMAP_START (ioremap_bot) 319 #define IOREMAP_END (KERN_IO_END) 320 321 /* Advertise special mapping type for AGP */ 322 #define HAVE_PAGE_AGP 323 324 #ifndef __ASSEMBLY__ 325 326 /* 327 * This is the default implementation of various PTE accessors, it's 328 * used in all cases except Book3S with 64K pages where we have a 329 * concept of sub-pages 330 */ 331 #ifndef __real_pte 332 333 #define __real_pte(e, p, o) ((real_pte_t){(e)}) 334 #define __rpte_to_pte(r) ((r).pte) 335 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) 336 337 #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ 338 do { \ 339 index = 0; \ 340 shift = mmu_psize_defs[psize].shift; \ 341 342 #define pte_iterate_hashed_end() } while(0) 343 344 /* 345 * We expect this to be called only for user addresses or kernel virtual 346 * addresses other than the linear mapping. 347 */ 348 #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K 349 350 #endif /* __real_pte */ 351 352 static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, 353 pte_t *ptep, unsigned long clr, 354 unsigned long set, int huge) 355 { 356 if (radix_enabled()) 357 return radix__pte_update(mm, addr, ptep, clr, set, huge); 358 return hash__pte_update(mm, addr, ptep, clr, set, huge); 359 } 360 /* 361 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. 362 * We currently remove entries from the hashtable regardless of whether 363 * the entry was young or dirty. 364 * 365 * We should be more intelligent about this but for the moment we override 366 * these functions and force a tlb flush unconditionally 367 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same 368 * function for both hash and radix. 369 */ 370 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 371 unsigned long addr, pte_t *ptep) 372 { 373 unsigned long old; 374 375 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 376 return 0; 377 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 378 return (old & _PAGE_ACCESSED) != 0; 379 } 380 381 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 382 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 383 ({ \ 384 int __r; \ 385 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 386 __r; \ 387 }) 388 389 static inline int __pte_write(pte_t pte) 390 { 391 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); 392 } 393 394 #ifdef CONFIG_NUMA_BALANCING 395 #define pte_savedwrite pte_savedwrite 396 static inline bool pte_savedwrite(pte_t pte) 397 { 398 /* 399 * Saved write ptes are prot none ptes that doesn't have 400 * privileged bit sit. We mark prot none as one which has 401 * present and pviliged bit set and RWX cleared. To mark 402 * protnone which used to have _PAGE_WRITE set we clear 403 * the privileged bit. 404 */ 405 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); 406 } 407 #else 408 #define pte_savedwrite pte_savedwrite 409 static inline bool pte_savedwrite(pte_t pte) 410 { 411 return false; 412 } 413 #endif 414 415 static inline int pte_write(pte_t pte) 416 { 417 return __pte_write(pte) || pte_savedwrite(pte); 418 } 419 420 static inline int pte_read(pte_t pte) 421 { 422 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); 423 } 424 425 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 426 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 427 pte_t *ptep) 428 { 429 if (__pte_write(*ptep)) 430 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); 431 else if (unlikely(pte_savedwrite(*ptep))) 432 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); 433 } 434 435 #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT 436 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 437 unsigned long addr, pte_t *ptep) 438 { 439 /* 440 * We should not find protnone for hugetlb, but this complete the 441 * interface. 442 */ 443 if (__pte_write(*ptep)) 444 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); 445 else if (unlikely(pte_savedwrite(*ptep))) 446 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); 447 } 448 449 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 450 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 451 unsigned long addr, pte_t *ptep) 452 { 453 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 454 return __pte(old); 455 } 456 457 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL 458 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 459 unsigned long addr, 460 pte_t *ptep, int full) 461 { 462 if (full && radix_enabled()) { 463 /* 464 * We know that this is a full mm pte clear and 465 * hence can be sure there is no parallel set_pte. 466 */ 467 return radix__ptep_get_and_clear_full(mm, addr, ptep, full); 468 } 469 return ptep_get_and_clear(mm, addr, ptep); 470 } 471 472 473 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 474 pte_t * ptep) 475 { 476 pte_update(mm, addr, ptep, ~0UL, 0, 0); 477 } 478 479 static inline int pte_dirty(pte_t pte) 480 { 481 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); 482 } 483 484 static inline int pte_young(pte_t pte) 485 { 486 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); 487 } 488 489 static inline int pte_special(pte_t pte) 490 { 491 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); 492 } 493 494 static inline bool pte_exec(pte_t pte) 495 { 496 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); 497 } 498 499 500 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 501 static inline bool pte_soft_dirty(pte_t pte) 502 { 503 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); 504 } 505 506 static inline pte_t pte_mksoft_dirty(pte_t pte) 507 { 508 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); 509 } 510 511 static inline pte_t pte_clear_soft_dirty(pte_t pte) 512 { 513 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); 514 } 515 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 516 517 #ifdef CONFIG_NUMA_BALANCING 518 static inline int pte_protnone(pte_t pte) 519 { 520 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == 521 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 522 } 523 524 #define pte_mk_savedwrite pte_mk_savedwrite 525 static inline pte_t pte_mk_savedwrite(pte_t pte) 526 { 527 /* 528 * Used by Autonuma subsystem to preserve the write bit 529 * while marking the pte PROT_NONE. Only allow this 530 * on PROT_NONE pte 531 */ 532 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != 533 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); 534 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 535 } 536 537 #define pte_clear_savedwrite pte_clear_savedwrite 538 static inline pte_t pte_clear_savedwrite(pte_t pte) 539 { 540 /* 541 * Used by KSM subsystem to make a protnone pte readonly. 542 */ 543 VM_BUG_ON(!pte_protnone(pte)); 544 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 545 } 546 #else 547 #define pte_clear_savedwrite pte_clear_savedwrite 548 static inline pte_t pte_clear_savedwrite(pte_t pte) 549 { 550 VM_WARN_ON(1); 551 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 552 } 553 #endif /* CONFIG_NUMA_BALANCING */ 554 555 static inline bool pte_hw_valid(pte_t pte) 556 { 557 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == 558 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); 559 } 560 561 static inline int pte_present(pte_t pte) 562 { 563 /* 564 * A pte is considerent present if _PAGE_PRESENT is set. 565 * We also need to consider the pte present which is marked 566 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID 567 * if we find _PAGE_PRESENT cleared. 568 */ 569 570 if (pte_hw_valid(pte)) 571 return true; 572 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == 573 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); 574 } 575 576 #ifdef CONFIG_PPC_MEM_KEYS 577 extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); 578 #else 579 static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) 580 { 581 return true; 582 } 583 #endif /* CONFIG_PPC_MEM_KEYS */ 584 585 static inline bool pte_user(pte_t pte) 586 { 587 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); 588 } 589 590 #define pte_access_permitted pte_access_permitted 591 static inline bool pte_access_permitted(pte_t pte, bool write) 592 { 593 /* 594 * _PAGE_READ is needed for any access and will be 595 * cleared for PROT_NONE 596 */ 597 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 598 return false; 599 600 if (write && !pte_write(pte)) 601 return false; 602 603 return arch_pte_access_permitted(pte_val(pte), write, 0); 604 } 605 606 /* 607 * Conversion functions: convert a page and protection to a page entry, 608 * and a page entry and page directory to the page they refer to. 609 * 610 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 611 * long for now. 612 */ 613 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 614 { 615 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); 616 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); 617 618 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); 619 } 620 621 static inline unsigned long pte_pfn(pte_t pte) 622 { 623 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; 624 } 625 626 /* Generic modifiers for PTE bits */ 627 static inline pte_t pte_wrprotect(pte_t pte) 628 { 629 if (unlikely(pte_savedwrite(pte))) 630 return pte_clear_savedwrite(pte); 631 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); 632 } 633 634 static inline pte_t pte_exprotect(pte_t pte) 635 { 636 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); 637 } 638 639 static inline pte_t pte_mkclean(pte_t pte) 640 { 641 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); 642 } 643 644 static inline pte_t pte_mkold(pte_t pte) 645 { 646 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); 647 } 648 649 static inline pte_t pte_mkexec(pte_t pte) 650 { 651 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); 652 } 653 654 static inline pte_t pte_mkwrite(pte_t pte) 655 { 656 /* 657 * write implies read, hence set both 658 */ 659 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); 660 } 661 662 static inline pte_t pte_mkdirty(pte_t pte) 663 { 664 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); 665 } 666 667 static inline pte_t pte_mkyoung(pte_t pte) 668 { 669 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); 670 } 671 672 static inline pte_t pte_mkspecial(pte_t pte) 673 { 674 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); 675 } 676 677 static inline pte_t pte_mkhuge(pte_t pte) 678 { 679 return pte; 680 } 681 682 static inline pte_t pte_mkdevmap(pte_t pte) 683 { 684 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); 685 } 686 687 static inline pte_t pte_mkprivileged(pte_t pte) 688 { 689 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); 690 } 691 692 static inline pte_t pte_mkuser(pte_t pte) 693 { 694 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); 695 } 696 697 /* 698 * This is potentially called with a pmd as the argument, in which case it's not 699 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. 700 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software 701 * use in page directory entries (ie. non-ptes). 702 */ 703 static inline int pte_devmap(pte_t pte) 704 { 705 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); 706 707 return (pte_raw(pte) & mask) == mask; 708 } 709 710 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 711 { 712 /* FIXME!! check whether this need to be a conditional */ 713 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | 714 cpu_to_be64(pgprot_val(newprot))); 715 } 716 717 /* Encode and de-code a swap entry */ 718 #define MAX_SWAPFILES_CHECK() do { \ 719 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 720 /* \ 721 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 722 * We filter HPTEFLAGS on set_pte. \ 723 */ \ 724 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 725 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ 726 } while (0) 727 728 #define SWP_TYPE_BITS 5 729 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 730 & ((1UL << SWP_TYPE_BITS) - 1)) 731 #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) 732 #define __swp_entry(type, offset) ((swp_entry_t) { \ 733 ((type) << _PAGE_BIT_SWAP_TYPE) \ 734 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) 735 /* 736 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from 737 * swap type and offset we get from swap and convert that to pte to find a 738 * matching pte in linux page table. 739 * Clear bits not found in swap entries here. 740 */ 741 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) 742 #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) 743 #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) 744 #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) 745 746 #ifdef CONFIG_MEM_SOFT_DIRTY 747 #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) 748 #else 749 #define _PAGE_SWP_SOFT_DIRTY 0UL 750 #endif /* CONFIG_MEM_SOFT_DIRTY */ 751 752 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 753 static inline pte_t pte_swp_mksoft_dirty(pte_t pte) 754 { 755 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 756 } 757 758 static inline bool pte_swp_soft_dirty(pte_t pte) 759 { 760 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); 761 } 762 763 static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) 764 { 765 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); 766 } 767 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 768 769 static inline bool check_pte_access(unsigned long access, unsigned long ptev) 770 { 771 /* 772 * This check for _PAGE_RWX and _PAGE_PRESENT bits 773 */ 774 if (access & ~ptev) 775 return false; 776 /* 777 * This check for access to privilege space 778 */ 779 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) 780 return false; 781 782 return true; 783 } 784 /* 785 * Generic functions with hash/radix callbacks 786 */ 787 788 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 789 pte_t *ptep, pte_t entry, 790 unsigned long address, 791 int psize) 792 { 793 if (radix_enabled()) 794 return radix__ptep_set_access_flags(vma, ptep, entry, 795 address, psize); 796 return hash__ptep_set_access_flags(ptep, entry); 797 } 798 799 #define __HAVE_ARCH_PTE_SAME 800 static inline int pte_same(pte_t pte_a, pte_t pte_b) 801 { 802 if (radix_enabled()) 803 return radix__pte_same(pte_a, pte_b); 804 return hash__pte_same(pte_a, pte_b); 805 } 806 807 static inline int pte_none(pte_t pte) 808 { 809 if (radix_enabled()) 810 return radix__pte_none(pte); 811 return hash__pte_none(pte); 812 } 813 814 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 815 pte_t *ptep, pte_t pte, int percpu) 816 { 817 818 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); 819 /* 820 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE 821 * in all the callers. 822 */ 823 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); 824 825 if (radix_enabled()) 826 return radix__set_pte_at(mm, addr, ptep, pte, percpu); 827 return hash__set_pte_at(mm, addr, ptep, pte, percpu); 828 } 829 830 #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) 831 832 #define pgprot_noncached pgprot_noncached 833 static inline pgprot_t pgprot_noncached(pgprot_t prot) 834 { 835 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 836 _PAGE_NON_IDEMPOTENT); 837 } 838 839 #define pgprot_noncached_wc pgprot_noncached_wc 840 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) 841 { 842 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | 843 _PAGE_TOLERANT); 844 } 845 846 #define pgprot_cached pgprot_cached 847 static inline pgprot_t pgprot_cached(pgprot_t prot) 848 { 849 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); 850 } 851 852 #define pgprot_writecombine pgprot_writecombine 853 static inline pgprot_t pgprot_writecombine(pgprot_t prot) 854 { 855 return pgprot_noncached_wc(prot); 856 } 857 /* 858 * check a pte mapping have cache inhibited property 859 */ 860 static inline bool pte_ci(pte_t pte) 861 { 862 __be64 pte_v = pte_raw(pte); 863 864 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || 865 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) 866 return true; 867 return false; 868 } 869 870 static inline void pmd_clear(pmd_t *pmdp) 871 { 872 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 873 /* 874 * Don't use this if we can possibly have a hash page table 875 * entry mapping this. 876 */ 877 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 878 } 879 *pmdp = __pmd(0); 880 } 881 882 static inline int pmd_none(pmd_t pmd) 883 { 884 return !pmd_raw(pmd); 885 } 886 887 static inline int pmd_present(pmd_t pmd) 888 { 889 /* 890 * A pmd is considerent present if _PAGE_PRESENT is set. 891 * We also need to consider the pmd present which is marked 892 * invalid during a split. Hence we look for _PAGE_INVALID 893 * if we find _PAGE_PRESENT cleared. 894 */ 895 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) 896 return true; 897 898 return false; 899 } 900 901 static inline int pmd_is_serializing(pmd_t pmd) 902 { 903 /* 904 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear 905 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). 906 * 907 * This condition may also occur when flushing a pmd while flushing 908 * it (see ptep_modify_prot_start), so callers must ensure this 909 * case is fine as well. 910 */ 911 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == 912 cpu_to_be64(_PAGE_INVALID)) 913 return true; 914 915 return false; 916 } 917 918 static inline int pmd_bad(pmd_t pmd) 919 { 920 if (radix_enabled()) 921 return radix__pmd_bad(pmd); 922 return hash__pmd_bad(pmd); 923 } 924 925 static inline void pud_clear(pud_t *pudp) 926 { 927 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { 928 /* 929 * Don't use this if we can possibly have a hash page table 930 * entry mapping this. 931 */ 932 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); 933 } 934 *pudp = __pud(0); 935 } 936 937 static inline int pud_none(pud_t pud) 938 { 939 return !pud_raw(pud); 940 } 941 942 static inline int pud_present(pud_t pud) 943 { 944 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); 945 } 946 947 extern struct page *pud_page(pud_t pud); 948 extern struct page *pmd_page(pmd_t pmd); 949 static inline pte_t pud_pte(pud_t pud) 950 { 951 return __pte_raw(pud_raw(pud)); 952 } 953 954 static inline pud_t pte_pud(pte_t pte) 955 { 956 return __pud_raw(pte_raw(pte)); 957 } 958 #define pud_write(pud) pte_write(pud_pte(pud)) 959 960 static inline int pud_bad(pud_t pud) 961 { 962 if (radix_enabled()) 963 return radix__pud_bad(pud); 964 return hash__pud_bad(pud); 965 } 966 967 #define pud_access_permitted pud_access_permitted 968 static inline bool pud_access_permitted(pud_t pud, bool write) 969 { 970 return pte_access_permitted(pud_pte(pud), write); 971 } 972 973 #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) 974 static inline __be64 p4d_raw(p4d_t x) 975 { 976 return pgd_raw(x.pgd); 977 } 978 979 #define p4d_write(p4d) pte_write(p4d_pte(p4d)) 980 981 static inline void p4d_clear(p4d_t *p4dp) 982 { 983 *p4dp = __p4d(0); 984 } 985 986 static inline int p4d_none(p4d_t p4d) 987 { 988 return !p4d_raw(p4d); 989 } 990 991 static inline int p4d_present(p4d_t p4d) 992 { 993 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); 994 } 995 996 static inline pte_t p4d_pte(p4d_t p4d) 997 { 998 return __pte_raw(p4d_raw(p4d)); 999 } 1000 1001 static inline p4d_t pte_p4d(pte_t pte) 1002 { 1003 return __p4d_raw(pte_raw(pte)); 1004 } 1005 1006 static inline int p4d_bad(p4d_t p4d) 1007 { 1008 if (radix_enabled()) 1009 return radix__p4d_bad(p4d); 1010 return hash__p4d_bad(p4d); 1011 } 1012 1013 #define p4d_access_permitted p4d_access_permitted 1014 static inline bool p4d_access_permitted(p4d_t p4d, bool write) 1015 { 1016 return pte_access_permitted(p4d_pte(p4d), write); 1017 } 1018 1019 extern struct page *p4d_page(p4d_t p4d); 1020 1021 /* Pointers in the page table tree are physical addresses */ 1022 #define __pgtable_ptr_val(ptr) __pa(ptr) 1023 1024 #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) 1025 #define p4d_page_vaddr(p4d) __va(p4d_val(p4d) & ~P4D_MASKED_BITS) 1026 1027 #define pte_ERROR(e) \ 1028 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 1029 #define pmd_ERROR(e) \ 1030 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 1031 #define pud_ERROR(e) \ 1032 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 1033 #define pgd_ERROR(e) \ 1034 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 1035 1036 static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) 1037 { 1038 if (radix_enabled()) { 1039 #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) 1040 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; 1041 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); 1042 #endif 1043 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); 1044 } 1045 return hash__map_kernel_page(ea, pa, prot); 1046 } 1047 1048 static inline int __meminit vmemmap_create_mapping(unsigned long start, 1049 unsigned long page_size, 1050 unsigned long phys) 1051 { 1052 if (radix_enabled()) 1053 return radix__vmemmap_create_mapping(start, page_size, phys); 1054 return hash__vmemmap_create_mapping(start, page_size, phys); 1055 } 1056 1057 #ifdef CONFIG_MEMORY_HOTPLUG 1058 static inline void vmemmap_remove_mapping(unsigned long start, 1059 unsigned long page_size) 1060 { 1061 if (radix_enabled()) 1062 return radix__vmemmap_remove_mapping(start, page_size); 1063 return hash__vmemmap_remove_mapping(start, page_size); 1064 } 1065 #endif 1066 1067 static inline pte_t pmd_pte(pmd_t pmd) 1068 { 1069 return __pte_raw(pmd_raw(pmd)); 1070 } 1071 1072 static inline pmd_t pte_pmd(pte_t pte) 1073 { 1074 return __pmd_raw(pte_raw(pte)); 1075 } 1076 1077 static inline pte_t *pmdp_ptep(pmd_t *pmd) 1078 { 1079 return (pte_t *)pmd; 1080 } 1081 #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) 1082 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) 1083 #define pmd_young(pmd) pte_young(pmd_pte(pmd)) 1084 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) 1085 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) 1086 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) 1087 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) 1088 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) 1089 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) 1090 #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) 1091 #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) 1092 1093 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY 1094 #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) 1095 #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) 1096 #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) 1097 1098 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION 1099 #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) 1100 #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) 1101 #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) 1102 #endif 1103 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ 1104 1105 #ifdef CONFIG_NUMA_BALANCING 1106 static inline int pmd_protnone(pmd_t pmd) 1107 { 1108 return pte_protnone(pmd_pte(pmd)); 1109 } 1110 #endif /* CONFIG_NUMA_BALANCING */ 1111 1112 #define pmd_write(pmd) pte_write(pmd_pte(pmd)) 1113 #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) 1114 #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) 1115 1116 #define pmd_access_permitted pmd_access_permitted 1117 static inline bool pmd_access_permitted(pmd_t pmd, bool write) 1118 { 1119 /* 1120 * pmdp_invalidate sets this combination (which is not caught by 1121 * !pte_present() check in pte_access_permitted), to prevent 1122 * lock-free lookups, as part of the serialize_against_pte_lookup() 1123 * synchronisation. 1124 * 1125 * This also catches the case where the PTE's hardware PRESENT bit is 1126 * cleared while TLB is flushed, which is suboptimal but should not 1127 * be frequent. 1128 */ 1129 if (pmd_is_serializing(pmd)) 1130 return false; 1131 1132 return pte_access_permitted(pmd_pte(pmd), write); 1133 } 1134 1135 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 1136 extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); 1137 extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); 1138 extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); 1139 extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, 1140 pmd_t *pmdp, pmd_t pmd); 1141 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, 1142 unsigned long addr, pmd_t *pmd) 1143 { 1144 } 1145 1146 extern int hash__has_transparent_hugepage(void); 1147 static inline int has_transparent_hugepage(void) 1148 { 1149 if (radix_enabled()) 1150 return radix__has_transparent_hugepage(); 1151 return hash__has_transparent_hugepage(); 1152 } 1153 #define has_transparent_hugepage has_transparent_hugepage 1154 1155 static inline unsigned long 1156 pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, 1157 unsigned long clr, unsigned long set) 1158 { 1159 if (radix_enabled()) 1160 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1161 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); 1162 } 1163 1164 /* 1165 * returns true for pmd migration entries, THP, devmap, hugetlb 1166 * But compile time dependent on THP config 1167 */ 1168 static inline int pmd_large(pmd_t pmd) 1169 { 1170 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1171 } 1172 1173 /* 1174 * For radix we should always find H_PAGE_HASHPTE zero. Hence 1175 * the below will work for radix too 1176 */ 1177 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, 1178 unsigned long addr, pmd_t *pmdp) 1179 { 1180 unsigned long old; 1181 1182 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) 1183 return 0; 1184 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); 1185 return ((old & _PAGE_ACCESSED) != 0); 1186 } 1187 1188 #define __HAVE_ARCH_PMDP_SET_WRPROTECT 1189 static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, 1190 pmd_t *pmdp) 1191 { 1192 if (__pmd_write((*pmdp))) 1193 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); 1194 else if (unlikely(pmd_savedwrite(*pmdp))) 1195 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); 1196 } 1197 1198 /* 1199 * Only returns true for a THP. False for pmd migration entry. 1200 * We also need to return true when we come across a pte that 1201 * in between a thp split. While splitting THP, we mark the pmd 1202 * invalid (pmdp_invalidate()) before we set it with pte page 1203 * address. A pmd_trans_huge() check against a pmd entry during that time 1204 * should return true. 1205 * We should not call this on a hugetlb entry. We should check for HugeTLB 1206 * entry using vma->vm_flags 1207 * The page table walk rule is explained in Documentation/vm/transhuge.rst 1208 */ 1209 static inline int pmd_trans_huge(pmd_t pmd) 1210 { 1211 if (!pmd_present(pmd)) 1212 return false; 1213 1214 if (radix_enabled()) 1215 return radix__pmd_trans_huge(pmd); 1216 return hash__pmd_trans_huge(pmd); 1217 } 1218 1219 #define __HAVE_ARCH_PMD_SAME 1220 static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) 1221 { 1222 if (radix_enabled()) 1223 return radix__pmd_same(pmd_a, pmd_b); 1224 return hash__pmd_same(pmd_a, pmd_b); 1225 } 1226 1227 static inline pmd_t pmd_mkhuge(pmd_t pmd) 1228 { 1229 if (radix_enabled()) 1230 return radix__pmd_mkhuge(pmd); 1231 return hash__pmd_mkhuge(pmd); 1232 } 1233 1234 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS 1235 extern int pmdp_set_access_flags(struct vm_area_struct *vma, 1236 unsigned long address, pmd_t *pmdp, 1237 pmd_t entry, int dirty); 1238 1239 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG 1240 extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, 1241 unsigned long address, pmd_t *pmdp); 1242 1243 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR 1244 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, 1245 unsigned long addr, pmd_t *pmdp) 1246 { 1247 if (radix_enabled()) 1248 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); 1249 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); 1250 } 1251 1252 static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, 1253 unsigned long address, pmd_t *pmdp) 1254 { 1255 if (radix_enabled()) 1256 return radix__pmdp_collapse_flush(vma, address, pmdp); 1257 return hash__pmdp_collapse_flush(vma, address, pmdp); 1258 } 1259 #define pmdp_collapse_flush pmdp_collapse_flush 1260 1261 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL 1262 pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, 1263 unsigned long addr, 1264 pmd_t *pmdp, int full); 1265 1266 #define __HAVE_ARCH_PGTABLE_DEPOSIT 1267 static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, 1268 pmd_t *pmdp, pgtable_t pgtable) 1269 { 1270 if (radix_enabled()) 1271 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1272 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); 1273 } 1274 1275 #define __HAVE_ARCH_PGTABLE_WITHDRAW 1276 static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, 1277 pmd_t *pmdp) 1278 { 1279 if (radix_enabled()) 1280 return radix__pgtable_trans_huge_withdraw(mm, pmdp); 1281 return hash__pgtable_trans_huge_withdraw(mm, pmdp); 1282 } 1283 1284 #define __HAVE_ARCH_PMDP_INVALIDATE 1285 extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, 1286 pmd_t *pmdp); 1287 1288 #define pmd_move_must_withdraw pmd_move_must_withdraw 1289 struct spinlock; 1290 extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, 1291 struct spinlock *old_pmd_ptl, 1292 struct vm_area_struct *vma); 1293 /* 1294 * Hash translation mode use the deposited table to store hash pte 1295 * slot information. 1296 */ 1297 #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit 1298 static inline bool arch_needs_pgtable_deposit(void) 1299 { 1300 if (radix_enabled()) 1301 return false; 1302 return true; 1303 } 1304 extern void serialize_against_pte_lookup(struct mm_struct *mm); 1305 1306 1307 static inline pmd_t pmd_mkdevmap(pmd_t pmd) 1308 { 1309 if (radix_enabled()) 1310 return radix__pmd_mkdevmap(pmd); 1311 return hash__pmd_mkdevmap(pmd); 1312 } 1313 1314 static inline int pmd_devmap(pmd_t pmd) 1315 { 1316 return pte_devmap(pmd_pte(pmd)); 1317 } 1318 1319 static inline int pud_devmap(pud_t pud) 1320 { 1321 return 0; 1322 } 1323 1324 static inline int pgd_devmap(pgd_t pgd) 1325 { 1326 return 0; 1327 } 1328 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ 1329 1330 static inline int pud_pfn(pud_t pud) 1331 { 1332 /* 1333 * Currently all calls to pud_pfn() are gated around a pud_devmap() 1334 * check so this should never be used. If it grows another user we 1335 * want to know about it. 1336 */ 1337 BUILD_BUG(); 1338 return 0; 1339 } 1340 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION 1341 pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); 1342 void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, 1343 pte_t *, pte_t, pte_t); 1344 1345 /* 1346 * Returns true for a R -> RW upgrade of pte 1347 */ 1348 static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) 1349 { 1350 if (!(old_val & _PAGE_READ)) 1351 return false; 1352 1353 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) 1354 return true; 1355 1356 return false; 1357 } 1358 1359 /* 1360 * Like pmd_huge() and pmd_large(), but works regardless of config options 1361 */ 1362 #define pmd_is_leaf pmd_is_leaf 1363 #define pmd_leaf pmd_is_leaf 1364 static inline bool pmd_is_leaf(pmd_t pmd) 1365 { 1366 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); 1367 } 1368 1369 #define pud_is_leaf pud_is_leaf 1370 #define pud_leaf pud_is_leaf 1371 static inline bool pud_is_leaf(pud_t pud) 1372 { 1373 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); 1374 } 1375 1376 #define p4d_is_leaf p4d_is_leaf 1377 #define p4d_leaf p4d_is_leaf 1378 static inline bool p4d_is_leaf(p4d_t p4d) 1379 { 1380 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PTE)); 1381 } 1382 1383 #endif /* __ASSEMBLY__ */ 1384 #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ 1385