1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_ 3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_ 4 5 #include <asm/page.h> 6 7 #ifdef CONFIG_HUGETLB_PAGE 8 #define HAVE_ARCH_HUGETLB_UNMAPPED_AREA 9 #endif 10 #define HAVE_ARCH_UNMAPPED_AREA 11 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 12 13 #ifndef __ASSEMBLY__ 14 /* 15 * Page size definition 16 * 17 * shift : is the "PAGE_SHIFT" value for that page size 18 * sllp : is a bit mask with the value of SLB L || LP to be or'ed 19 * directly to a slbmte "vsid" value 20 * penc : is the HPTE encoding mask for the "LP" field: 21 * 22 */ 23 struct mmu_psize_def { 24 unsigned int shift; /* number of bits */ 25 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ 26 unsigned int tlbiel; /* tlbiel supported for that page size */ 27 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ 28 unsigned long h_rpt_pgsize; /* H_RPT_INVALIDATE page size encoding */ 29 union { 30 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ 31 unsigned long ap; /* Ap encoding used by PowerISA 3.0 */ 32 }; 33 }; 34 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 35 #endif /* __ASSEMBLY__ */ 36 37 /* 64-bit classic hash table MMU */ 38 #include <asm/book3s/64/mmu-hash.h> 39 40 #ifndef __ASSEMBLY__ 41 /* 42 * ISA 3.0 partition and process table entry format 43 */ 44 struct prtb_entry { 45 __be64 prtb0; 46 __be64 prtb1; 47 }; 48 extern struct prtb_entry *process_tb; 49 50 struct patb_entry { 51 __be64 patb0; 52 __be64 patb1; 53 }; 54 extern struct patb_entry *partition_tb; 55 56 /* Bits in patb0 field */ 57 #define PATB_HR (1UL << 63) 58 #define RPDB_MASK 0x0fffffffffffff00UL 59 #define RPDB_SHIFT (1UL << 8) 60 #define RTS1_SHIFT 61 /* top 2 bits of radix tree size */ 61 #define RTS1_MASK (3UL << RTS1_SHIFT) 62 #define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */ 63 #define RTS2_MASK (7UL << RTS2_SHIFT) 64 #define RPDS_MASK 0x1f /* root page dir. size field */ 65 66 /* Bits in patb1 field */ 67 #define PATB_GR (1UL << 63) /* guest uses radix; must match HR */ 68 #define PRTS_MASK 0x1f /* process table size field */ 69 #define PRTB_MASK 0x0ffffffffffff000UL 70 71 /* Number of supported LPID bits */ 72 extern unsigned int mmu_lpid_bits; 73 74 /* Number of supported PID bits */ 75 extern unsigned int mmu_pid_bits; 76 77 /* Base PID to allocate from */ 78 extern unsigned int mmu_base_pid; 79 80 /* 81 * memory block size used with radix translation. 82 */ 83 extern unsigned long __ro_after_init radix_mem_block_size; 84 85 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4) 86 #define PRTB_ENTRIES (1ul << mmu_pid_bits) 87 88 #define PATB_SIZE_SHIFT (mmu_lpid_bits + 4) 89 #define PATB_ENTRIES (1ul << mmu_lpid_bits) 90 91 typedef unsigned long mm_context_id_t; 92 struct spinlock; 93 94 /* Maximum possible number of NPUs in a system. */ 95 #define NV_MAX_NPUS 8 96 97 typedef struct { 98 union { 99 /* 100 * We use id as the PIDR content for radix. On hash we can use 101 * more than one id. The extended ids are used when we start 102 * having address above 512TB. We allocate one extended id 103 * for each 512TB. The new id is then used with the 49 bit 104 * EA to build a new VA. We always use ESID_BITS_1T_MASK bits 105 * from EA and new context ids to build the new VAs. 106 */ 107 mm_context_id_t id; 108 #ifdef CONFIG_PPC_64S_HASH_MMU 109 mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE]; 110 #endif 111 }; 112 113 /* Number of bits in the mm_cpumask */ 114 atomic_t active_cpus; 115 116 /* Number of users of the external (Nest) MMU */ 117 atomic_t copros; 118 119 /* Number of user space windows opened in process mm_context */ 120 atomic_t vas_windows; 121 122 #ifdef CONFIG_PPC_64S_HASH_MMU 123 struct hash_mm_context *hash_context; 124 #endif 125 126 void __user *vdso; 127 /* 128 * pagetable fragment support 129 */ 130 void *pte_frag; 131 void *pmd_frag; 132 #ifdef CONFIG_SPAPR_TCE_IOMMU 133 struct list_head iommu_group_mem_list; 134 #endif 135 136 #ifdef CONFIG_PPC_MEM_KEYS 137 /* 138 * Each bit represents one protection key. 139 * bit set -> key allocated 140 * bit unset -> key available for allocation 141 */ 142 u32 pkey_allocation_map; 143 s16 execute_only_pkey; /* key holding execute-only protection */ 144 #endif 145 } mm_context_t; 146 147 #ifdef CONFIG_PPC_64S_HASH_MMU 148 static inline u16 mm_ctx_user_psize(mm_context_t *ctx) 149 { 150 return ctx->hash_context->user_psize; 151 } 152 153 static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize) 154 { 155 ctx->hash_context->user_psize = user_psize; 156 } 157 158 static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx) 159 { 160 return ctx->hash_context->low_slices_psize; 161 } 162 163 static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx) 164 { 165 return ctx->hash_context->high_slices_psize; 166 } 167 168 static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx) 169 { 170 return ctx->hash_context->slb_addr_limit; 171 } 172 173 static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit) 174 { 175 ctx->hash_context->slb_addr_limit = limit; 176 } 177 178 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize) 179 { 180 #ifdef CONFIG_PPC_64K_PAGES 181 if (psize == MMU_PAGE_64K) 182 return &ctx->hash_context->mask_64k; 183 #endif 184 #ifdef CONFIG_HUGETLB_PAGE 185 if (psize == MMU_PAGE_16M) 186 return &ctx->hash_context->mask_16m; 187 if (psize == MMU_PAGE_16G) 188 return &ctx->hash_context->mask_16g; 189 #endif 190 BUG_ON(psize != MMU_PAGE_4K); 191 192 return &ctx->hash_context->mask_4k; 193 } 194 195 #ifdef CONFIG_PPC_SUBPAGE_PROT 196 static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx) 197 { 198 return ctx->hash_context->spt; 199 } 200 #endif 201 202 /* 203 * The current system page and segment sizes 204 */ 205 extern int mmu_virtual_psize; 206 extern int mmu_vmalloc_psize; 207 extern int mmu_io_psize; 208 #else /* CONFIG_PPC_64S_HASH_MMU */ 209 #ifdef CONFIG_PPC_64K_PAGES 210 #define mmu_virtual_psize MMU_PAGE_64K 211 #else 212 #define mmu_virtual_psize MMU_PAGE_4K 213 #endif 214 #endif 215 extern int mmu_linear_psize; 216 extern int mmu_vmemmap_psize; 217 218 /* MMU initialization */ 219 void mmu_early_init_devtree(void); 220 void hash__early_init_devtree(void); 221 void radix__early_init_devtree(void); 222 #ifdef CONFIG_PPC_PKEY 223 void pkey_early_init_devtree(void); 224 #else 225 static inline void pkey_early_init_devtree(void) {} 226 #endif 227 228 extern void hash__early_init_mmu(void); 229 extern void radix__early_init_mmu(void); 230 static inline void __init early_init_mmu(void) 231 { 232 if (radix_enabled()) 233 return radix__early_init_mmu(); 234 return hash__early_init_mmu(); 235 } 236 extern void hash__early_init_mmu_secondary(void); 237 extern void radix__early_init_mmu_secondary(void); 238 static inline void early_init_mmu_secondary(void) 239 { 240 if (radix_enabled()) 241 return radix__early_init_mmu_secondary(); 242 return hash__early_init_mmu_secondary(); 243 } 244 245 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, 246 phys_addr_t first_memblock_size); 247 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base, 248 phys_addr_t first_memblock_size) 249 { 250 /* 251 * Hash has more strict restrictions. At this point we don't 252 * know which translations we will pick. Hence go with hash 253 * restrictions. 254 */ 255 if (!early_radix_enabled()) 256 hash__setup_initial_memory_limit(first_memblock_base, 257 first_memblock_size); 258 } 259 260 #ifdef CONFIG_PPC_PSERIES 261 void __init radix_init_pseries(void); 262 #else 263 static inline void radix_init_pseries(void) { } 264 #endif 265 266 #ifdef CONFIG_HOTPLUG_CPU 267 #define arch_clear_mm_cpumask_cpu(cpu, mm) \ 268 do { \ 269 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { \ 270 atomic_dec(&(mm)->context.active_cpus); \ 271 cpumask_clear_cpu(cpu, mm_cpumask(mm)); \ 272 } \ 273 } while (0) 274 275 void cleanup_cpu_mmu_context(void); 276 #endif 277 278 #ifdef CONFIG_PPC_64S_HASH_MMU 279 static inline int get_user_context(mm_context_t *ctx, unsigned long ea) 280 { 281 int index = ea >> MAX_EA_BITS_PER_CONTEXT; 282 283 if (likely(index < ARRAY_SIZE(ctx->extended_id))) 284 return ctx->extended_id[index]; 285 286 /* should never happen */ 287 WARN_ON(1); 288 return 0; 289 } 290 291 static inline unsigned long get_user_vsid(mm_context_t *ctx, 292 unsigned long ea, int ssize) 293 { 294 unsigned long context = get_user_context(ctx, ea); 295 296 return get_vsid(context, ea, ssize); 297 } 298 #endif 299 300 #endif /* __ASSEMBLY__ */ 301 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */ 302